diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 4732 |
1 files changed, 2350 insertions, 2382 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 3d5089040..58986be27 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,173 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.823729 # Number of seconds simulated -sim_ticks 2823728611500 # Number of ticks simulated -final_tick 2823728611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.823751 # Number of seconds simulated +sim_ticks 2823750824500 # Number of ticks simulated +final_tick 2823750824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236626 # Simulator instruction rate (inst/s) -host_op_rate 287030 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5437492370 # Simulator tick rate (ticks/s) -host_mem_usage 592088 # Number of bytes of host memory used -host_seconds 519.31 # Real time elapsed on the host -sim_insts 122881667 # Number of instructions simulated -sim_ops 149056790 # Number of ops (including micro ops) simulated +host_inst_rate 186823 # Simulator instruction rate (inst/s) +host_op_rate 226618 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4292269892 # Simulator tick rate (ticks/s) +host_mem_usage 585968 # Number of bytes of host memory used +host_seconds 657.87 # Real time elapsed on the host +sim_insts 122905142 # Number of instructions simulated +sim_ops 149084969 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 538276 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3140708 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 542180 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3155236 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 122816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 897088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 122688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 900352 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 1792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 339840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2003776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 341632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1990912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4736 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 386816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 3512832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 381248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 3510400 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10950024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 538276 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 122816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 339840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 386816 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 10952712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 542180 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 122688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 341632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 381248 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1387748 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8235776 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8236736 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8253300 # Number of bytes written to this memory +system.physmem.bytes_written::total 8254260 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16864 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 49593 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16925 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 49820 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1919 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1917 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14068 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 28 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5310 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 31309 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 70 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 31108 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 74 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 6044 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 54888 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 5957 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 54850 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180067 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 128684 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180109 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 128699 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133065 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133080 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 190626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1112256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 192007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1117392 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 43494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 317696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 318850 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 120352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 709621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 120985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 705059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1677 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu3.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 136988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1244040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 135015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1243169 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3877860 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 190626 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 43494 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 120352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 136988 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491459 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2916632 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3878781 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 192007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 120985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 135015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 491456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2916949 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2922838 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2916632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2923155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2916949 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 190626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1118462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 192007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1123598 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 43494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 317696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 318850 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 120352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 709621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 120985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 705059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1677 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 136988 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1244040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 135015 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1243169 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6800697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 113588 # Number of read requests accepted -system.physmem.writeReqs 68931 # Number of write requests accepted -system.physmem.readBursts 113588 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 68931 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 7262464 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue -system.physmem.bytesWritten 4410816 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 7269632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4411584 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6801936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 113342 # Number of read requests accepted +system.physmem.writeReqs 68762 # Number of write requests accepted +system.physmem.readBursts 113342 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 68762 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 7247168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue +system.physmem.bytesWritten 4399872 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 7253888 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4400768 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 7537 # Per bank write bursts -system.physmem.perBankRdBursts::1 6789 # Per bank write bursts -system.physmem.perBankRdBursts::2 7399 # Per bank write bursts -system.physmem.perBankRdBursts::3 7485 # Per bank write bursts -system.physmem.perBankRdBursts::4 7337 # Per bank write bursts -system.physmem.perBankRdBursts::5 7010 # Per bank write bursts -system.physmem.perBankRdBursts::6 7617 # Per bank write bursts -system.physmem.perBankRdBursts::7 7715 # Per bank write bursts +system.physmem.perBankRdBursts::0 7506 # Per bank write bursts +system.physmem.perBankRdBursts::1 6787 # Per bank write bursts +system.physmem.perBankRdBursts::2 7407 # Per bank write bursts +system.physmem.perBankRdBursts::3 7543 # Per bank write bursts +system.physmem.perBankRdBursts::4 7335 # Per bank write bursts +system.physmem.perBankRdBursts::5 7022 # Per bank write bursts +system.physmem.perBankRdBursts::6 7619 # Per bank write bursts +system.physmem.perBankRdBursts::7 7707 # Per bank write bursts system.physmem.perBankRdBursts::8 6869 # Per bank write bursts -system.physmem.perBankRdBursts::9 7528 # Per bank write bursts -system.physmem.perBankRdBursts::10 7086 # Per bank write bursts -system.physmem.perBankRdBursts::11 6373 # Per bank write bursts +system.physmem.perBankRdBursts::9 7531 # Per bank write bursts +system.physmem.perBankRdBursts::10 6987 # Per bank write bursts +system.physmem.perBankRdBursts::11 6354 # Per bank write bursts system.physmem.perBankRdBursts::12 6401 # Per bank write bursts -system.physmem.perBankRdBursts::13 7208 # Per bank write bursts -system.physmem.perBankRdBursts::14 6839 # Per bank write bursts -system.physmem.perBankRdBursts::15 6283 # Per bank write bursts -system.physmem.perBankWrBursts::0 4402 # Per bank write bursts -system.physmem.perBankWrBursts::1 3960 # Per bank write bursts -system.physmem.perBankWrBursts::2 4483 # Per bank write bursts -system.physmem.perBankWrBursts::3 4623 # Per bank write bursts -system.physmem.perBankWrBursts::4 4313 # Per bank write bursts -system.physmem.perBankWrBursts::5 4310 # Per bank write bursts -system.physmem.perBankWrBursts::6 4616 # Per bank write bursts -system.physmem.perBankWrBursts::7 4482 # Per bank write bursts -system.physmem.perBankWrBursts::8 4162 # Per bank write bursts +system.physmem.perBankRdBursts::13 7189 # Per bank write bursts +system.physmem.perBankRdBursts::14 6831 # Per bank write bursts +system.physmem.perBankRdBursts::15 6149 # Per bank write bursts +system.physmem.perBankWrBursts::0 4366 # Per bank write bursts +system.physmem.perBankWrBursts::1 3966 # Per bank write bursts +system.physmem.perBankWrBursts::2 4487 # Per bank write bursts +system.physmem.perBankWrBursts::3 4689 # Per bank write bursts +system.physmem.perBankWrBursts::4 4379 # Per bank write bursts +system.physmem.perBankWrBursts::5 4312 # Per bank write bursts +system.physmem.perBankWrBursts::6 4615 # Per bank write bursts +system.physmem.perBankWrBursts::7 4485 # Per bank write bursts +system.physmem.perBankWrBursts::8 4160 # Per bank write bursts system.physmem.perBankWrBursts::9 4849 # Per bank write bursts -system.physmem.perBankWrBursts::10 4455 # Per bank write bursts -system.physmem.perBankWrBursts::11 3923 # Per bank write bursts -system.physmem.perBankWrBursts::12 3821 # Per bank write bursts -system.physmem.perBankWrBursts::13 4641 # Per bank write bursts -system.physmem.perBankWrBursts::14 4142 # Per bank write bursts -system.physmem.perBankWrBursts::15 3737 # Per bank write bursts +system.physmem.perBankWrBursts::10 4371 # Per bank write bursts +system.physmem.perBankWrBursts::11 3905 # Per bank write bursts +system.physmem.perBankWrBursts::12 3814 # Per bank write bursts +system.physmem.perBankWrBursts::13 4615 # Per bank write bursts +system.physmem.perBankWrBursts::14 4128 # Per bank write bursts +system.physmem.perBankWrBursts::15 3607 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2822156484500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 2822178697500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 113588 # Read request sizes (log2) +system.physmem.readPktSize::6 113342 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 68931 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 85837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 24551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 68762 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 85611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 24487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -195,130 +191,131 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 68 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 64 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 63 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 63 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 29 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39396 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.306224 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.340600 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.184189 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15747 39.97% 39.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9259 23.50% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3829 9.72% 73.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2133 5.41% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1523 3.87% 82.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 982 2.49% 84.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 643 1.63% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 644 1.63% 88.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4636 11.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39396 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3632 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 31.238987 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 631.062126 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 3630 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 39262 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.647547 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.649192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.383393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15575 39.67% 39.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9414 23.98% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3760 9.58% 73.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2064 5.26% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1515 3.86% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1018 2.59% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 639 1.63% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 658 1.68% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4619 11.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39262 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3618 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 31.293256 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 632.321482 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 3616 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3632 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3632 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.975496 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.811099 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.084616 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 8 0.22% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.06% 0.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.06% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 6 0.17% 0.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3236 89.10% 89.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 53 1.46% 91.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 53 1.46% 92.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 39 1.07% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 77 2.12% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 40 1.10% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 9 0.25% 97.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.28% 97.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 6 0.17% 97.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.17% 97.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.08% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.08% 97.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 57 1.57% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.06% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.11% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.08% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.03% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.06% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.14% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3632 # Writes before turning the bus around for reads -system.physmem.totQLat 1343214500 # Total ticks spent queuing -system.physmem.totMemAccLat 3470889500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 567380000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11836.99 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 3618 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3618 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.001658 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.828073 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.498575 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 5 0.14% 0.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 2 0.06% 0.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.06% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 2 0.06% 0.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3234 89.39% 89.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 43 1.19% 90.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 55 1.52% 92.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 37 1.02% 93.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 88 2.43% 95.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 33 0.91% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 11 0.30% 97.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.30% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 5 0.14% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.19% 97.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.06% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.14% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 54 1.49% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.08% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.11% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.06% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.03% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.03% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.06% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.08% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3618 # Writes before turning the bus around for reads +system.physmem.totQLat 1331922750 # Total ticks spent queuing +system.physmem.totMemAccLat 3455116500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 566185000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11762.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30586.99 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30512.26 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.57 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.57 # Average system read bandwidth in MiByte/s @@ -328,42 +325,42 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.43 # Average write queue length when enqueuing -system.physmem.readRowHits 93570 # Number of row buffer hits during reads -system.physmem.writeRowHits 49429 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.71 # Row buffer hit rate for writes -system.physmem.avgGap 15462261.38 # Average gap between requests -system.physmem.pageHitRate 78.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 157845240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 85919625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 459334200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 228024720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179708830080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 71920006785 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1621544131500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1874104092150 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.482602 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2641247054000 # Time in different power states -system.physmem_0.memoryStateTime::REF 91875680000 # Time in different power states +system.physmem.avgWrQLen 19.94 # Average write queue length when enqueuing +system.physmem.readRowHits 93386 # Number of row buffer hits during reads +system.physmem.writeRowHits 49336 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.75 # Row buffer hit rate for writes +system.physmem.avgGap 15497620.58 # Average gap between requests +system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 157701600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 85878375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 459622800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 228737520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179710355760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 72061196355 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1617839664000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1870543156410 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.633364 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2641056208250 # Time in different power states +system.physmem_0.memoryStateTime::REF 91876460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18345210500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18550863000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139988520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76201125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 425778600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 218570400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179708830080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 71085141180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1620445714500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1872100224405 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.494295 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2642466740000 # Time in different power states -system.physmem_1.memoryStateTime::REF 91875680000 # Time in different power states +system.physmem_1.actEnergy 139119120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 75726750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 423618000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 216749520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179710355760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 71208324450 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1622163329250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1873937222850 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.425184 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2642291372250 # Time in different power states +system.physmem_1.memoryStateTime::REF 91876460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17119297500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17320352000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -376,9 +373,9 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -386,7 +383,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -416,49 +413,49 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 4971 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 4971 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 4971 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 4971 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 4971 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 56876140626 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.265788 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -15117011624 -26.58% -26.58% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993152250 126.58% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 56876140626 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2795 68.19% 68.19% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1304 31.81% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4099 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4971 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 4996 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 4996 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 4996 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 4996 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 4996 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 56881650376 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.265666 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -15111501624 -26.57% -26.57% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993152000 126.57% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 56881650376 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2808 68.21% 68.21% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1309 31.79% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4117 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4996 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4971 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4099 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4996 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4117 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4099 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9070 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4117 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9113 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12098971 # DTB read hits -system.cpu0.dtb.read_misses 4249 # DTB read misses -system.cpu0.dtb.write_hits 9143699 # DTB write hits +system.cpu0.dtb.read_hits 12099084 # DTB read hits +system.cpu0.dtb.read_misses 4274 # DTB read misses +system.cpu0.dtb.write_hits 9151888 # DTB write hits system.cpu0.dtb.write_misses 722 # DTB write misses system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 363 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2759 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2772 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 830 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 821 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 174 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12103220 # DTB read accesses -system.cpu0.dtb.write_accesses 9144421 # DTB write accesses +system.cpu0.dtb.perms_faults 173 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12103358 # DTB read accesses +system.cpu0.dtb.write_accesses 9152610 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21242670 # DTB hits -system.cpu0.dtb.misses 4971 # DTB misses -system.cpu0.dtb.accesses 21247641 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 21250972 # DTB hits +system.cpu0.dtb.misses 4996 # DTB misses +system.cpu0.dtb.accesses 21255968 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -488,660 +485,660 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 2431 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2431 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2431 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2431 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2431 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 56876140626 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.265790 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -15117125624 -26.58% -26.58% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993266250 126.58% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 56876140626 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1312 74.72% 74.72% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 444 25.28% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1756 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 2442 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2442 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2442 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2442 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2442 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 56881650376 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.265668 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -15111616124 -26.57% -26.57% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993266500 126.57% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 56881650376 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1322 74.86% 74.86% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 444 25.14% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1766 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2431 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2431 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2442 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2442 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1756 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1756 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4187 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56920666 # ITB inst hits -system.cpu0.itb.inst_misses 2431 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1766 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1766 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4208 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56923800 # ITB inst hits +system.cpu0.itb.inst_misses 2442 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 363 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1695 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1703 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56923097 # ITB inst accesses -system.cpu0.itb.hits 56920666 # DTB hits -system.cpu0.itb.misses 2431 # DTB misses -system.cpu0.itb.accesses 56923097 # DTB accesses -system.cpu0.numPwrStateTransitions 2544 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1272 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 2140717570.690252 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 53412982832.831551 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1258 98.90% 98.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 10 0.79% 99.69% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.08% 99.76% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 56926242 # ITB inst accesses +system.cpu0.itb.hits 56923800 # DTB hits +system.cpu0.itb.misses 2442 # DTB misses +system.cpu0.itb.accesses 56926242 # DTB accesses +system.cpu0.numPwrStateTransitions 2560 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1280 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 2127325768.303125 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 53245910996.367020 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1265 98.83% 98.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 11 0.86% 99.69% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.08% 99.77% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.08% 99.84% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.08% 99.92% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 1 0.08% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1799910941001 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1272 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 100735861582 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2722992749918 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 68768248 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 1799911049001 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1280 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 100773841072 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2722976983428 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 68778258 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3086 # number of quiesce instructions executed -system.cpu0.committedInsts 55456471 # Number of instructions committed -system.cpu0.committedOps 67221308 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58995481 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4380 # Number of float alu accesses -system.cpu0.num_func_calls 5787158 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7357632 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58995481 # number of integer instructions -system.cpu0.num_fp_insts 4380 # number of float instructions -system.cpu0.num_int_register_reads 108769217 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41129875 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3339 # number of times the floating registers were read +system.cpu0.committedInsts 55461787 # Number of instructions committed +system.cpu0.committedOps 67232154 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 59006752 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4424 # Number of float alu accesses +system.cpu0.num_func_calls 5784619 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7357566 # number of instructions that are conditional controls +system.cpu0.num_int_insts 59006752 # number of integer instructions +system.cpu0.num_fp_insts 4424 # number of float instructions +system.cpu0.num_int_register_reads 108790658 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41133474 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3383 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1042 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 204568240 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 24713959 # number of times the CC registers were written -system.cpu0.num_mem_refs 21830038 # number of memory refs -system.cpu0.num_load_insts 12248052 # Number of load instructions -system.cpu0.num_store_insts 9581986 # Number of store instructions -system.cpu0.num_idle_cycles 64949431.464966 # Number of idle cycles -system.cpu0.num_busy_cycles 3818816.535034 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055532 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944468 # Percentage of idle cycles -system.cpu0.Branches 13461051 # Number of branches fetched +system.cpu0.num_cc_register_reads 204599031 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 24717436 # number of times the CC registers were written +system.cpu0.num_mem_refs 21838245 # number of memory refs +system.cpu0.num_load_insts 12248234 # Number of load instructions +system.cpu0.num_store_insts 9590011 # Number of store instructions +system.cpu0.num_idle_cycles 64958382.766609 # Number of idle cycles +system.cpu0.num_busy_cycles 3819875.233391 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055539 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944461 # Percentage of idle cycles +system.cpu0.Branches 13458694 # Number of branches fetched system.cpu0.op_class::No_OpClass 2178 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46425629 67.96% 67.96% # Class of executed instruction -system.cpu0.op_class::IntMult 50781 0.07% 68.04% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3880 0.01% 68.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 46427379 67.95% 67.96% # Class of executed instruction +system.cpu0.op_class::IntMult 50783 0.07% 68.03% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3883 0.01% 68.04% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.04% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.04% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::MemRead 12248052 17.93% 85.97% # Class of executed instruction -system.cpu0.op_class::MemWrite 9581986 14.03% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 12248234 17.93% 85.96% # Class of executed instruction +system.cpu0.op_class::MemWrite 9590011 14.04% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68312506 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 833701 # number of replacements +system.cpu0.op_class::total 68322468 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 833257 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.996712 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 45908566 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 834213 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.032187 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 45925455 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 833769 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.081749 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.062806 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.552141 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.736312 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 13.645453 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941529 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022563 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009251 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.026651 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.041518 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.532588 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.805161 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 13.617445 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941487 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022525 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009385 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.026597 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193086177 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193086177 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 11466814 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 3604015 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4048059 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6693191 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25812079 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 8805127 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 2681872 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3150720 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 4155645 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18793364 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178315 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 56771 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 67457 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 85993 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 388536 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 216736 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 75016 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70705 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 88525 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 450982 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 217763 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76661 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73616 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 92634 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460674 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20271941 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 6285887 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7198779 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 10848836 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44605443 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20450256 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 6342658 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7266236 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 10934829 # number of overall hits -system.cpu0.dcache.overall_hits::total 44993979 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170779 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 51895 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 83860 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 219596 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 526130 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 112315 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 34838 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 103940 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 1226727 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1477820 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 53930 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 19459 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 19330 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 42725 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 135444 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3695 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2338 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3825 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8068 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17926 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 27 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 283094 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 86733 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 187800 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 1446323 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2003950 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 337024 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 106192 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 207130 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 1489048 # number of overall misses -system.cpu0.dcache.overall_misses::total 2139394 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 835936000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1210061000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3349856000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5395853000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1273084500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 5046790496 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 61121825312 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 67441700308 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28644500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 55618500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 110733000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 194996000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 615000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 615000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 2109020500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 6256851496 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu3.data 64471681312 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 72837553308 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 2109020500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 6256851496 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu3.data 64471681312 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 72837553308 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11637593 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 3655910 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4131919 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 6912787 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26338209 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 8917442 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 2716710 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3254660 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu3.data 5382372 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 20271184 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 232245 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 76230 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 86787 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 128718 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 523980 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 220431 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 77354 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 74530 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 96593 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 468908 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 217765 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 76661 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73616 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 92661 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460703 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 20555035 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 6372620 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7386579 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 12295159 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 46609393 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 20787280 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 6448850 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7473366 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 12423877 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 47133373 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014675 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.014195 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.020296 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031767 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019976 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012595 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.012824 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.031936 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.227916 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.072903 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.232212 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.255267 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.222729 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.331927 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.258491 # 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miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019796 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012601 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.012863 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.031644 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.227397 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.072739 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.231660 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.256695 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.219973 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.331536 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.257884 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016783 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.030405 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050648 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.083898 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038210 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000005 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000216 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013780 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013680 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.024497 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.117383 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.042820 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016216 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.016569 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.026762 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.119595 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045211 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16098.086903 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14546.422110 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15206.326995 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10214.182170 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36539.438713 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48814.196996 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 49582.195398 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45437.858814 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12242.237346 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14975.855665 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13738.383589 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10962.073007 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 22525 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21452.380952 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24299.707602 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 34021.446398 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44337.605217 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36235.438935 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19824.480575 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30781.544090 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43067.948553 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33937.592696 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 336311 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 29493 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 12565 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 679 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.765698 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 43.435935 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 691735 # number of writebacks +system.cpu0.dcache.writebacks::total 691735 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 104 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 8524 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 107233 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 115861 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 47971 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1130213 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1178184 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1643 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2350 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5425 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9418 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 3034 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 108026 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 111164 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 47325 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1128149 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1175474 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1653 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2318 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5313 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9284 # number of LoadLockedReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu1.data 104 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 56495 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu3.data 1237446 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1294045 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 50359 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu3.data 1236175 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1286638 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu1.data 104 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 56495 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu3.data 1237446 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1294045 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 51791 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 75336 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112363 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 239490 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 34838 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 55969 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 96514 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 187321 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 19125 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 15868 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 29717 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 64710 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 695 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1475 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2643 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4813 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 27 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 86629 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 131305 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu3.data 208877 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 426811 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 105754 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 147173 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu3.data 238594 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 491521 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 3424 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 7115 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7790 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18329 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2828 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5194 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6258 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14280 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 6252 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12309 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 14048 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32609 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 782633000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1020579500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1612657500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3415870000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238246500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2646664500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4858846947 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8743757947 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 247386000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 228071000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 457588500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 933045500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8958000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 27255500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 37981000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 74194500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 588000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 588000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2020879500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3667244000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6471504447 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12159627947 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2268265500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3895315000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 6929092947 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13092673447 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 601507000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1484874500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1676185500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3762567000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 601507000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1484874500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1676185500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3762567000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014166 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018233 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016254 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009093 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012824 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017197 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017931 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009241 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.250885 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.182838 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.230869 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123497 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.008985 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019791 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.027362 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010264 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000291 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000059 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013594 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017776 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016989 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.009157 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016399 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019693 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019204 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.010428 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15111.370701 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13547.035946 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14352.211137 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14263.100756 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35542.984672 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47288.043381 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50343.441853 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46677.937588 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12935.215686 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14373.014873 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15398.206414 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14418.876526 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12889.208633 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 18478.305085 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14370.412410 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15415.437357 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 21777.777778 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21777.777778 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23327.979083 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27929.203001 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30982.369753 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28489.490540 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21448.507858 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26467.592561 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29041.354548 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26637.058126 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175673.773364 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 208696.345748 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215171.437741 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205279.447869 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96210.332694 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 120633.235844 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 119318.443907 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115384.311080 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1971000 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.470268 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 93100003 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1971512 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 47.222641 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12494493500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 436.802699 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 12.961360 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 25.140810 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 36.565399 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.853130 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025315 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.049103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.071417 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998965 # Average percentage of cache occupancy +system.cpu0.dcache.overall_mshr_hits::cpu2.data 50359 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu3.data 1236175 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1286638 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 52115 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 74903 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112442 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 239460 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 34991 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 55281 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 96449 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 186721 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 19358 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 15598 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 29608 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 64564 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 698 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1451 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2779 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4928 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 20 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 87106 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 130184 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu3.data 208891 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 426181 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 106464 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 145782 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu3.data 238499 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 490745 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 3449 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 7107 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7761 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18317 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2842 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5190 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6229 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14261 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 6291 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12297 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 13990 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32578 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 786951500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1017548500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1612818000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3417318000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1243560500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2630255500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4839784419 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8713600419 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 249854500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 223680000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 457627500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 931162000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9093000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 27428500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 39926500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76448000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 430500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 430500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2030512000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3647804000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6452602419 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12130918419 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2280366500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3871484000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 6910229919 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13062080419 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 605119000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1489074500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1668784000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3762977500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 605119000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1489074500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1668784000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3762977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014260 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018147 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016236 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009089 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012863 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017049 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017910 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009210 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.252406 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.180557 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.230420 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123190 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.009027 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019499 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.028813 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010510 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000216 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000043 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013664 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017664 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016968 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.009142 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016502 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019551 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019173 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.010410 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15100.287825 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13584.883115 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14343.554899 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14270.934603 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35539.438713 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47579.738066 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50179.726270 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46666.418983 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12907.041017 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14340.300038 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15456.211159 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14422.309646 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13027.220630 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 18903.170227 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14367.218424 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15512.987013 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 21525 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21525 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23310.816706 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28020.371167 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30889.805779 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28464.240356 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21419.132289 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26556.666804 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 28973.831836 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26616.838519 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175447.665990 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 209522.231603 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215021.775544 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205436.343288 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96188.046416 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 121092.502236 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 119284.060043 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115506.706980 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1969655 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.471697 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 93089501 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1970167 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 47.249548 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 12499304500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 436.731895 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 12.926501 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 25.039106 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 36.774196 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.852992 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025247 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.048905 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu3.inst 0.071825 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998968 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 260 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 97085383 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 97085383 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 56179314 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 17648655 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 9977787 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu3.inst 9294247 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 93100003 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56179314 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 17648655 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 9977787 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu3.inst 9294247 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 93100003 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56179314 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 17648655 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 9977787 # number of overall hits -system.cpu0.icache.overall_hits::cpu3.inst 9294247 # number of overall hits -system.cpu0.icache.overall_hits::total 93100003 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 743108 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 211772 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 473406 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu3.inst 585545 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2013831 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 743108 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 211772 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 473406 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu3.inst 585545 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2013831 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 743108 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 211772 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 473406 # number of overall misses -system.cpu0.icache.overall_misses::cpu3.inst 585545 # number of overall misses -system.cpu0.icache.overall_misses::total 2013831 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2898883500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6546923000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 7956012985 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 17401819485 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2898883500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 6546923000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu3.inst 7956012985 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 17401819485 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2898883500 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2702402500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6037100500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7028496990 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 15767999990 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011933 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045007 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.054960 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012897 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011933 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045007 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.054960 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012897 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011933 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045007 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054960 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012897 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12690.970184 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12848.776652 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12926.779771 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12855.958306 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12690.970184 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12848.776652 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12926.779771 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12855.958306 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12690.970184 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12848.776652 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12926.779771 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12855.958306 # average overall mshr miss latency +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1171,63 +1168,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 2016 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 2016 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 564 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1452 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 2016 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 2016 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 2016 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1645 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12118.844985 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10271.833283 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6851.972198 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 2014 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 2014 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 554 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1460 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 2014 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 2014 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 2014 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1648 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12287.621359 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10419.476914 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6887.691629 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.91% 0.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-6143 468 28.45% 29.36% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::6144-8191 121 7.36% 36.72% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::10240-12287 510 31.00% 67.72% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-14335 106 6.44% 74.16% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::14336-16383 70 4.26% 78.42% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-18431 12 0.73% 79.15% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::22528-24575 321 19.51% 98.66% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-26623 22 1.34% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1645 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-6143 458 27.79% 28.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::6144-8191 116 7.04% 35.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::10240-12287 507 30.76% 66.50% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-14335 107 6.49% 73.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::14336-16383 75 4.55% 77.55% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-18431 12 0.73% 78.28% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::22528-24575 336 20.39% 98.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-26623 22 1.33% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1648 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1089 66.20% 66.20% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 556 33.80% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1645 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2016 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1102 66.87% 66.87% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 546 33.13% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1648 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2014 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2016 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1645 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2014 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1648 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1645 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3661 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1648 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3662 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3812918 # DTB read hits -system.cpu1.dtb.read_misses 1745 # DTB read misses -system.cpu1.dtb.write_hits 2796286 # DTB write hits -system.cpu1.dtb.write_misses 271 # DTB write misses -system.cpu1.dtb.flush_tlb 154 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 3812187 # DTB read hits +system.cpu1.dtb.read_misses 1742 # DTB read misses +system.cpu1.dtb.write_hits 2799792 # DTB write hits +system.cpu1.dtb.write_misses 272 # DTB write misses +system.cpu1.dtb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 180 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1245 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1235 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 243 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 241 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 87 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3814663 # DTB read accesses -system.cpu1.dtb.write_accesses 2796557 # DTB write accesses +system.cpu1.dtb.perms_faults 89 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3813929 # DTB read accesses +system.cpu1.dtb.write_accesses 2800064 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6609204 # DTB hits -system.cpu1.dtb.misses 2016 # DTB misses -system.cpu1.dtb.accesses 6611220 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 6611979 # DTB hits +system.cpu1.dtb.misses 2014 # DTB misses +system.cpu1.dtb.accesses 6613993 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1257,148 +1254,148 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 1033 # Table walker walks requested system.cpu1.itb.walker.walksShort 1033 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 205 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 828 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 201 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 832 # Level at which table walker walks with short descriptors terminate system.cpu1.itb.walker.walkWaitTime::samples 1033 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::0 1033 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1033 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 765 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12816.993464 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10782.034364 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7152.863364 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 258 33.73% 33.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 199 26.01% 59.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 58 7.58% 67.32% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 58 7.58% 74.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-18431 1 0.13% 75.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 183 23.92% 98.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-26623 8 1.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 765 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::samples 763 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12903.669725 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10877.320310 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7130.133618 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 252 33.03% 33.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 198 25.95% 58.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 53 6.95% 65.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 68 8.91% 74.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-18431 1 0.13% 74.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 185 24.25% 99.21% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-26623 6 0.79% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 763 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 560 73.20% 73.20% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 205 26.80% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 765 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 562 73.66% 73.66% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 201 26.34% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 763 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1033 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1033 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 765 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 765 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1798 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 17860427 # ITB inst hits +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 763 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 763 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1796 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 17843952 # ITB inst hits system.cpu1.itb.inst_misses 1033 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 154 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 180 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 732 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 730 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 17861460 # ITB inst accesses -system.cpu1.itb.hits 17860427 # DTB hits +system.cpu1.itb.inst_accesses 17844985 # ITB inst accesses +system.cpu1.itb.hits 17843952 # DTB hits system.cpu1.itb.misses 1033 # DTB misses -system.cpu1.itb.accesses 17861460 # DTB accesses -system.cpu1.numPwrStateTransitions 700 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 350 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 887126528.134286 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 11718884453.100866 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 345 98.57% 98.57% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 3 0.86% 99.43% # Distribution of time spent in the clock gated state +system.cpu1.itb.accesses 17844985 # DTB accesses +system.cpu1.numPwrStateTransitions 704 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 352 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 882103975.423295 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 11685879500.755745 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 347 98.58% 98.58% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 3 0.85% 99.43% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.57% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 156797355001 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 350 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 2513234326653 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 310494284847 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 143797366 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 156798535501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 352 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 2513250225151 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 310500599349 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 143831015 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 17268414 # Number of instructions committed -system.cpu1.committedOps 20827213 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18584422 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1582 # Number of float alu accesses -system.cpu1.num_func_calls 1992181 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2177842 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18584422 # number of integer instructions -system.cpu1.num_fp_insts 1582 # number of float instructions -system.cpu1.num_int_register_reads 34431709 # number of times the integer registers were read -system.cpu1.num_int_register_writes 13029372 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1129 # number of times the floating registers were read +system.cpu1.committedInsts 17251961 # Number of instructions committed +system.cpu1.committedOps 20817165 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18580086 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1666 # Number of float alu accesses +system.cpu1.num_func_calls 1994134 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2173480 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18580086 # number of integer instructions +system.cpu1.num_fp_insts 1666 # number of float instructions +system.cpu1.num_int_register_reads 34429785 # number of times the integer registers were read +system.cpu1.num_int_register_writes 13026660 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1213 # number of times the floating registers were read system.cpu1.num_fp_register_writes 454 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 75826477 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7417953 # number of times the CC registers were written -system.cpu1.num_mem_refs 6811480 # number of memory refs -system.cpu1.num_load_insts 3856412 # Number of load instructions -system.cpu1.num_store_insts 2955068 # Number of store instructions -system.cpu1.num_idle_cycles 136802879.005961 # Number of idle cycles -system.cpu1.num_busy_cycles 6994486.994039 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048641 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951359 # Percentage of idle cycles -system.cpu1.Branches 4283216 # Number of branches fetched -system.cpu1.op_class::No_OpClass 49 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14611363 68.15% 68.15% # Class of executed instruction -system.cpu1.op_class::IntMult 16029 0.07% 68.23% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 979 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::MemRead 3856412 17.99% 86.22% # Class of executed instruction -system.cpu1.op_class::MemWrite 2955068 13.78% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 75796626 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7400275 # number of times the CC registers were written +system.cpu1.num_mem_refs 6814833 # number of memory refs +system.cpu1.num_load_insts 3855659 # Number of load instructions +system.cpu1.num_store_insts 2959174 # Number of store instructions +system.cpu1.num_idle_cycles 136834040.067403 # Number of idle cycles +system.cpu1.num_busy_cycles 6996974.932597 # Number of busy cycles +system.cpu1.not_idle_fraction 0.048647 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.951353 # Percentage of idle cycles +system.cpu1.Branches 4280023 # Number of branches fetched +system.cpu1.op_class::No_OpClass 48 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14598901 68.12% 68.12% # Class of executed instruction +system.cpu1.op_class::IntMult 16055 0.07% 68.20% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 990 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::MemRead 3855659 17.99% 86.19% # Class of executed instruction +system.cpu1.op_class::MemWrite 2959174 13.81% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21439900 # Class of executed instruction -system.cpu2.branchPred.lookups 5566129 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2825980 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 493463 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3182486 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 1660276 # Number of BTB hits +system.cpu1.op_class::total 21430827 # Class of executed instruction +system.cpu2.branchPred.lookups 5563915 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2829451 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 493242 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3244476 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 1661186 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 52.169153 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1582499 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 327011 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 671898 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 638941 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 32957 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 21982 # Number of mispredicted indirect branches. -system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu2.branchPred.BTBHitPct 51.200440 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1571960 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 328162 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 674670 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 641704 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 32966 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 22004 # Number of mispredicted indirect branches. +system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1428,59 +1425,59 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu2.dtb.walker.walks 11822 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 11822 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7337 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4485 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 11822 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 11822 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 11822 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2048 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 12710.205078 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 10939.246339 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 6922.657260 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 574 28.03% 28.03% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1046 51.07% 79.10% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 414 20.21% 99.32% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::24576-32767 12 0.59% 99.90% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.walker.walks 11911 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 11911 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7385 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4526 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 11911 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 11911 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 11911 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2027 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 12784.410459 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 11026.371953 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 6894.594481 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 547 26.99% 26.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1059 52.24% 79.23% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 401 19.78% 99.01% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::24576-32767 18 0.89% 99.90% # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.10% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2048 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 2000043000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0 2000043000 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 2000043000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1270 62.01% 62.01% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 778 37.99% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2048 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 11822 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkCompletionTime::total 2027 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 2000042500 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0 2000042500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 2000042500 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 1245 61.42% 61.42% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 782 38.58% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2027 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 11911 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 11822 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2048 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 11911 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2027 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2048 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 13870 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2027 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 13938 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4336552 # DTB read hits -system.cpu2.dtb.read_misses 10662 # DTB read misses -system.cpu2.dtb.write_hits 3355101 # DTB write hits -system.cpu2.dtb.write_misses 1160 # DTB write misses -system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 4327855 # DTB read hits +system.cpu2.dtb.read_misses 10705 # DTB read misses +system.cpu2.dtb.write_hits 3342614 # DTB write hits +system.cpu2.dtb.write_misses 1206 # DTB write misses +system.cpu2.dtb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 143 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1416 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 270 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 1399 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 245 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 127 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4347214 # DTB read accesses -system.cpu2.dtb.write_accesses 3356261 # DTB write accesses +system.cpu2.dtb.perms_faults 123 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4338560 # DTB read accesses +system.cpu2.dtb.write_accesses 3343820 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 7691653 # DTB hits -system.cpu2.dtb.misses 11822 # DTB misses -system.cpu2.dtb.accesses 7703475 # DTB accesses -system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.hits 7670469 # DTB hits +system.cpu2.dtb.misses 11911 # DTB misses +system.cpu2.dtb.accesses 7682380 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1510,139 +1507,140 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu2.itb.walker.walks 1331 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1331 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 253 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1078 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1331 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1331 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1331 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 850 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12864.705882 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 11157.048638 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6541.427390 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 256 30.12% 30.12% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 237 27.88% 58.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 63 7.41% 65.41% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 116 13.65% 79.06% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 176 20.71% 99.76% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu2.itb.walker.walks 1348 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1348 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 252 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1096 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1348 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1348 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1348 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 848 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 13074.292453 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 11434.302344 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6448.856060 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 240 28.30% 28.30% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::6144-8191 2 0.24% 28.54% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 241 28.42% 56.96% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 61 7.19% 64.15% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 126 14.86% 79.01% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 176 20.75% 99.76% # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walkCompletionTime::24576-26623 2 0.24% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 850 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 2000028500 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 2000028500 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 2000028500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 607 71.41% 71.41% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 243 28.59% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 850 # Table walker page sizes translated +system.cpu2.itb.walker.walkCompletionTime::total 848 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 2000028000 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2000028000 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 2000028000 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 600 70.75% 70.75% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 248 29.25% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 848 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1331 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1331 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1348 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1348 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 850 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 850 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2181 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10452986 # ITB inst hits -system.cpu2.itb.inst_misses 1331 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 848 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 848 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2196 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10441487 # ITB inst hits +system.cpu2.itb.inst_misses 1348 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 143 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 822 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 821 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1709 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1710 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10454317 # ITB inst accesses -system.cpu2.itb.hits 10452986 # DTB hits -system.cpu2.itb.misses 1331 # DTB misses -system.cpu2.itb.accesses 10454317 # DTB accesses -system.cpu2.numPwrStateTransitions 1086 # Number of power state transitions -system.cpu2.pwrStateClkGateDist::samples 543 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::mean 5039016894.569060 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::stdev 41056292942.981247 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::underflows 498 91.71% 91.71% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1000-5e+10 38 7.00% 98.71% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::5e+10-1e+11 1 0.18% 98.90% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 1 0.18% 99.08% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 1 0.18% 99.26% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 1 0.18% 99.45% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 2 0.37% 99.82% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.18% 100.00% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::max_value 500052575501 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::total 543 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateResidencyTicks::ON 87542437749 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::CLK_GATED 2736186173751 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 141973763 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 10442835 # ITB inst accesses +system.cpu2.itb.hits 10441487 # DTB hits +system.cpu2.itb.misses 1348 # DTB misses +system.cpu2.itb.accesses 10442835 # DTB accesses +system.cpu2.numPwrStateTransitions 1074 # Number of power state transitions +system.cpu2.pwrStateClkGateDist::samples 537 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::mean 5095328839.376163 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::stdev 41281959005.190056 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::underflows 492 91.62% 91.62% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1000-5e+10 38 7.08% 98.70% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::5e+10-1e+11 1 0.19% 98.88% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 1 0.19% 99.07% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 1 0.19% 99.26% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 1 0.19% 99.44% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 2 0.37% 99.81% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.19% 100.00% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::max_value 500052269001 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::total 537 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateResidencyTicks::ON 87559237755 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::CLK_GATED 2736191586745 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 141974504 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 19207375 # Number of instructions committed -system.cpu2.committedOps 23288496 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1385563 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 546 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 36865 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 7.391628 # CPI: cycles per instruction -system.cpu2.ipc 0.135288 # IPC: instructions per cycle -system.cpu2.op_class_0::No_OpClass 48 0.00% 0.00% # Class of committed instruction -system.cpu2.op_class_0::IntAlu 15543125 66.74% 66.74% # Class of committed instruction -system.cpu2.op_class_0::IntMult 18693 0.08% 66.82% # Class of committed instruction -system.cpu2.op_class_0::IntDiv 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::FloatAdd 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::FloatCmp 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::FloatCvt 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::FloatMult 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::FloatDiv 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdAdd 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdAlu 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdCmp 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdCvt 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdMisc 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdMult 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdShift 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMisc 1356 0.01% 66.83% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction -system.cpu2.op_class_0::MemRead 4252165 18.26% 85.09% # Class of committed instruction -system.cpu2.op_class_0::MemWrite 3473109 14.91% 100.00% # Class of committed instruction +system.cpu2.committedInsts 19185413 # Number of instructions committed +system.cpu2.committedOps 23254826 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1388377 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 540 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 36744 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 7.400128 # CPI: cycles per instruction +system.cpu2.ipc 0.135133 # IPC: instructions per cycle +system.cpu2.op_class_0::No_OpClass 50 0.00% 0.00% # Class of committed instruction +system.cpu2.op_class_0::IntAlu 15529839 66.78% 66.78% # Class of committed instruction +system.cpu2.op_class_0::IntMult 18571 0.08% 66.86% # Class of committed instruction +system.cpu2.op_class_0::IntDiv 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::FloatAdd 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::FloatCmp 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::FloatCvt 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::FloatMult 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::FloatDiv 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdAdd 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdAlu 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdCmp 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdCvt 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdMisc 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdMult 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdShift 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMisc 1326 0.01% 66.87% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction +system.cpu2.op_class_0::MemRead 4244552 18.25% 85.12% # Class of committed instruction +system.cpu2.op_class_0::MemWrite 3460488 14.88% 100.00% # Class of committed instruction system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.op_class_0::total 23288496 # Class of committed instruction +system.cpu2.op_class_0::total 23254826 # Class of committed instruction system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 41357618 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 100616145 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13553665 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7461562 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 296736 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8400664 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 4438644 # Number of BTB hits +system.cpu2.tickCycles 38692637 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 103281867 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13574263 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7472946 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 296816 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 8409244 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 4443267 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 52.836823 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3086842 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 16263 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 2014355 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 1952666 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 61689 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 18072 # Number of mispredicted indirect branches. -system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu3.branchPred.BTBHitPct 52.837889 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3091382 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 16244 # Number of incorrect RAS predictions. +system.cpu3.branchPred.indirectLookups 2018293 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 1956673 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 61620 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 18086 # Number of mispredicted indirect branches. +system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1672,91 +1670,92 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu3.dtb.walker.walks 34281 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 34281 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 10962 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8120 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 15199 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19082 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 497.143905 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 3025.740716 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-8191 18625 97.61% 97.61% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::8192-16383 304 1.59% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-24575 96 0.50% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::24576-32767 29 0.15% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-40959 9 0.05% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::40960-49151 16 0.08% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.walker.walks 34289 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 34289 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 10988 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8074 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 15227 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 19062 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 480.983108 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 2977.429006 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-8191 18630 97.73% 97.73% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::8192-16383 285 1.50% 99.23% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-24575 92 0.48% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::24576-32767 31 0.16% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-40959 6 0.03% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::40960-49151 14 0.07% 99.98% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::49152-57343 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19082 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6403 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 11721.380603 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 9562.982056 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 7657.065586 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-8191 2445 38.19% 38.19% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2784 43.48% 81.66% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::16384-24575 982 15.34% 97.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::24576-32767 97 1.51% 98.52% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-40959 43 0.67% 99.19% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::40960-49151 36 0.56% 99.75% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::49152-57343 11 0.17% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-73727 1 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkWaitTime::total 19062 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6433 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 11737.913882 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 9614.193609 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 7621.962559 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-8191 2432 37.81% 37.81% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2842 44.18% 81.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::16384-24575 955 14.85% 96.83% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::24576-32767 108 1.68% 98.51% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-40959 45 0.70% 99.21% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::40960-49151 39 0.61% 99.81% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::49152-57343 6 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-73727 2 0.03% 99.95% # Table walker service (enqueue to completion) latency system.cpu3.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6403 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8551346564 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.449586 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::stdev 0.363024 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8598250064 100.55% 100.55% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 33569000 -0.39% 100.16% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 6441000 -0.08% 100.08% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 2603000 -0.03% 100.05% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1836000 -0.02% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 609000 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 358000 -0.00% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 901500 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 248500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 75500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 42000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 21500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 24500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 20500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walkCompletionTime::total 6433 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8544248564 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.589102 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::stdev 0.347038 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8589968064 100.54% 100.54% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 32103000 -0.38% 100.16% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 6761500 -0.08% 100.08% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 2522000 -0.03% 100.05% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1641500 -0.02% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 647000 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 437000 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 926500 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 267500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 118000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 41000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 32500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 26000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 29500 -0.00% 100.00% # Table walker pending requests distribution system.cpu3.dtb.walker.walksPending::28-29 9000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 144500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8551346564 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1841 71.89% 71.89% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 720 28.11% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2561 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 34281 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walksPending::30-31 157500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8544248564 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1826 71.78% 71.78% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 718 28.22% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2544 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 34289 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 34281 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2561 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 34289 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2544 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2561 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 36842 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2544 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 36833 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7461865 # DTB read hits -system.cpu3.dtb.read_misses 28710 # DTB read misses -system.cpu3.dtb.write_hits 5703323 # DTB write hits -system.cpu3.dtb.write_misses 5571 # DTB write misses +system.cpu3.dtb.read_hits 7476077 # DTB read hits +system.cpu3.dtb.read_misses 28705 # DTB read misses +system.cpu3.dtb.write_hits 5707301 # DTB write hits +system.cpu3.dtb.write_misses 5584 # DTB write misses system.cpu3.dtb.flush_tlb 157 # Number of times complete TLB was flushed -system.cpu3.dtb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA +system.cpu3.dtb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1649 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 376 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 696 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_entries 1654 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 379 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 711 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 324 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7490575 # DTB read accesses -system.cpu3.dtb.write_accesses 5708894 # DTB write accesses +system.cpu3.dtb.perms_faults 337 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7504782 # DTB read accesses +system.cpu3.dtb.write_accesses 5712885 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 13165188 # DTB hits -system.cpu3.dtb.misses 34281 # DTB misses -system.cpu3.dtb.accesses 13199469 # DTB accesses -system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.hits 13183378 # DTB hits +system.cpu3.dtb.misses 34289 # DTB misses +system.cpu3.dtb.accesses 13217667 # DTB accesses +system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1786,394 +1785,389 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu3.itb.walker.walks 4271 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4271 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1364 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2480 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 427 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 3844 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1432.232050 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 5712.962295 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-8191 3589 93.37% 93.37% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::8192-16383 172 4.47% 97.84% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-24575 42 1.09% 98.93% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::24576-32767 19 0.49% 99.43% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-40959 8 0.21% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::40960-49151 2 0.05% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-57343 3 0.08% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::57344-65535 3 0.08% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-73727 3 0.08% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-106495 1 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 3844 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 1607 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 11557.249533 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 9424.986938 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7716.115539 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-8191 693 43.12% 43.12% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-16383 628 39.08% 82.20% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-24575 248 15.43% 97.64% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-32767 18 1.12% 98.76% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-40959 11 0.68% 99.44% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-49151 4 0.25% 99.69% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::49152-57343 2 0.12% 99.81% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::57344-65535 2 0.12% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu3.itb.walker.walks 4253 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4253 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1354 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2463 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 436 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 3817 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1262.509824 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 4945.350323 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-8191 3591 94.08% 94.08% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::8192-16383 162 4.24% 98.32% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-24575 27 0.71% 99.03% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::24576-32767 17 0.45% 99.48% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-40959 8 0.21% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::40960-49151 6 0.16% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-57343 1 0.03% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::57344-65535 4 0.10% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 3817 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 1618 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 11355.377009 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 9318.464391 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 7299.331906 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-8191 704 43.51% 43.51% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-16383 629 38.88% 82.39% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-24575 254 15.70% 98.08% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-32767 19 1.17% 99.26% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-40959 8 0.49% 99.75% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-49151 2 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::49152-57343 1 0.06% 99.94% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 1607 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -8760206064 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.998053 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.036484 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -15003296 0.17% 0.17% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -8746780268 99.85% 100.02% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1238500 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 234500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 77000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 27500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -8760206064 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 845 71.61% 71.61% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 335 28.39% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1180 # Table walker page sizes translated +system.cpu3.itb.walker.walkCompletionTime::total 1618 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -4448372768 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.737414 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.439006 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -1166371868 26.22% 26.22% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -3283428900 73.81% 100.03% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1175000 -0.03% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 224000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 29000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -4448372768 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 844 71.40% 71.40% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 338 28.60% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1182 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4271 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4271 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4253 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4253 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1180 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1180 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5451 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9881110 # ITB inst hits -system.cpu3.itb.inst_misses 4271 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1182 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1182 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5435 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9894210 # ITB inst hits +system.cpu3.itb.inst_misses 4253 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses system.cpu3.itb.flush_tlb 157 # Number of times complete TLB was flushed -system.cpu3.itb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1130 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1133 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 688 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 703 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 9885381 # ITB inst accesses -system.cpu3.itb.hits 9881110 # DTB hits -system.cpu3.itb.misses 4271 # DTB misses -system.cpu3.itb.accesses 9885381 # DTB accesses -system.cpu3.numPwrStateTransitions 1752 # Number of power state transitions -system.cpu3.pwrStateClkGateDist::samples 876 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::mean 24094343.119863 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::stdev 642903034.341614 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::underflows 861 98.29% 98.29% # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::1000-5e+10 15 1.71% 100.00% # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::max_value 18909601804 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::total 876 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateResidencyTicks::ON 2802621966927 # Cumulative time (in ticks) in various power states -system.cpu3.pwrStateResidencyTicks::CLK_GATED 21106644573 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 55785273 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 9898463 # ITB inst accesses +system.cpu3.itb.hits 9894210 # DTB hits +system.cpu3.itb.misses 4253 # DTB misses +system.cpu3.itb.accesses 9898463 # DTB accesses +system.cpu3.numPwrStateTransitions 1744 # Number of power state transitions +system.cpu3.pwrStateClkGateDist::samples 872 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::mean 24195228.891055 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::stdev 644254106.585039 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::underflows 857 98.28% 98.28% # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::1000-5e+10 15 1.72% 100.00% # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::max_value 18906661340 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::total 872 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateResidencyTicks::ON 2802652584907 # Cumulative time (in ticks) in various power states +system.cpu3.pwrStateResidencyTicks::CLK_GATED 21098239593 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 55802582 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20908000 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 53885903 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13553665 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9478152 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 32386357 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1568366 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 62842 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 789 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 205 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 111743 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 71140 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9879793 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 204446 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2275 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 54325636 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.196451 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.331637 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 20935031 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 53976458 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13574263 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9491322 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 32368112 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1569845 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 63704 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 1342 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 208 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 113598 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 71390 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9892868 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 204224 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2239 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 54338522 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.198008 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.332788 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 39861224 73.37% 73.37% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1851185 3.41% 76.78% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1193872 2.20% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3684209 6.78% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 942616 1.74% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 608186 1.12% 88.62% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2968602 5.46% 94.08% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 642558 1.18% 95.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2573184 4.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 39853023 73.34% 73.34% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1853402 3.41% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1194631 2.20% 78.95% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3690685 6.79% 85.74% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 942938 1.74% 87.48% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 608116 1.12% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2975810 5.48% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 643271 1.18% 95.26% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2576646 4.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 54325636 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.242961 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.965952 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14640847 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 30019695 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 7950688 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 1013386 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 700819 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 1055619 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 84442 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 46804905 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 276831 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 700819 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15165703 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3026847 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 21377967 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8430788 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 5623288 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 44934013 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 688 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1185922 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 108960 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 3941702 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 46859874 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 206319060 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 50493308 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 4028 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 39227152 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 7632722 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 719514 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 667644 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5723010 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 7961881 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 6281202 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1151665 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1548744 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 43283738 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 518690 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 41211324 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 55538 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6082655 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 14072346 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 54569 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 54325636 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.758598 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.457345 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 54338522 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.243255 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.967275 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14662616 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 29996417 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 7962115 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 1015455 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 701676 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 1056216 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 84320 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 46882791 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 277439 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 701676 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15188976 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3032843 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 21357872 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8442903 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 5613994 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 45010257 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 711 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1193798 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 109598 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 3924436 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 46943427 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 206658226 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 50584429 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 3918 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 39299455 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 7643972 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 719812 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 667882 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5739952 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 7978184 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 6284983 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1159177 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1675680 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 43355264 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 518308 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 41274077 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 55092 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 6092748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 14109869 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 54644 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 54338522 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.759573 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.457624 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 38109289 70.15% 70.15% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5329887 9.81% 79.96% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 4096392 7.54% 87.50% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3334775 6.14% 93.64% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1373146 2.53% 96.17% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 820032 1.51% 97.68% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 873869 1.61% 99.29% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 257598 0.47% 99.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 130648 0.24% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 38089201 70.10% 70.10% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5343903 9.83% 79.93% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 4107112 7.56% 87.49% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3342238 6.15% 93.64% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1372760 2.53% 96.17% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 822455 1.51% 97.68% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 871489 1.60% 99.28% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 257925 0.47% 99.76% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 131439 0.24% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 54325636 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 54338522 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 64574 10.28% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 290075 46.19% 56.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 273387 43.53% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 64295 10.27% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 1 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 288567 46.11% 56.39% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 272927 43.61% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 62 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 27512260 66.76% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 31067 0.08% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2328 0.01% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7676579 18.63% 85.47% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 5989018 14.53% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 61 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 27558257 66.77% 66.77% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 31168 0.08% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2328 0.01% 66.85% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.85% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.85% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.85% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7689945 18.63% 85.48% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 5992314 14.52% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 41211324 # Type of FU issued -system.cpu3.iq.rate 0.738749 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 628036 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015239 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 137423269 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 49907863 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 40057337 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 8589 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 4965 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3611 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 41834624 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4674 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 172531 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 41274077 # Type of FU issued +system.cpu3.iq.rate 0.739645 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 625790 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015162 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 137559378 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 49989246 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 40120759 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 8180 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 4843 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3492 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 41895381 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4425 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 174238 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1192071 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1205 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 28350 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 578135 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1195264 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1195 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 28361 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 579365 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 104076 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 43928 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 104459 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 43794 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 700819 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 2631101 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 281724 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 43863606 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 65733 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 7961881 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 6281202 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 267636 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 25569 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 250025 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 28350 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 127807 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 129932 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 257739 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 40889941 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7546714 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 287190 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 701676 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 2636383 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 282446 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 43936154 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 66826 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 7978184 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 6284983 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 267113 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 25993 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 250282 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 28361 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 127792 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 130048 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 257840 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 40954158 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7560730 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 285711 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 61178 # number of nop insts executed -system.cpu3.iew.exec_refs 13479048 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7536415 # Number of branches executed -system.cpu3.iew.exec_stores 5932334 # Number of stores executed -system.cpu3.iew.exec_rate 0.732988 # Inst execution rate -system.cpu3.iew.wb_sent 40598229 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 40060948 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 21086851 # num instructions producing a value -system.cpu3.iew.wb_consumers 37255196 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.718128 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.566011 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 6097168 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 464121 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 213352 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 53028005 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.712049 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.609623 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 62582 # number of nop insts executed +system.cpu3.iew.exec_refs 13496719 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7548230 # Number of branches executed +system.cpu3.iew.exec_stores 5935989 # Number of stores executed +system.cpu3.iew.exec_rate 0.733912 # Inst execution rate +system.cpu3.iew.wb_sent 40661575 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 40124251 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 21126058 # num instructions producing a value +system.cpu3.iew.wb_consumers 37308798 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.719039 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.566249 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 6107928 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 463664 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 213549 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 53039462 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.713065 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.610172 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 38640353 72.87% 72.87% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6301176 11.88% 84.75% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3204030 6.04% 90.79% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1405492 2.65% 93.44% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 791558 1.49% 94.94% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 551411 1.04% 95.98% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 959183 1.81% 97.78% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 243959 0.46% 98.24% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 930843 1.76% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 38622110 72.82% 72.82% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6314877 11.91% 84.72% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3213776 6.06% 90.78% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1409463 2.66% 93.44% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 790260 1.49% 94.93% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 551904 1.04% 95.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 961415 1.81% 97.78% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 244563 0.46% 98.24% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 931094 1.76% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 53028005 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 30988188 # Number of instructions committed -system.cpu3.commit.committedOps 37758554 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 53039462 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 31045718 # Number of instructions committed +system.cpu3.commit.committedOps 37820561 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 12472877 # Number of memory references committed -system.cpu3.commit.loads 6769810 # Number of loads committed -system.cpu3.commit.membars 181184 # Number of memory barriers committed -system.cpu3.commit.branches 7122308 # Number of branches committed -system.cpu3.commit.fp_insts 3347 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 32924881 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1244375 # Number of function calls committed. +system.cpu3.commit.refs 12488538 # Number of memory references committed +system.cpu3.commit.loads 6782920 # Number of loads committed +system.cpu3.commit.membars 181312 # Number of memory barriers committed +system.cpu3.commit.branches 7134012 # Number of branches committed +system.cpu3.commit.fp_insts 3283 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 32975843 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1245781 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 25253254 66.88% 66.88% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 30097 0.08% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2326 0.01% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6769810 17.93% 84.90% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5703067 15.10% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 25299473 66.89% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 30222 0.08% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2328 0.01% 66.98% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.98% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.98% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.98% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6782920 17.93% 84.91% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5705618 15.09% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 37758554 # Class of committed instruction -system.cpu3.commit.bw_lim_events 930843 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 90355963 # The number of ROB reads -system.cpu3.rob.rob_writes 89008957 # The number of ROB writes -system.cpu3.timesIdled 227178 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1459637 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5161855344 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 30949407 # Number of Instructions Simulated -system.cpu3.committedOps 37719773 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.802467 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.802467 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.554795 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.554795 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 44810788 # number of integer regfile reads -system.cpu3.int_regfile_writes 25112754 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14550 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12084 # number of floating regfile writes -system.cpu3.cc_regfile_reads 144202732 # number of cc regfile reads -system.cpu3.cc_regfile_writes 15932572 # number of cc regfile writes -system.cpu3.misc_regfile_reads 98044257 # number of misc regfile reads -system.cpu3.misc_regfile_writes 343753 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu3.commit.op_class_0::total 37820561 # Class of committed instruction +system.cpu3.commit.bw_lim_events 931094 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 90431014 # The number of ROB reads +system.cpu3.rob.rob_writes 89155949 # The number of ROB writes +system.cpu3.timesIdled 227288 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1464060 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5161848397 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 31005981 # Number of Instructions Simulated +system.cpu3.committedOps 37780824 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.799736 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.799736 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.555637 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.555637 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 44884059 # number of integer regfile reads +system.cpu3.int_regfile_writes 25155589 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14375 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12072 # number of floating regfile writes +system.cpu3.cc_regfile_reads 144434496 # number of cc regfile reads +system.cpu3.cc_regfile_writes 15958517 # number of cc regfile writes +system.cpu3.misc_regfile_reads 98127938 # number of misc regfile reads +system.cpu3.misc_regfile_writes 343145 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30152 # Transaction distribution system.iobus.trans_dist::ReadResp 30152 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution @@ -2224,17 +2218,17 @@ system.iobus.pkt_size_system.bridge.master::total 159093 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 30018500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 29851500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 228500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 19500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 1500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 40500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) @@ -2242,32 +2236,32 @@ system.iobus.reqLayer19.occupancy 3000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 3980500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 4026500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 22050500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 23286500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 72564537 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 72958030 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 50308000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 50254000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 14338000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.002475 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.002565 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 248713478009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.002475 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062655 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062655 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 248718527509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.002565 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062660 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062660 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 327996 # Number of tag accesses system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses system.iocache.ReadReq_misses::total 220 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2276,14 +2270,14 @@ system.iocache.demand_misses::realview.ide 36444 # system.iocache.demand_misses::total 36444 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36444 # number of overall misses system.iocache.overall_misses::total 36444 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 16064414 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 16064414 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1679848123 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1679848123 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 1695912537 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1695912537 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 1695912537 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1695912537 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 16295912 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 16295912 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 1689414118 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1689414118 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 1705710030 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1705710030 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 1705710030 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1705710030 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2300,14 +2294,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 73020.063636 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 73020.063636 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 46373.899155 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 46373.899155 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 46534.752963 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 46534.752963 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 46534.752963 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 46534.752963 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 74072.327273 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 74072.327273 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 46637.978081 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 46637.978081 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 46803.589891 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 46803.589891 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 46803.589891 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 46803.589891 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2316,771 +2310,744 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 135 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 135 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 13984 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 13984 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 14119 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 14119 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 14119 # 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Sample count of references to valid blocks. +system.l2c.tags.avg_refs 30.922703 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 79359149000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 49022.002356 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902695 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.002960 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4655.957926 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1835.969861 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000002 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 777.111964 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 859.577397 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.871513 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.006796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2228.936773 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 823.872322 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 51.838280 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 0.001832 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2977.448230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1828.803519 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.748377 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 774.839390 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 858.475569 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.852845 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2233.809872 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 830.848364 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 56.245543 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.itb.walker 0.001828 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2978.546484 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1834.278716 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.748016 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.071036 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.027961 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.071044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.028015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011858 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013116 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.011823 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.013099 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000318 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.012571 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000791 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.034085 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.012678 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000858 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.045432 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.027905 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993422 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65111 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu3.inst 0.045449 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.027989 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993419 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65108 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 60 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2175 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8177 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54718 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000900 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.993515 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45392150 # Number of tag accesses -system.l2c.tags.data_accesses 45392150 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 4238 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2128 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1538 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 869 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 12508 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 1155 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 20749 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 3773 # number of ReadReq hits -system.l2c.ReadReq_hits::total 46958 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 692418 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 692418 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1933833 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1933833 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.tags.age_task_id_blocks_1024::2 2141 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8201 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54725 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.993469 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45365928 # Number of tag accesses +system.l2c.tags.data_accesses 45365928 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.l2c.ReadReq_hits::cpu0.dtb.walker 4277 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2153 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1575 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 876 # 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number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 9 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3.data 31 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 56 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 19 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 20 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 66454 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 22443 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 25986 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 44665 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 159548 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 735257 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 209850 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 468084 # 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mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010958 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006708 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033462 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.023567 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.030243 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016676 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000635 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.134807 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002180 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011367 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.214420 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003562 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010958 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.230466 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.040194 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000635 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.134807 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002180 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011367 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.214420 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003562 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010958 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.230466 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.040194 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74732.142857 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74714.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 82479.729730 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 75930.693069 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18974.789916 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18981.566820 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19021.709634 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18997.571342 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 32062.500000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 32062.500000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68568.532819 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67019.125313 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 72527.572774 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70259.355515 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72362.412949 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73310.969557 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72841.782163 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74047.865727 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72685.714286 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78755.750399 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76035.126972 # average ReadSharedReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 80355.769231 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18969.214437 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19030.892449 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18987.671233 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18993.894994 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 45125 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 45125 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68565.346369 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67280.427884 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 72222.062251 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70179.447604 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73408.711528 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73170.660925 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73361.171563 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73291.070677 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74053.002070 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73203.507153 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 79058.105023 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76293.740237 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69491.379912 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74732.142857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72362.412949 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67401.048079 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73408.711528 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69486.823808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74714.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73170.660925 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67688.234733 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 82479.729730 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73310.969557 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 73020.559181 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 71012.363415 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73361.171563 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 72762.226913 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 71025.605108 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69491.379912 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74732.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72362.412949 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67401.048079 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73408.711528 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69486.823808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74714.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73170.660925 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67688.234733 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 82479.729730 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73310.969557 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 73020.559181 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 71012.363415 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163168.224299 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196193.886156 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202667.586650 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 192775.819739 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89361.484325 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 113406.409944 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 112384.716686 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 108356.220675 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 348991 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 146410 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73361.171563 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72762.226913 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 71025.605108 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162942.157147 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197019.980301 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202519.134132 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 192933.313315 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89331.982197 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 113866.878100 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 112348.177269 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 108476.870894 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 349065 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 146440 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 75609 # Transaction distribution +system.membus.trans_dist::ReadResp 75665 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::WritebackDirty 128684 # Transaction distribution -system.membus.trans_dist::CleanEvict 8545 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4547 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1834 # Transaction distribution -system.membus.trans_dist::ReadExReq 135487 # Transaction distribution -system.membus.trans_dist::ReadExResp 135487 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35495 # Transaction distribution +system.membus.trans_dist::WritebackDirty 128699 # Transaction distribution +system.membus.trans_dist::CleanEvict 8576 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4535 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1836 # Transaction distribution +system.membus.trans_dist::ReadExReq 135474 # Transaction distribution +system.membus.trans_dist::ReadExResp 135474 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 35551 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 22240 # Transaction distribution +system.membus.trans_dist::InvalidateResp 22160 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 476439 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 583891 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95179 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 95179 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 476553 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 584005 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95097 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 95097 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679102 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16891580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17054705 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19376305 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 335 # Total snoops (count) -system.membus.snoop_fanout::samples 342553 # Request fanout histogram -system.membus.snoop_fanout::mean 0.015446 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.123318 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16895100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17058225 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2321472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19379697 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 340 # Total snoops (count) +system.membus.snoopTraffic 21632 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 342782 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015424 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.123231 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 337262 98.46% 98.46% # Request fanout histogram -system.membus.snoop_fanout::1 5291 1.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 337495 98.46% 98.46% # Request fanout histogram +system.membus.snoop_fanout::1 5287 1.54% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 342553 # Request fanout histogram -system.membus.reqLayer0.occupancy 56458000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 342782 # Request fanout histogram +system.membus.reqLayer0.occupancy 57572000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 682999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 694499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 493971550 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 502472051 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 649041000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 647767750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 721087 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 729588 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3112,84 +3079,85 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5640723 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2834949 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 44718 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 306 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 306 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5637070 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2833088 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 44773 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 304 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 304 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 110723 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2619809 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 110855 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2618591 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 747367 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1971000 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 146335 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2812 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2841 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296829 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296829 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1971549 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 537547 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4488 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5931996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2625304 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25229 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 99111 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8681640 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 252349880 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97897081 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 40868 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 174056 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 350461885 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 123025 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4134650 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021870 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.146260 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 746435 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1969655 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 146584 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2802 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 21 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296389 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296389 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1970201 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 537545 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4503 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5927985 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2623938 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25305 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 99572 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8676800 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 252179448 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97825081 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41104 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 175440 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 350221073 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 122763 # Total snoops (count) +system.toL2Bus.snoopTraffic 6010036 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 4133801 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021872 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.146266 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4044224 97.81% 97.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 90426 2.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4043386 97.81% 97.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 90415 2.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4134650 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3415029456 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4133801 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3409727455 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 230913 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 234412 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1843284752 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1840405228 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 768457664 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 767451664 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10607473 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10602473 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 47113721 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 47179732 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed |