diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 4611 |
1 files changed, 2345 insertions, 2266 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 932631673..a5289b78c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,160 +1,164 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.824888 # Number of seconds simulated -sim_ticks 2824887572500 # Number of ticks simulated -final_tick 2824887572500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.824845 # Number of seconds simulated +sim_ticks 2824844934500 # Number of ticks simulated +final_tick 2824844934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 216723 # Simulator instruction rate (inst/s) -host_op_rate 262904 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4977623525 # Simulator tick rate (ticks/s) -host_mem_usage 565980 # Number of bytes of host memory used -host_seconds 567.52 # Real time elapsed on the host -sim_insts 122993828 # Number of instructions simulated -sim_ops 149202488 # Number of ops (including micro ops) simulated +host_inst_rate 301884 # Simulator instruction rate (inst/s) +host_op_rate 366207 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6935241973 # Simulator tick rate (ticks/s) +host_mem_usage 588164 # Number of bytes of host memory used +host_seconds 407.32 # Real time elapsed on the host +sim_insts 122962642 # Number of instructions simulated +sim_ops 149162643 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 541924 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4139684 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 101376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 929664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 333376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1678720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 417152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 3014592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 540004 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4201700 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 117312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 902784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 307648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1658880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 418176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 2992192 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11164040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 541924 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 101376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 333376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 417152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1393828 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8400768 # Number of bytes written to this memory +system.physmem.bytes_read::total 11145864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 540004 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 117312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 307648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 418176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1383140 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8393280 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8418292 # Number of bytes written to this memory +system.physmem.bytes_written::total 8410804 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 65202 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1584 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14526 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5209 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 26230 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 68 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 6518 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 47103 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16891 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 66171 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1833 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14106 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 26 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4807 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 25920 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 66 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 6534 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 46753 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 183411 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131262 # Number of write requests responded to by this memory +system.physmem.num_reads::total 183127 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131145 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135643 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135526 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 68 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 191839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1465433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 329098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 118014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 594261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1541 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 147670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1067155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 191162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1487409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 41529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 319587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 108908 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 587246 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 148035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1059241 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3952030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 191839 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 118014 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 147670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 493410 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2973842 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6203 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2980045 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2973842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3945655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 191162 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 41529 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 108908 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 148035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 489634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2971236 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2977439 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2971236 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 191839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1471637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 329098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 118014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 594261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 147670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1067155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 191162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1493613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 41529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 319587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 108908 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 587246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 148035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1059241 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6932075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 101269 # Number of read requests accepted -system.physmem.writeReqs 69732 # Number of write requests accepted -system.physmem.readBursts 101269 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 69732 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6474944 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6272 # Total number of bytes read from write queue -system.physmem.bytesWritten 4461760 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6481216 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4462848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 98 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6923094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 100046 # Number of read requests accepted +system.physmem.writeReqs 68732 # Number of write requests accepted +system.physmem.readBursts 100046 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 68732 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6396992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue +system.physmem.bytesWritten 4397632 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6402944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4398848 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6934 # Per bank write bursts -system.physmem.perBankRdBursts::1 6434 # Per bank write bursts -system.physmem.perBankRdBursts::2 6537 # Per bank write bursts -system.physmem.perBankRdBursts::3 6251 # Per bank write bursts -system.physmem.perBankRdBursts::4 6342 # Per bank write bursts -system.physmem.perBankRdBursts::5 6194 # Per bank write bursts -system.physmem.perBankRdBursts::6 6528 # Per bank write bursts -system.physmem.perBankRdBursts::7 6694 # Per bank write bursts -system.physmem.perBankRdBursts::8 6445 # Per bank write bursts -system.physmem.perBankRdBursts::9 6959 # Per bank write bursts -system.physmem.perBankRdBursts::10 6209 # Per bank write bursts -system.physmem.perBankRdBursts::11 5533 # Per bank write bursts -system.physmem.perBankRdBursts::12 5533 # Per bank write bursts -system.physmem.perBankRdBursts::13 6776 # Per bank write bursts -system.physmem.perBankRdBursts::14 6216 # Per bank write bursts -system.physmem.perBankRdBursts::15 5586 # Per bank write bursts -system.physmem.perBankWrBursts::0 4691 # Per bank write bursts -system.physmem.perBankWrBursts::1 4256 # Per bank write bursts -system.physmem.perBankWrBursts::2 4619 # Per bank write bursts -system.physmem.perBankWrBursts::3 4200 # Per bank write bursts -system.physmem.perBankWrBursts::4 4373 # Per bank write bursts -system.physmem.perBankWrBursts::5 4446 # Per bank write bursts -system.physmem.perBankWrBursts::6 4606 # Per bank write bursts -system.physmem.perBankWrBursts::7 4292 # Per bank write bursts -system.physmem.perBankWrBursts::8 4489 # Per bank write bursts -system.physmem.perBankWrBursts::9 5118 # Per bank write bursts -system.physmem.perBankWrBursts::10 4307 # Per bank write bursts -system.physmem.perBankWrBursts::11 3733 # Per bank write bursts -system.physmem.perBankWrBursts::12 3760 # Per bank write bursts -system.physmem.perBankWrBursts::13 4801 # Per bank write bursts -system.physmem.perBankWrBursts::14 4212 # Per bank write bursts -system.physmem.perBankWrBursts::15 3812 # Per bank write bursts +system.physmem.perBankRdBursts::0 6841 # Per bank write bursts +system.physmem.perBankRdBursts::1 6294 # Per bank write bursts +system.physmem.perBankRdBursts::2 6670 # Per bank write bursts +system.physmem.perBankRdBursts::3 6264 # Per bank write bursts +system.physmem.perBankRdBursts::4 6125 # Per bank write bursts +system.physmem.perBankRdBursts::5 5943 # Per bank write bursts +system.physmem.perBankRdBursts::6 6707 # Per bank write bursts +system.physmem.perBankRdBursts::7 6704 # Per bank write bursts +system.physmem.perBankRdBursts::8 6491 # Per bank write bursts +system.physmem.perBankRdBursts::9 6555 # Per bank write bursts +system.physmem.perBankRdBursts::10 6154 # Per bank write bursts +system.physmem.perBankRdBursts::11 5521 # Per bank write bursts +system.physmem.perBankRdBursts::12 5628 # Per bank write bursts +system.physmem.perBankRdBursts::13 6555 # Per bank write bursts +system.physmem.perBankRdBursts::14 6152 # Per bank write bursts +system.physmem.perBankRdBursts::15 5349 # Per bank write bursts +system.physmem.perBankWrBursts::0 4568 # Per bank write bursts +system.physmem.perBankWrBursts::1 4266 # Per bank write bursts +system.physmem.perBankWrBursts::2 4764 # Per bank write bursts +system.physmem.perBankWrBursts::3 4205 # Per bank write bursts +system.physmem.perBankWrBursts::4 4158 # Per bank write bursts +system.physmem.perBankWrBursts::5 4117 # Per bank write bursts +system.physmem.perBankWrBursts::6 4748 # Per bank write bursts +system.physmem.perBankWrBursts::7 4286 # Per bank write bursts +system.physmem.perBankWrBursts::8 4452 # Per bank write bursts +system.physmem.perBankWrBursts::9 4767 # Per bank write bursts +system.physmem.perBankWrBursts::10 4196 # Per bank write bursts +system.physmem.perBankWrBursts::11 3943 # Per bank write bursts +system.physmem.perBankWrBursts::12 3845 # Per bank write bursts +system.physmem.perBankWrBursts::13 4709 # Per bank write bursts +system.physmem.perBankWrBursts::14 4129 # Per bank write bursts +system.physmem.perBankWrBursts::15 3560 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 2823321303500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 2823278666500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 101269 # Read request sizes (log2) +system.physmem.readPktSize::6 100046 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 69732 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 77442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21001 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 68732 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 76464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 20945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -182,172 +186,170 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 64 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 66 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39430 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 277.365255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.227213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.241894 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16179 41.03% 41.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9599 24.34% 65.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3886 9.86% 75.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2087 5.29% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1608 4.08% 84.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1015 2.57% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 638 1.62% 88.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 547 1.39% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3871 9.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39430 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3587 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.196264 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 471.698929 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 3585 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::45 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39182 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 275.494666 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.171776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.907235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16210 41.37% 41.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9497 24.24% 65.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3855 9.84% 75.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2019 5.15% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1646 4.20% 84.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1042 2.66% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 570 1.45% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 566 1.44% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3777 9.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39182 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3537 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.251343 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 474.824507 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3535 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3587 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3587 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.435461 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.049607 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.402559 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 5 0.14% 0.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 1 0.03% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.06% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 3 0.08% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3190 88.93% 89.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 86 2.40% 91.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 46 1.28% 92.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 29 0.81% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 24 0.67% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 7 0.20% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 31 0.86% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.22% 95.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 55 1.53% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 9 0.25% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.11% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.20% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 27 0.75% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.06% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.08% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 13 0.36% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 26 0.72% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.03% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.11% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3587 # Writes before turning the bus around for reads -system.physmem.totQLat 1320327750 # Total ticks spent queuing -system.physmem.totMemAccLat 3217284000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 505855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13050.46 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 3537 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3537 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.426915 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.022626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.137247 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 7 0.20% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 2 0.06% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.06% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 5 0.14% 0.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3142 88.83% 89.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 84 2.37% 91.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 38 1.07% 92.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 37 1.05% 93.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 22 0.62% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 9 0.25% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 25 0.71% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.17% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 52 1.47% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.23% 97.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.14% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 10 0.28% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 31 0.88% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.03% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.03% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 15 0.42% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 29 0.82% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 1 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3537 # Writes before turning the bus around for reads +system.physmem.totQLat 1310108250 # Total ticks spent queuing +system.physmem.totMemAccLat 3184227000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 499765000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13107.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31800.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31857.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.00 # Average write queue length when enqueuing -system.physmem.readRowHits 81754 # Number of row buffer hits during reads -system.physmem.writeRowHits 49701 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.27 # Row buffer hit rate for writes -system.physmem.avgGap 16510554.34 # Average gap between requests -system.physmem.pageHitRate 76.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 156287880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 85131750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 404929200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 229929840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179785114080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 73278235845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1622828751000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1876768379595 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.450508 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2640406091750 # Time in different power states -system.physmem_0.memoryStateTime::REF 91914680000 # Time in different power states +system.physmem.avgWrQLen 28.41 # Average write queue length when enqueuing +system.physmem.readRowHits 80619 # Number of row buffer hits during reads +system.physmem.writeRowHits 48864 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.09 # Row buffer hit rate for writes +system.physmem.avgGap 16727764.68 # Average gap between requests +system.physmem.pageHitRate 76.76 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 156212280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 85094625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 402051000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 227525760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179782062720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 73198076175 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1622869382250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1876720404810 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.445189 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2640467902750 # Time in different power states +system.physmem_0.memoryStateTime::REF 91913120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 20314514250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 20211500000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 141802920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 77215875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 384181200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 221823360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179785114080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72833545215 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1617851985750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1871295668400 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.627988 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2641096901750 # Time in different power states -system.physmem_1.memoryStateTime::REF 91914680000 # Time in different power states +system.physmem_1.actEnergy 140003640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76213500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 377559000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 217734480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179782062720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72424788525 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1619952843000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1872971204865 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.534203 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2641599878750 # Time in different power states +system.physmem_1.memoryStateTime::REF 91913120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19627144250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19067953250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -397,47 +399,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 4962 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 4962 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 4962 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 4962 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 4962 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 53085003580 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.356186 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -18908123670 -35.62% -35.62% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993127250 135.62% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 53085003580 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2699 66.41% 66.41% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1365 33.59% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4064 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4962 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 4956 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 4956 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 4956 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 4956 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 4956 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 57378110626 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.254713 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -14614977624 -25.47% -25.47% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993088250 125.47% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 57378110626 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2714 66.86% 66.86% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1345 33.14% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4059 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4956 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4962 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4064 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4956 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4059 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4064 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9026 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4059 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9015 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 11954908 # DTB read hits -system.cpu0.dtb.read_misses 4164 # DTB read misses -system.cpu0.dtb.write_hits 9290329 # DTB write hits -system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12035285 # DTB read hits +system.cpu0.dtb.read_misses 4159 # DTB read misses +system.cpu0.dtb.write_hits 9387276 # DTB write hits +system.cpu0.dtb.write_misses 797 # DTB write misses +system.cpu0.dtb.flush_tlb 170 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 344 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2862 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2853 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 723 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 725 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 165 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 11959072 # DTB read accesses -system.cpu0.dtb.write_accesses 9291127 # DTB write accesses +system.cpu0.dtb.read_accesses 12039444 # DTB read accesses +system.cpu0.dtb.write_accesses 9388073 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21245237 # DTB hits -system.cpu0.dtb.misses 4962 # DTB misses -system.cpu0.dtb.accesses 21250199 # DTB accesses +system.cpu0.dtb.hits 21422561 # DTB hits +system.cpu0.dtb.misses 4956 # DTB misses +system.cpu0.dtb.accesses 21427517 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -467,649 +469,652 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2303 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2303 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2303 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2303 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2303 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 53085003580 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.356188 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -18908264170 -35.62% -35.62% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993267750 135.62% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 53085003580 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1258 73.83% 73.83% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 446 26.17% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1704 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2296 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2296 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2296 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2296 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2296 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 57378110626 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.254717 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -14615152624 -25.47% -25.47% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993263250 125.47% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 57378110626 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1260 74.03% 74.03% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 442 25.97% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1702 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2303 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2303 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2296 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2296 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1704 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1704 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4007 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 57101564 # ITB inst hits -system.cpu0.itb.inst_misses 2303 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1702 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1702 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 3998 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 57357207 # ITB inst hits +system.cpu0.itb.inst_misses 2296 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 170 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 344 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1710 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1708 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 57103867 # ITB inst accesses -system.cpu0.itb.hits 57101564 # DTB hits -system.cpu0.itb.misses 2303 # DTB misses -system.cpu0.itb.accesses 57103867 # DTB accesses -system.cpu0.numCycles 69056557 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 57359503 # ITB inst accesses +system.cpu0.itb.hits 57357207 # DTB hits +system.cpu0.itb.misses 2296 # DTB misses +system.cpu0.itb.accesses 57359503 # DTB accesses +system.cpu0.numCycles 69413199 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3089 # number of quiesce instructions executed -system.cpu0.committedInsts 55689685 # Number of instructions committed -system.cpu0.committedOps 67533645 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 59242517 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4477 # Number of float alu accesses -system.cpu0.num_func_calls 5745226 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7381576 # number of instructions that are conditional controls -system.cpu0.num_int_insts 59242517 # number of integer instructions -system.cpu0.num_fp_insts 4477 # number of float instructions -system.cpu0.num_int_register_reads 109364432 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41082844 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3371 # number of times the floating registers were read +system.cpu0.kern.inst.quiesce 3088 # number of quiesce instructions executed +system.cpu0.committedInsts 55950811 # Number of instructions committed +system.cpu0.committedOps 67895775 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 59559074 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4429 # Number of float alu accesses +system.cpu0.num_func_calls 5748533 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7418510 # number of instructions that are conditional controls +system.cpu0.num_int_insts 59559074 # number of integer instructions +system.cpu0.num_fp_insts 4429 # number of float instructions +system.cpu0.num_int_register_reads 109971244 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41296090 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3323 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1108 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 205589269 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25204829 # number of times the CC registers were written -system.cpu0.num_mem_refs 21807623 # number of memory refs -system.cpu0.num_load_insts 12096876 # Number of load instructions -system.cpu0.num_store_insts 9710747 # Number of store instructions -system.cpu0.num_idle_cycles 65266459.651417 # Number of idle cycles -system.cpu0.num_busy_cycles 3790097.348583 # Number of busy cycles -system.cpu0.not_idle_fraction 0.054884 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.945116 # Percentage of idle cycles -system.cpu0.Branches 13519232 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2179 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46765026 68.14% 68.15% # Class of executed instruction -system.cpu0.op_class::IntMult 50017 0.07% 68.22% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3786 0.01% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.22% # Class of executed instruction -system.cpu0.op_class::MemRead 12096876 17.63% 85.85% # Class of executed instruction -system.cpu0.op_class::MemWrite 9710747 14.15% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 206667111 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25287842 # number of times the CC registers were written +system.cpu0.num_mem_refs 21990124 # number of memory refs +system.cpu0.num_load_insts 12179885 # Number of load instructions +system.cpu0.num_store_insts 9810239 # Number of store instructions +system.cpu0.num_idle_cycles 65532351.821320 # Number of idle cycles +system.cpu0.num_busy_cycles 3880847.178680 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055909 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944091 # Percentage of idle cycles +system.cpu0.Branches 13556627 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2177 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46939683 68.04% 68.05% # Class of executed instruction +system.cpu0.op_class::IntMult 49866 0.07% 68.12% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3817 0.01% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.12% # Class of executed instruction +system.cpu0.op_class::MemRead 12179885 17.66% 85.78% # Class of executed instruction +system.cpu0.op_class::MemWrite 9810239 14.22% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68628631 # Class of executed instruction -system.cpu0.dcache.tags.replacements 834080 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.996936 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 46068701 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 834592 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.199069 # Average number of references to valid blocks. +system.cpu0.op_class::total 68985667 # Class of executed instruction +system.cpu0.dcache.tags.replacements 833417 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.996599 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 46053699 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 833929 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.224964 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.869099 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 12.090258 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.459372 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 17.578207 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929432 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.023614 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012616 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.034332 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.718134 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.522877 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.743087 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 15.012501 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.936949 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022506 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011217 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.029321 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193256162 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193256162 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11356893 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 3664656 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4328434 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6496122 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25846105 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 8947209 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 2625670 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3368119 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 3982538 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18923536 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 168512 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 54432 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 75016 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 87845 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 385805 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 206942 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 74426 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 78729 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 90116 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 450213 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 207891 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76401 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 81635 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 94165 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460092 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20304102 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 6290326 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7696553 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 10478660 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44769641 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20472614 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 6344758 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7771569 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 10566505 # number of overall hits -system.cpu0.dcache.overall_hits::total 45155446 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 160217 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 56728 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 95563 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 209826 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 522334 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 126244 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 30952 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 98555 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 1104293 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1360044 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 49130 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 18052 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 32658 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 39211 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 139051 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3529 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2613 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3858 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8177 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18177 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 29 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 286461 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 87680 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 194118 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 1314119 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1882378 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 335591 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 105732 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 226776 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 1353330 # number of overall misses -system.cpu0.dcache.overall_misses::total 2021429 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 1016014500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1426628000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3739680000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6182322500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1887949500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 6611273497 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 78305573428 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 86804796425 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 34719000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 55073500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 117380500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 207173000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 1140000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 1140000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 2903964000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 8037901497 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu3.data 82045253428 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 92987118925 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 2903964000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 8037901497 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu3.data 82045253428 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 92987118925 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11517110 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 3721384 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4423997 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 6705948 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26368439 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9073453 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 2656622 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3466674 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu3.data 5086831 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 20283580 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 217642 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 72484 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 107674 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 127056 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 524856 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 210471 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 77039 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 82587 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 98293 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 468390 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 207891 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 76401 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 81635 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 94194 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460121 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 20590563 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 6378006 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7890671 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 11792779 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 46652019 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 20808205 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 6450490 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7998345 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 11919835 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 47176875 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013911 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.015244 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.021601 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031290 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019809 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013914 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011651 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.028429 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.217089 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.067051 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.225738 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.249048 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.303304 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.308612 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.264932 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016767 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.033918 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.046714 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.083190 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038807 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000308 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000063 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013912 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013747 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.024601 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.111434 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.040349 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016128 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.016391 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.028353 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu3.data 0.113536 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.042848 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17910.282400 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14928.664860 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17822.767436 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11835.956495 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60996.042259 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67082.070894 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70910.141989 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 63824.991269 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13287.026406 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14275.142561 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14354.959031 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11397.535347 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 39310.344828 # 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number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 12525 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 561 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.190818 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 62.912656 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 193158098 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 193158098 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11428917 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 3665384 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4294725 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 6439390 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25828416 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9038916 # 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number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 20978687 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 6445172 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7924859 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu3.data 11803901 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 47152619 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014066 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.015194 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.021522 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031007 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019740 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013971 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011332 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.028355 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.218156 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.066740 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.228899 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.247525 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.300778 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.306138 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.264544 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018231 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.033759 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.044189 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.082806 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038487 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000273 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000059 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.014024 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013587 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.024519 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.111670 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.040182 # 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average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70750.347147 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 63556.482685 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13888.995032 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13810.878661 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14281.250000 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.003551 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 35320 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 32703.703704 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 32740.959959 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41361.869171 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 62417.135955 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 49193.272799 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27117.987201 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 35403.977962 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 60644.123709 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 45804.041517 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 501932 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 35431 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 12377 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 549 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.553607 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 64.537341 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 691847 # number of writebacks -system.cpu0.dcache.writebacks::total 691847 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 79 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 15182 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 96539 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 111800 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 44856 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1015633 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1060489 # 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number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 6386365938 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11696318938 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 234355500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 312434500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 488593000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1035383000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 16564500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 21022000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 38674500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76261000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 858000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 858000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2746746500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 4685417500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 8124079438 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15556243438 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2981102000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 4997852000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 8612672438 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16591626438 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 629109500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1118645000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1808845000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3556599500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 517115500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 860105000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1408279452 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2785499952 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1146225000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1978750000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 3217124452 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6342099452 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015174 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018086 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016790 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009391 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011332 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015450 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017507 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008439 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.243899 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.209461 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.225402 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.130193 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.013171 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.015432 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.025271 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010015 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000273 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000054 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013576 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.016930 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.017099 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.008977 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016168 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019535 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019297 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.010324 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17131.119965 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14546.692533 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15573.979638 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15599.814496 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59235.825815 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66654.455352 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72468.578376 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68346.367667 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13247.159573 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13908.850109 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17403.134461 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15175.116153 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16223.800196 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 16790.734824 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16001.034340 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16260.341151 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 34320 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 34320 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31749.890189 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35401.451444 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40680.604485 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37165.479930 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28608.600520 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32282.945987 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37811.529763 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34083.325331 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177764.764058 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 199615.453248 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215261.811258 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202701.441924 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179304.958391 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 197907.271054 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 212378.140854 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200959.523267 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178456.328818 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 198869.346734 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 213989.919649 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201932.672716 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1989175 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.436154 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 93885937 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1989687 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 47.186285 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12780860000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 432.324798 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 10.897610 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 29.477932 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 38.735813 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.844384 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.021284 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.057574 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.075656 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998899 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1977299 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.446080 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 94017526 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1977811 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 47.536153 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 12783647500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 433.555546 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 10.959606 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 24.981249 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 41.949679 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.846788 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.021405 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.048792 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu3.inst 0.081933 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998918 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 227 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 97909665 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 97909665 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 56380254 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 17885752 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 10407436 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu3.inst 9212495 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 93885937 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56380254 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 17885752 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 10407436 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu3.inst 9212495 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 93885937 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56380254 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 17885752 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 10407436 # number of overall hits -system.cpu0.icache.overall_hits::cpu3.inst 9212495 # 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number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 206480 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 504682 # number of overall misses -system.cpu0.icache.overall_misses::cpu3.inst 599818 # number of overall misses -system.cpu0.icache.overall_misses::total 2033994 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2883003500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 7207358000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 8637022483 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18727383983 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2883003500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 7207358000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu3.inst 8637022483 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18727383983 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2883003500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 7207358000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu3.inst 8637022483 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18727383983 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57103268 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 18092232 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 10912118 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu3.inst 9812313 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 95919931 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57103268 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 18092232 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 10912118 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu3.inst 9812313 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 95919931 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57103268 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 18092232 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 10912118 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu3.inst 9812313 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 95919931 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012662 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011413 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.046250 # 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average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13358.719603 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13114.433055 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13205.314695 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13591.068341 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13358.719603 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13114.433055 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13205.314695 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13591.068341 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13358.719603 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1140,60 +1145,55 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 1864 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 1864 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 484 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1380 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 1864 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 1864 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 1864 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1576 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 14376.903553 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 12683.026885 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6626.503749 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-6143 273 17.32% 17.32% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::6144-8191 48 3.05% 20.37% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::10240-12287 463 29.38% 49.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-14335 60 3.81% 53.55% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::14336-16383 242 15.36% 68.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-18431 70 4.44% 73.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::22528-24575 399 25.32% 98.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-26623 21 1.33% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1576 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 1898 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1898 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 494 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1404 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1898 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1898 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1898 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1607 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13317.672682 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11568.146418 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7309.305815 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 1216 75.67% 75.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 390 24.27% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1607 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1094 69.42% 69.42% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 482 30.58% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1576 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1864 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1115 69.38% 69.38% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 492 30.62% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1607 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1898 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1864 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1576 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1898 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1607 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1576 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3440 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1607 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3505 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3874336 # DTB read hits -system.cpu1.dtb.read_misses 1644 # DTB read misses -system.cpu1.dtb.write_hits 2735867 # DTB write hits -system.cpu1.dtb.write_misses 220 # DTB write misses -system.cpu1.dtb.flush_tlb 150 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 124 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 3875526 # DTB read hits +system.cpu1.dtb.read_misses 1673 # DTB read misses +system.cpu1.dtb.write_hits 2730535 # DTB write hits +system.cpu1.dtb.write_misses 225 # DTB write misses +system.cpu1.dtb.flush_tlb 151 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 137 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1077 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1104 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 240 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 62 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3875980 # DTB read accesses -system.cpu1.dtb.write_accesses 2736087 # DTB write accesses +system.cpu1.dtb.perms_faults 65 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3877199 # DTB read accesses +system.cpu1.dtb.write_accesses 2730760 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6610203 # DTB hits -system.cpu1.dtb.misses 1864 # DTB misses -system.cpu1.dtb.accesses 6612067 # DTB accesses +system.cpu1.dtb.hits 6606061 # DTB hits +system.cpu1.dtb.misses 1898 # DTB misses +system.cpu1.dtb.accesses 6607959 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1223,89 +1223,89 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 917 # Table walker walks requested -system.cpu1.itb.walker.walksShort 917 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 177 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 740 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 917 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 917 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 917 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 666 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13797.297297 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 12192.351828 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6305.163791 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 141 21.17% 21.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.15% 21.32% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 171 25.68% 47.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 40 6.01% 53.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 171 25.68% 78.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 137 20.57% 99.25% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-26623 5 0.75% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 666 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 937 # Table walker walks requested +system.cpu1.itb.walker.walksShort 937 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 756 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 937 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 937 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 937 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 679 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12754.050074 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11061.595827 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6405.303661 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 193 28.42% 28.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::6144-8191 2 0.29% 28.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 178 26.22% 54.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 59 8.69% 63.62% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 121 17.82% 81.44% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 122 17.97% 99.41% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-26623 4 0.59% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 679 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 489 73.42% 73.42% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 177 26.58% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 666 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 498 73.34% 73.34% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 181 26.66% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 679 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 917 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 917 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 937 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 937 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 666 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 666 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1583 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 18092232 # ITB inst hits -system.cpu1.itb.inst_misses 917 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 679 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 679 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1616 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 18092512 # ITB inst hits +system.cpu1.itb.inst_misses 937 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 150 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 124 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 151 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 137 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 697 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 710 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 18093149 # ITB inst accesses -system.cpu1.itb.hits 18092232 # DTB hits -system.cpu1.itb.misses 917 # DTB misses -system.cpu1.itb.accesses 18093149 # DTB accesses -system.cpu1.numCycles 144011117 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 18093449 # ITB inst accesses +system.cpu1.itb.hits 18092512 # DTB hits +system.cpu1.itb.misses 937 # DTB misses +system.cpu1.itb.accesses 18093449 # DTB accesses +system.cpu1.numCycles 144009903 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 17422083 # Number of instructions committed -system.cpu1.committedOps 20907241 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18575942 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1372 # Number of float alu accesses -system.cpu1.num_func_calls 1991871 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2240039 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18575942 # number of integer instructions -system.cpu1.num_fp_insts 1372 # number of float instructions -system.cpu1.num_int_register_reads 34372457 # number of times the integer registers were read -system.cpu1.num_int_register_writes 13029259 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1112 # number of times the floating registers were read +system.cpu1.committedInsts 17421496 # Number of instructions committed +system.cpu1.committedOps 20899704 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18577797 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1420 # Number of float alu accesses +system.cpu1.num_func_calls 1993621 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2230861 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18577797 # number of integer instructions +system.cpu1.num_fp_insts 1420 # number of float instructions +system.cpu1.num_int_register_reads 34369600 # number of times the integer registers were read +system.cpu1.num_int_register_writes 13035963 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1160 # number of times the floating registers were read system.cpu1.num_fp_register_writes 260 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 76102433 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7596638 # number of times the CC registers were written -system.cpu1.num_mem_refs 6802434 # number of memory refs -system.cpu1.num_load_insts 3915999 # Number of load instructions -system.cpu1.num_store_insts 2886435 # Number of store instructions -system.cpu1.num_idle_cycles 136776220.801950 # Number of idle cycles -system.cpu1.num_busy_cycles 7234896.198050 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050238 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949762 # Percentage of idle cycles -system.cpu1.Branches 4344241 # Number of branches fetched -system.cpu1.op_class::No_OpClass 21 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14689053 68.29% 68.29% # Class of executed instruction -system.cpu1.op_class::IntMult 16409 0.08% 68.37% # Class of executed instruction +system.cpu1.num_cc_register_reads 76091586 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7577345 # number of times the CC registers were written +system.cpu1.num_mem_refs 6800182 # number of memory refs +system.cpu1.num_load_insts 3918123 # Number of load instructions +system.cpu1.num_store_insts 2882059 # Number of store instructions +system.cpu1.num_idle_cycles 136636530.852378 # Number of idle cycles +system.cpu1.num_busy_cycles 7373372.147622 # Number of busy cycles +system.cpu1.not_idle_fraction 0.051200 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.948800 # Percentage of idle cycles +system.cpu1.Branches 4337148 # Number of branches fetched +system.cpu1.op_class::No_OpClass 23 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14686036 68.30% 68.30% # Class of executed instruction +system.cpu1.op_class::IntMult 16352 0.08% 68.37% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 68.37% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 68.37% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 68.37% # Class of executed instruction @@ -1329,24 +1329,28 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.37% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.37% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.37% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 960 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::MemRead 3915999 18.21% 86.58% # Class of executed instruction -system.cpu1.op_class::MemWrite 2886435 13.42% 100.00% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 955 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::MemRead 3918123 18.22% 86.60% # Class of executed instruction +system.cpu1.op_class::MemWrite 2882059 13.40% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21508877 # Class of executed instruction -system.cpu2.branchPred.lookups 5793612 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2980826 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 510173 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3341090 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2404622 # Number of BTB hits +system.cpu1.op_class::total 21503548 # Class of executed instruction +system.cpu2.branchPred.lookups 5770264 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2970192 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 504477 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3340147 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 1745677 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.971183 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1623448 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 331512 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 52.263478 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1611184 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 331954 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 670735 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 637081 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 33654 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 21230 # Number of mispredicted indirect branches. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1376,54 +1380,60 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 13179 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 13179 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8247 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4932 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 13179 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 13179 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 13179 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2214 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 13311.653117 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 11619.348750 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 8511.573667 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-32767 2213 99.95% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-294911 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2214 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walks 12712 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 12712 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8004 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4708 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 12712 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 12712 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 12712 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2182 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 12059.578368 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 10400.362655 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 6359.555797 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::2048-4095 13 0.60% 0.60% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::4096-6143 665 30.48% 31.07% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::6144-8191 1 0.05% 31.12% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::10240-12287 773 35.43% 66.54% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::12288-14335 182 8.34% 74.89% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::14336-16383 171 7.84% 82.72% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::22528-24575 366 16.77% 99.50% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::24576-26623 11 0.50% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 2182 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000052000 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000052000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000052000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1376 62.15% 62.15% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 838 37.85% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2214 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 13179 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 1365 62.56% 62.56% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 817 37.44% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2182 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12712 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 13179 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2214 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12712 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2182 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2214 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 15393 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2182 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 14894 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4658745 # DTB read hits -system.cpu2.dtb.read_misses 11783 # DTB read misses -system.cpu2.dtb.write_hits 3577519 # DTB write hits -system.cpu2.dtb.write_misses 1396 # DTB write misses -system.cpu2.dtb.flush_tlb 154 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 176 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 4621518 # DTB read hits +system.cpu2.dtb.read_misses 11435 # DTB read misses +system.cpu2.dtb.write_hits 3537262 # DTB write hits +system.cpu2.dtb.write_misses 1277 # DTB write misses +system.cpu2.dtb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 162 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1514 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 206 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 331 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 1476 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 227 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 324 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4670528 # DTB read accesses -system.cpu2.dtb.write_accesses 3578915 # DTB write accesses +system.cpu2.dtb.perms_faults 121 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4632953 # DTB read accesses +system.cpu2.dtb.write_accesses 3538539 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 8236264 # DTB hits -system.cpu2.dtb.misses 13179 # DTB misses -system.cpu2.dtb.accesses 8249443 # DTB accesses +system.cpu2.dtb.hits 8158780 # DTB hits +system.cpu2.dtb.misses 12712 # DTB misses +system.cpu2.dtb.accesses 8171492 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1453,82 +1463,122 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 1381 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1381 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 251 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1130 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1381 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1381 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1381 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 875 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 13237.714286 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 11667.376673 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6208.114147 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 218 24.91% 24.91% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::6144-8191 1 0.11% 25.03% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 241 27.54% 52.57% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 34 3.89% 56.46% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 216 24.69% 81.14% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 162 18.51% 99.66% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::24576-26623 3 0.34% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 875 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walks 1416 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1416 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 256 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1160 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1416 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1416 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1416 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 870 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 12294.252874 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 10677.468386 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6303.110021 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 282 32.41% 32.41% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::6144-8191 1 0.11% 32.53% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 251 28.85% 61.38% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 36 4.14% 65.52% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 152 17.47% 82.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::16384-18431 1 0.11% 83.10% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 145 16.67% 99.77% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::24576-26623 2 0.23% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 870 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000037500 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000037500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000037500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 624 71.31% 71.31% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 251 28.69% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 875 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 614 70.57% 70.57% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 256 29.43% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 870 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1381 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1381 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1416 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1416 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 875 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 875 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2256 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10914034 # ITB inst hits -system.cpu2.itb.inst_misses 1381 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 870 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 870 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2286 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10823576 # ITB inst hits +system.cpu2.itb.inst_misses 1416 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 154 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 176 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 162 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 885 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 879 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1797 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1762 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10915415 # ITB inst accesses -system.cpu2.itb.hits 10914034 # DTB hits -system.cpu2.itb.misses 1381 # DTB misses -system.cpu2.itb.accesses 10915415 # DTB accesses -system.cpu2.numCycles 1393570543 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 10824992 # ITB inst accesses +system.cpu2.itb.hits 10823576 # DTB hits +system.cpu2.itb.misses 1416 # DTB misses +system.cpu2.itb.accesses 10824992 # DTB accesses +system.cpu2.numCycles 1395003779 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 20500176 # Number of instructions committed -system.cpu2.committedOps 24831062 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1467933 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 564 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 4256215364 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 67.978467 # CPI: cycles per instruction -system.cpu2.ipc 0.014711 # IPC: instructions per cycle +system.cpu2.committedInsts 20361751 # Number of instructions committed +system.cpu2.committedOps 24653563 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1458677 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 555 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 4254696736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 68.510993 # CPI: cycles per instruction +system.cpu2.ipc 0.014596 # IPC: instructions per cycle +system.cpu2.op_class_0::No_OpClass 53 0.00% 0.00% # Class of committed instruction +system.cpu2.op_class_0::IntAlu 16404326 66.54% 66.54% # Class of committed instruction +system.cpu2.op_class_0::IntMult 20837 0.08% 66.62% # Class of committed instruction +system.cpu2.op_class_0::IntDiv 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::FloatAdd 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::FloatCmp 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::FloatCvt 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::FloatMult 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::FloatDiv 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdAdd 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdAlu 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdCmp 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdCvt 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdMisc 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdMult 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdShift 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMisc 1376 0.01% 66.63% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.63% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.63% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.63% # Class of committed instruction +system.cpu2.op_class_0::MemRead 4532751 18.39% 85.02% # Class of committed instruction +system.cpu2.op_class_0::MemWrite 3694220 14.98% 100.00% # Class of committed instruction +system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu2.op_class_0::total 24653563 # Class of committed instruction system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 42639934 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 1350930609 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13289019 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7253126 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 312439 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8263558 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 6253160 # Number of BTB hits +system.cpu2.tickCycles 42378112 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 1352625667 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13251998 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7208175 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 300007 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 8273745 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 4241517 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 75.671521 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3098416 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 16246 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 51.264778 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3096619 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 16788 # Number of incorrect RAS predictions. +system.cpu3.branchPred.indirectLookups 2038227 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 1978271 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 59956 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 18256 # Number of mispredicted indirect branches. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1558,87 +1608,84 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 32928 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 32928 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11539 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7550 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 13839 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19089 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 453.769186 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 3060.650979 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-8191 18684 97.88% 97.88% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::8192-16383 255 1.34% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-24575 92 0.48% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::24576-32767 26 0.14% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-40959 12 0.06% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::40960-49151 11 0.06% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::49152-57343 5 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-73727 3 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19089 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6197 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 13294.578022 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 10885.248950 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 8635.189295 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-16383 4539 73.25% 73.25% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::16384-32767 1528 24.66% 97.90% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-49151 104 1.68% 99.58% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::49152-65535 10 0.16% 99.74% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-81919 13 0.21% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::147456-163839 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6197 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8048051564 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.976034 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8093653564 100.57% 100.57% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 33199000 -0.41% 100.15% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 6574500 -0.08% 100.07% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 2215500 -0.03% 100.04% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1246000 -0.02% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 692500 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 364000 -0.00% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 852000 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 153000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 182500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 65500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 10500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 20000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 4500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-29 3500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 19000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8048051564 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1804 69.07% 69.07% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 808 30.93% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2612 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 32928 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walks 33988 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 33988 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11189 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8109 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 14690 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 19298 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 517.203855 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 3689.785170 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-16383 19110 99.03% 99.03% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-32767 146 0.76% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-49151 30 0.16% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::49152-65535 4 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-81919 3 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::81920-98303 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::147456-163839 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 19298 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6381 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 13105.939508 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 10791.784480 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 9136.863267 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-32767 6254 98.01% 98.01% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-65535 124 1.94% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-98303 1 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-163839 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::360448-393215 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 6381 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8047267064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.135073 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8095966564 100.61% 100.61% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 33943000 -0.42% 100.18% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 7702500 -0.10% 100.09% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 2846000 -0.04% 100.05% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1530000 -0.02% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 743500 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 398000 -0.00% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 810000 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 216000 -0.00% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 164500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 85000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 84500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 64500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 35000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-29 17500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::30-31 59500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8047267064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1874 70.21% 70.21% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 795 29.79% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2669 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33988 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 32928 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2612 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33988 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2669 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2612 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 35540 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2669 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 36657 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7260437 # DTB read hits -system.cpu3.dtb.read_misses 28509 # DTB read misses -system.cpu3.dtb.write_hits 5425830 # DTB write hits -system.cpu3.dtb.write_misses 4419 # DTB write misses -system.cpu3.dtb.flush_tlb 161 # Number of times complete TLB was flushed -system.cpu3.dtb.flush_tlb_mva 272 # Number of times TLB was flushed by MVA +system.cpu3.dtb.read_hits 7187515 # DTB read hits +system.cpu3.dtb.read_misses 29422 # DTB read misses +system.cpu3.dtb.write_hits 5346412 # DTB write hits +system.cpu3.dtb.write_misses 4566 # DTB write misses +system.cpu3.dtb.flush_tlb 162 # Number of times complete TLB was flushed +system.cpu3.dtb.flush_tlb_mva 274 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1914 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 485 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 810 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_entries 1921 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 451 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 735 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 320 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7288946 # DTB read accesses -system.cpu3.dtb.write_accesses 5430249 # DTB write accesses +system.cpu3.dtb.perms_faults 408 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7216937 # DTB read accesses +system.cpu3.dtb.write_accesses 5350978 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 12686267 # DTB hits -system.cpu3.dtb.misses 32928 # DTB misses -system.cpu3.dtb.accesses 12719195 # DTB accesses +system.cpu3.dtb.hits 12533927 # DTB hits +system.cpu3.dtb.misses 33988 # DTB misses +system.cpu3.dtb.accesses 12567915 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1668,386 +1715,388 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 4959 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4959 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1575 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2956 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 428 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 4531 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1378.172589 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 5474.247381 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-8191 4267 94.17% 94.17% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::8192-16383 125 2.76% 96.93% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-24575 86 1.90% 98.83% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::24576-32767 32 0.71% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-40959 9 0.20% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::40960-49151 4 0.09% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-57343 1 0.02% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::57344-65535 2 0.04% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-73727 2 0.04% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::73728-81919 2 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 4531 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 1743 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 12810.097533 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 10341.257314 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 8222.199176 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-4095 24 1.38% 1.38% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::4096-8191 622 35.69% 37.06% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-12287 348 19.97% 57.03% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::12288-16383 324 18.59% 75.62% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-20479 26 1.49% 77.11% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::20480-24575 315 18.07% 95.18% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-28671 50 2.87% 98.05% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::28672-32767 6 0.34% 98.39% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-36863 6 0.34% 98.74% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::36864-40959 6 0.34% 99.08% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-45055 8 0.46% 99.54% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::45056-49151 4 0.23% 99.77% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.06% 99.83% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::57344-61439 2 0.11% 99.94% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::61440-65535 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 1743 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -4005171768 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean -0.325586 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -5306419980 132.49% 132.49% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 1298923212 -32.43% 100.06% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1978000 -0.05% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 238000 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 109000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -4005171768 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 967 73.54% 73.54% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 348 26.46% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1315 # Table walker page sizes translated +system.cpu3.itb.walker.walks 4586 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4586 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1476 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2630 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 480 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 4106 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1386.751096 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 5919.935544 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-8191 3869 94.23% 94.23% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::8192-16383 140 3.41% 97.64% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-24575 51 1.24% 98.88% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::24576-32767 18 0.44% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-40959 9 0.22% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::40960-49151 8 0.19% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-57343 3 0.07% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::57344-65535 2 0.05% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-73727 1 0.02% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.02% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::81920-90111 2 0.05% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::106496-114687 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 4106 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 1793 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 12167.875070 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 9929.586957 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 7490.636626 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-4095 25 1.39% 1.39% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::4096-8191 685 38.20% 39.60% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-12287 343 19.13% 58.73% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::12288-16383 337 18.80% 77.52% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-20479 34 1.90% 79.42% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::20480-24575 327 18.24% 97.66% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-28671 25 1.39% 99.05% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::28672-32767 2 0.11% 99.16% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-36863 8 0.45% 99.61% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::36864-40959 3 0.17% 99.78% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-45055 1 0.06% 99.83% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::45056-49151 1 0.06% 99.89% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::49152-53247 2 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 1793 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -8048536564 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.273748 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.444975 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -5842963052 72.60% 72.60% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -2207207512 27.42% 100.02% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1197000 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 240000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 159500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 37500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -8048536564 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 959 73.04% 73.04% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 354 26.96% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1313 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4959 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4959 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4586 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4586 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1315 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1315 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 6274 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9813721 # ITB inst hits -system.cpu3.itb.inst_misses 4959 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1313 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1313 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5899 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9766961 # ITB inst hits +system.cpu3.itb.inst_misses 4586 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 161 # Number of times complete TLB was flushed -system.cpu3.itb.flush_tlb_mva 272 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb 162 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb_mva 274 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1311 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1310 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 728 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 793 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 9818680 # ITB inst accesses -system.cpu3.itb.hits 9813721 # DTB hits -system.cpu3.itb.misses 4959 # DTB misses -system.cpu3.itb.accesses 9818680 # DTB accesses -system.cpu3.numCycles 58198977 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 9771547 # ITB inst accesses +system.cpu3.itb.hits 9766961 # DTB hits +system.cpu3.itb.misses 4586 # DTB misses +system.cpu3.itb.accesses 9771547 # DTB accesses +system.cpu3.numCycles 57688008 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20997510 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 52319874 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13289019 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9351576 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 34146869 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1603241 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 75601 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 830 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 252 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 167692 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 75270 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 481 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9812317 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 215159 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2588 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 56266104 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.124866 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.272811 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 20811667 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 52032939 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13251998 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9316407 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 33930226 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1581195 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 68181 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 231 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 120341 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 80383 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 479 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9765461 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 207701 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2399 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 55802921 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.126478 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.271735 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 42091874 74.81% 74.81% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1838725 3.27% 78.08% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1172268 2.08% 80.16% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3680170 6.54% 86.70% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 919176 1.63% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 559542 0.99% 89.33% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2920436 5.19% 94.52% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 600253 1.07% 95.59% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2483660 4.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 41696635 74.72% 74.72% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1836227 3.29% 78.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1165179 2.09% 80.10% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3688200 6.61% 86.71% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 906119 1.62% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 549240 0.98% 89.32% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2914414 5.22% 94.54% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 602851 1.08% 95.62% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2444056 4.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 56266104 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.228338 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.898983 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14691998 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 32127735 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 7847757 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 886811 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 711602 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 982939 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 91189 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 45025985 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 297573 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 711602 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15176381 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3842485 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 22070368 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8242497 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 6222544 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 43140081 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 802 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 912982 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 87651 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 4846837 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 44765157 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 198174110 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 48152546 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 3891 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 37263168 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 7501989 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 722657 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 671168 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5019030 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 7753962 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 6001781 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1096461 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1526920 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 41470903 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 516515 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 39452509 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 52405 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6056878 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 13877375 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 54814 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 56266104 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.701177 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.409085 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 55802921 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.229718 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.901971 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14568500 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 31866419 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 7772530 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 890722 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 704491 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 971896 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 87220 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 44589995 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 289462 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 704491 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15048240 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3770694 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 21829138 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8174722 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 6275353 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 42740341 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 1149 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 970338 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 89122 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 4852694 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 44469906 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 196241867 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 47658111 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 4195 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 37088315 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 7381591 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 715058 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 665415 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5054904 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 7671721 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 5900836 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1096117 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1546300 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 41143792 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 502169 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 39136227 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 53751 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 5932360 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 13678384 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 53132 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 55802921 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.701329 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.406591 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 40628428 72.21% 72.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5180351 9.21% 81.41% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 3993172 7.10% 88.51% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3216769 5.72% 94.23% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1270144 2.26% 96.49% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 778707 1.38% 97.87% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 841867 1.50% 99.37% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 243134 0.43% 99.80% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 113532 0.20% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 40242426 72.12% 72.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5178735 9.28% 81.40% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 3976743 7.13% 88.52% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3203415 5.74% 94.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1255788 2.25% 96.51% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 764372 1.37% 97.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 832267 1.49% 99.37% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 238253 0.43% 99.80% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 110922 0.20% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 56266104 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 55802921 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 56907 9.43% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 285269 47.26% 56.69% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 261388 43.31% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 55579 9.37% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 279420 47.11% 56.48% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 258160 43.52% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 82 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 26244378 66.52% 66.52% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 29732 0.08% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2423 0.01% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7478738 18.96% 85.56% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 5697150 14.44% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 26095739 66.68% 66.68% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 29921 0.08% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2385 0.01% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7397588 18.90% 85.66% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 5610508 14.34% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 39452509 # Type of FU issued -system.cpu3.iq.rate 0.677890 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 603564 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015298 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 135818664 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 48068982 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 38286246 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 8427 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 4554 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3686 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 40051464 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4527 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 171911 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 39136227 # Type of FU issued +system.cpu3.iq.rate 0.678412 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 593159 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015156 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 134713506 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 47601839 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 37987745 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 8779 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 5136 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 39724596 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4706 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 167565 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1183804 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1366 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 29886 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 609084 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1160512 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1106 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 29283 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 565980 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 109633 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 44383 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 108566 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 42617 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 711602 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 3194648 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 528279 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 42035264 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 85063 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 7753962 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 6001781 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 267022 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 22471 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 499621 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 29886 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 141382 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 125809 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 267191 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 39120156 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7345638 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 299518 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 704491 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 3164370 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 480380 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 41688366 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 67674 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 7671721 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 5900836 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 259515 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 22770 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 451545 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 29283 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 127479 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 130166 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 257645 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 38819065 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7269277 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 283258 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 47846 # number of nop insts executed -system.cpu3.iew.exec_refs 12983277 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7265357 # Number of branches executed -system.cpu3.iew.exec_stores 5637639 # Number of stores executed -system.cpu3.iew.exec_rate 0.672179 # Inst execution rate -system.cpu3.iew.wb_sent 38830479 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 38289932 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 20020734 # num instructions producing a value -system.cpu3.iew.wb_consumers 34859038 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.657914 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.574334 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 6072535 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 461701 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 222399 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 54967240 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.654139 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.550137 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 42405 # number of nop insts executed +system.cpu3.iew.exec_refs 12824699 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7229147 # Number of branches executed +system.cpu3.iew.exec_stores 5555422 # Number of stores executed +system.cpu3.iew.exec_rate 0.672914 # Inst execution rate +system.cpu3.iew.wb_sent 38534574 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 37991618 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 19895902 # num instructions producing a value +system.cpu3.iew.wb_consumers 34654427 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.658570 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.574123 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 5941681 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 449037 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 213879 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 54520381 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.655520 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.547792 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 41117767 74.80% 74.80% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6171974 11.23% 86.03% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3094219 5.63% 91.66% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1318133 2.40% 94.06% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 709863 1.29% 95.35% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 496595 0.90% 96.25% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 959944 1.75% 98.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 230664 0.42% 98.42% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 868081 1.58% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 40723522 74.69% 74.69% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6130634 11.24% 85.94% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3105134 5.70% 91.63% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1318169 2.42% 94.05% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 725183 1.33% 95.38% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 499193 0.92% 96.30% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 937316 1.72% 98.02% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 226626 0.42% 98.43% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 854604 1.57% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 54967240 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 29407542 # Number of instructions committed -system.cpu3.commit.committedOps 35956198 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 54520381 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 29254199 # Number of instructions committed +system.cpu3.commit.committedOps 35739216 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 11962855 # Number of memory references committed -system.cpu3.commit.loads 6570158 # Number of loads committed -system.cpu3.commit.membars 179658 # Number of memory barriers committed -system.cpu3.commit.branches 6851927 # Number of branches committed -system.cpu3.commit.fp_insts 3664 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 31411124 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1242322 # Number of function calls committed. +system.cpu3.commit.refs 11846065 # Number of memory references committed +system.cpu3.commit.loads 6511209 # Number of loads committed +system.cpu3.commit.membars 174051 # Number of memory barriers committed +system.cpu3.commit.branches 6823805 # Number of branches committed +system.cpu3.commit.fp_insts 3728 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 31222090 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1239495 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 23962177 66.64% 66.64% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 28743 0.08% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2423 0.01% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6570158 18.27% 85.00% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5392697 15.00% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 23861802 66.77% 66.77% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 28964 0.08% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2385 0.01% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6511209 18.22% 85.07% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5334856 14.93% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 35956198 # Class of committed instruction -system.cpu3.commit.bw_lim_events 868081 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 90502636 # The number of ROB reads -system.cpu3.rob.rob_writes 85356048 # The number of ROB writes -system.cpu3.timesIdled 229941 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1932873 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5160445886 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 29381884 # Number of Instructions Simulated -system.cpu3.committedOps 35930540 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.980778 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.980778 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.504852 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.504852 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 42608417 # number of integer regfile reads -system.cpu3.int_regfile_writes 24235283 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14369 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12266 # number of floating regfile writes -system.cpu3.cc_regfile_reads 138322316 # number of cc regfile reads -system.cpu3.cc_regfile_writes 14832721 # number of cc regfile writes -system.cpu3.misc_regfile_reads 76348373 # number of misc regfile reads -system.cpu3.misc_regfile_writes 345208 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30184 # Transaction distribution -system.iobus.trans_dist::ReadResp 30184 # Transaction distribution +system.cpu3.commit.op_class_0::total 35739216 # Class of committed instruction +system.cpu3.commit.bw_lim_events 854604 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 89694984 # The number of ROB reads +system.cpu3.rob.rob_writes 84644228 # The number of ROB writes +system.cpu3.timesIdled 227110 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1885087 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5160958859 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 29228584 # Number of Instructions Simulated +system.cpu3.committedOps 35713601 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.973685 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.973685 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.506667 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.506667 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 42269804 # number of integer regfile reads +system.cpu3.int_regfile_writes 24060507 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14520 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12259 # number of floating regfile writes +system.cpu3.cc_regfile_reads 137213750 # number of cc regfile reads +system.cpu3.cc_regfile_writes 14769664 # number of cc regfile writes +system.cpu3.misc_regfile_reads 75722045 # number of misc regfile reads +system.cpu3.misc_regfile_writes 336113 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30181 # Transaction distribution +system.iobus.trans_dist::ReadResp 30181 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution system.iobus.trans_dist::WriteResp 59010 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54148 # Packet count per connected master and slave (bytes) @@ -2070,9 +2119,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105436 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178388 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67865 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -2093,91 +2142,93 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159093 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480341 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 27681500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480317 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 27737500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 101500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 206500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 203000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 19500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 12500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 3853000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 3863000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 22107500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 22351500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 78671523 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 78673017 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 47950000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 48334000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 15518000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 15512000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 1.005787 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 249220700509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005787 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062862 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062862 # Average percentage of cache occupancy +system.iocache.tags.replacements 36409 # number of replacements +system.iocache.tags.tagsinuse 1.005569 # Cycle average of tags in use +system.iocache.tags.total_refs 30 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 249219554509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005569 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062848 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062848 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328284 # Number of tag accesses -system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses -system.iocache.ReadReq_misses::total 252 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses -system.iocache.demand_misses::total 252 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 252 # number of overall misses -system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 18163419 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 18163419 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1912585104 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1912585104 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 18163419 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 18163419 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 18163419 # number of overall miss cycles -system.iocache.overall_miss_latency::total 18163419 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) +system.iocache.tags.tag_accesses 328227 # Number of tag accesses +system.iocache.tags.data_accesses 328227 # Number of data accesses +system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits +system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits +system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses +system.iocache.ReadReq_misses::total 249 # number of ReadReq misses +system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses +system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses +system.iocache.demand_misses::total 249 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 249 # number of overall misses +system.iocache.overall_misses::total 249 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 17512919 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 17512919 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 1907451098 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1907451098 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 17512919 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 17512919 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 17512919 # number of overall miss cycles +system.iocache.overall_miss_latency::total 17512919 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 72077.059524 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 72077.059524 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52798.837898 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 52798.837898 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 72077.059524 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 72077.059524 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 72077.059524 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 72077.059524 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 70333.008032 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 70333.008032 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52699.298190 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 52699.298190 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 70333.008032 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 70333.008032 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 70333.008032 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 70333.008032 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2186,408 +2237,424 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 151 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 15216 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 15216 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 151 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 151 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 151 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 151 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 10613419 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10613419 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1151112953 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1151112953 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 10613419 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10613419 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 10613419 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10613419 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.599206 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.599206 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.420053 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.420053 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.599206 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.599206 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.599206 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.599206 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70287.543046 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70287.543046 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75651.482190 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75651.482190 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70287.543046 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70287.543046 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70287.543046 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70287.543046 # average overall mshr miss latency +system.iocache.writebacks::writebacks 36160 # number of writebacks +system.iocache.writebacks::total 36160 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 148 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 148 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 15187 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 15187 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 148 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 148 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 148 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 10112919 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10112919 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1147424968 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1147424968 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 10112919 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10112919 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 10112919 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10112919 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.594378 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.419252 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.419252 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.594378 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.594378 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68330.533784 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68330.533784 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75553.102522 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75553.102522 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68330.533784 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68330.533784 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68330.533784 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68330.533784 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104075 # number of replacements -system.l2c.tags.tagsinuse 65088.742939 # Cycle average of tags in use -system.l2c.tags.total_refs 5172869 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169255 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.562577 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 80144379500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48905.220399 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.971842 # Average occupied blocks per requestor +system.l2c.tags.replacements 103654 # number of replacements +system.l2c.tags.tagsinuse 65094.562586 # Cycle average of tags in use +system.l2c.tags.total_refs 5149242 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168905 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 30.486025 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 80133862000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 49018.245054 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.971846 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4329.133912 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2210.348927 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 681.885692 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 812.281679 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 23.888287 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2283.545519 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 778.271675 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 49.750062 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 3339.743961 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1673.700888 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.746234 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4276.002230 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2253.870491 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.966972 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 903.622290 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 882.214682 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 22.046662 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1923.753709 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 720.306234 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 49.949258 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 3365.651455 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1676.961608 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.747959 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.066057 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.033727 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.010405 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012394 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000365 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034844 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.011875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000759 # 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Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45714776 # Number of tag accesses -system.l2c.tags.data_accesses 45714776 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4211 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2125 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1917 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 966 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 14552 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 1305 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 20572 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 4671 # number of ReadReq hits -system.l2c.ReadReq_hits::total 50319 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 691847 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 691847 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1951174 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.001938 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003120 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.001911 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.994667 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.981229 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.945170 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.585844 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.320000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.296296 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.397681 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.465419 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.493956 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.267692 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.008901 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.009675 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.011996 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006663 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.034461 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.019060 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.029283 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016213 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000580 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008901 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.137216 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.001938 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009675 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.169449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003120 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.011996 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.206228 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.035422 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000580 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008901 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.137216 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.001938 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009675 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.169449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003120 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.011996 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.206228 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035422 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 125559.139785 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67993.297587 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68011.304348 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 67991.022099 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67998.504785 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 68812.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68812.500000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118608.808071 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117561.871949 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122645.881126 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 120483.140473 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121622.749591 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122640.095614 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 122580.578972 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122469.077478 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121691.045928 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 122967.684478 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127814.062740 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124901.273635 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121622.749591 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119163.897963 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122640.095614 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117965.061110 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 122580.578972 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 123100.274775 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121126.170847 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165258.971461 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 187113.758030 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202759.252648 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190198.506782 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167798.543689 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 186407.271054 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200867.139195 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189452.925474 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 166399.268255 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 186805.175879 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 201924.704004 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 189869.455854 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 76465 # Transaction distribution +system.membus.trans_dist::ReadResp 76256 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::WritebackDirty 131262 # Transaction distribution -system.membus.trans_dist::CleanEvict 9255 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4560 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1783 # Transaction distribution -system.membus.trans_dist::ReadExReq 138008 # Transaction distribution -system.membus.trans_dist::ReadExResp 138008 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36351 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WritebackDirty 131145 # Transaction distribution +system.membus.trans_dist::CleanEvict 8918 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4561 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1773 # Transaction distribution +system.membus.trans_dist::ReadExReq 137930 # Transaction distribution +system.membus.trans_dist::ReadExResp 137930 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 36142 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution system.membus.trans_dist::InvalidateResp 21008 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 486392 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 593844 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94027 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 94027 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 687871 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 485390 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 592842 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 93962 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 93962 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 686804 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17273404 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17436529 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2322624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2322624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19759153 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 308 # Total snoops (count) -system.membus.snoop_fanout::samples 423355 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17249660 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17412785 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2320704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2320704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19733489 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 305 # Total snoops (count) +system.membus.snoop_fanout::samples 422579 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 423355 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 422579 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 423355 # Request fanout histogram -system.membus.reqLayer0.occupancy 54051500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 422579 # Request fanout histogram +system.membus.reqLayer0.occupancy 54357000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 682000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 681000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 487313006 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 480576517 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 582602000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 576477250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 785081 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 796581 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2900,60 +2979,60 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5677345 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2853013 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 45306 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 358 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 358 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5652845 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2841067 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 44935 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 620 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 112463 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2640157 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 111946 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2627538 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 761584 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1989175 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 147491 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2813 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2842 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296749 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296749 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1989735 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 538020 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 15216 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5986563 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2626405 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26917 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102214 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8742099 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 254678264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97882489 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 44408 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 182720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 352787881 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 192824 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4204353 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021421 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.144784 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 760858 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1977299 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 146343 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2855 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2881 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296356 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296356 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1977848 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 537746 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 15186 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5950911 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2624548 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25489 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 101523 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8702471 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 253157304 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97861305 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41336 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 179384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 351239329 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 193521 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4203870 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021594 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.145354 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4114290 97.86% 97.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 90063 2.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4113091 97.84% 97.84% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 90779 2.16% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4204353 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3491124499 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4203870 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3441050999 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 176919 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 260919 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1900767119 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1872616750 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 770214712 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 760136706 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11666477 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11021467 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 48138206 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 48272206 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed |