diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full')
5 files changed, 2261 insertions, 1933 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index 8a89971a1..b371e25ee 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain -atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +atags_addr=134217728 +boot_loader=/dist/binaries/boot_emm.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename= +dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 -flags_addr=268435504 -gic_cpu_addr=520093952 +flags_addr=469827632 +gic_cpu_addr=738205696 have_generic_timer=false have_large_asid_64=false have_lpae=false @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 -load_offset=0 -machine_type=RealView_PBX +load_offset=2147483648 +machine_type=VExpress_EMM mem_mode=atomic -mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +mem_ranges=2147483648:2415919103 +memories=system.realview.vram system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -53,14 +53,14 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[0] +system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 -ranges=268435456:520093695 1073741824:1610612735 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -278,6 +278,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu0.istage2_mmu] @@ -424,6 +425,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu1.istage2_mmu] @@ -948,6 +950,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu2.istage2_mmu] @@ -1019,15 +1022,16 @@ type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 -use_default_range=false +use_default_range=true width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] type=BaseCache children=tags -addr_ranges=0:134217727 +addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain eventq_index=0 @@ -1046,8 +1050,8 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[26] -mem_side=system.membus.slave[2] +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] [system.iocache.tags] type=LRU @@ -1082,7 +1086,7 @@ tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.l2c.tags] type=LRU @@ -1105,8 +1109,8 @@ system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.system_port system.l2c.mem_side system.iocache.mem_side +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -1162,6 +1166,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -1171,7 +1176,7 @@ mem_sched_policy=frfcfs min_writes_per_switch=16 null=false page_policy=open_adaptive -range=0:134217727 +range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1200,46 +1205,37 @@ tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 -port=system.membus.master[6] +port=system.membus.master[5] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=0 +pci_cfg_base=805306368 pci_cfg_gen_offsets=false pci_io_base=0 system=system -[system.realview.a9scu] -type=A9SCU -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=520093696 -pio_latency=100000 -system=system -pio=system.membus.master[4] - [system.realview.aaci_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268451840 +pio_addr=470024192 pio_latency=100000 system=system -pio=system.iobus.master[21] +pio=system.iobus.master[18] [system.realview.cf_ctrl] type=IdeController -BAR0=402653184 +BAR0=471465984 BAR0LegacyIO=true -BAR0Size=16 -BAR1=402653440 +BAR0Size=256 +BAR1=471466240 BAR1LegacyIO=true -BAR1Size=1 +BAR1Size=4096 BAR2=1 BAR2LegacyIO=false BAR2Size=8 @@ -1309,18 +1305,18 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 -disks=system.cf0 +disks= eventq_index=0 -io_shift=1 +io_shift=2 pci_bus=2 -pci_dev=7 +pci_dev=0 pci_func=0 pio_latency=30000 platform=system.realview system=system -config=system.iobus.master[8] +config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.clcd] type=Pl111 @@ -1329,8 +1325,8 @@ clk_domain=system.clk_domain enable_capture=true eventq_index=0 gic=system.realview.gic -int_num=55 -pio_addr=268566528 +int_num=46 +pio_addr=471793664 pio_latency=10000 pixel_clock=41667 system=system @@ -1338,51 +1334,129 @@ vnc=system.vncserver dma=system.iobus.slave[1] pio=system.iobus.master[4] -[system.realview.dmac_fake] -type=AmbaFake -amba_id=0 +[system.realview.energy_ctrl] +type=EnergyCtrl clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler eventq_index=0 -ignore_access=false -pio_addr=268632064 +pio_addr=470286336 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[22] -[system.realview.energy_ctrl] -type=EnergyCtrl +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 clk_domain=system.clk_domain -dvfs_handler=system.dvfs_handler +config_latency=20000 eventq_index=0 -pio_addr=268496896 -pio_latency=100000 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] pio=system.iobus.master[25] -[system.realview.flash_fake] -type=IsaFake -clk_domain=system.clk_domain +[system.realview.generic_timer] +type=GenericTimer eventq_index=0 -fake_mem=true -pio_addr=1073741824 -pio_latency=100000 -pio_size=536870912 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 +gic=system.realview.gic +int_num=29 system=system -update_data=false -warn_access= -pio=system.iobus.master[24] [system.realview.gic] type=Pl390 clk_domain=system.clk_domain -cpu_addr=520093952 +cpu_addr=738205696 cpu_pio_delay=10000 -dist_addr=520097792 +dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 int_latency=10000 @@ -1392,38 +1466,111 @@ platform=system.realview system=system pio=system.membus.master[2] -[system.realview.gpio0_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268513280 -pio_latency=100000 -system=system -pio=system.iobus.master[16] - -[system.realview.gpio1_fake] -type=AmbaFake -amba_id=0 +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 clk_domain=system.clk_domain +enable_capture=true eventq_index=0 -ignore_access=false -pio_addr=268517376 -pio_latency=100000 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 system=system -pio=system.iobus.master[17] +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] -[system.realview.gpio2_fake] -type=AmbaFake -amba_id=0 +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 eventq_index=0 -ignore_access=false -pio_addr=268521472 -pio_latency=100000 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview system=system -pio=system.iobus.master[18] +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] [system.realview.kmi0] type=Pl050 @@ -1432,13 +1579,13 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=52 +int_num=44 is_mouse=false -pio_addr=268460032 +pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.kmi1] type=Pl050 @@ -1447,20 +1594,20 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=53 +int_num=45 is_mouse=true -pio_addr=268464128 +pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=false -pio_addr=520101888 +pio_addr=739246080 pio_latency=100000 pio_size=4095 ret_bad_addr=false @@ -1471,7 +1618,25 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[3] +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer @@ -1480,10 +1645,10 @@ eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 -pio_addr=520095232 +pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[3] [system.realview.mmc_fake] type=AmbaFake @@ -1491,10 +1656,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268455936 +pio_addr=470089728 pio_latency=100000 system=system -pio=system.iobus.master[22] +pio=system.iobus.master[21] [system.realview.nvmem] type=SimpleMemory @@ -1506,18 +1671,30 @@ in_addr_map=true latency=30000 latency_var=0 null=false -range=2147483648:2214592511 +range=0:67108863 port=system.membus.master[1] +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain eventq_index=0 -idreg=0 -pio_addr=268435456 +idreg=35979264 +pio_addr=469827584 pio_latency=100000 -proc_id0=201326592 -proc_id1=201327138 +proc_id0=335544320 +proc_id1=335544320 system=system pio=system.iobus.master[1] @@ -1528,34 +1705,12 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=42 -pio_addr=268529664 +int_num=36 +pio_addr=471269376 pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[23] - -[system.realview.sci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268492800 -pio_latency=100000 -system=system -pio=system.iobus.master[20] - -[system.realview.smc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=269357056 -pio_latency=100000 -system=system -pio=system.iobus.master[13] +pio=system.iobus.master[10] [system.realview.sp810_fake] type=AmbaFake @@ -1563,21 +1718,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=true -pio_addr=268439552 -pio_latency=100000 -system=system -pio=system.iobus.master[14] - -[system.realview.ssp_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268488704 +pio_addr=469893120 pio_latency=100000 system=system -pio=system.iobus.master[19] +pio=system.iobus.master[16] [system.realview.timer0] type=Sp804 @@ -1587,9 +1731,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=36 -int_num1=36 -pio_addr=268505088 +int_num0=34 +int_num1=34 +pio_addr=470876160 pio_latency=100000 system=system pio=system.iobus.master[2] @@ -1602,9 +1746,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=37 -int_num1=37 -pio_addr=268509184 +int_num0=35 +int_num1=35 +pio_addr=470941696 pio_latency=100000 system=system pio=system.iobus.master[3] @@ -1616,8 +1760,8 @@ end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=44 -pio_addr=268472320 +int_num=37 +pio_addr=470351872 pio_latency=100000 platform=system.realview system=system @@ -1630,10 +1774,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268476416 +pio_addr=470417408 pio_latency=100000 system=system -pio=system.iobus.master[10] +pio=system.iobus.master[13] [system.realview.uart2_fake] type=AmbaFake @@ -1641,10 +1785,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268480512 +pio_addr=470482944 pio_latency=100000 system=system -pio=system.iobus.master[11] +pio=system.iobus.master[14] [system.realview.uart3_fake] type=AmbaFake @@ -1652,10 +1796,54 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268484608 +pio_addr=470548480 pio_latency=100000 system=system -pio=system.iobus.master[12] +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] [system.realview.watchdog_fake] type=AmbaFake @@ -1663,10 +1851,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268500992 +pio_addr=470745088 pio_latency=100000 system=system -pio=system.iobus.master[15] +pio=system.iobus.master[17] [system.terminal] type=Terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index 41d09e09d..40aa358a7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -1,36 +1,55 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: LCD dual screen mode not supported -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] +warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] +warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] +warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3] +warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3] +warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1] +warn: Returning zero for read from miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr +warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2] +warn: instruction 'mcr bpiall' unimplemented +warn: instruction 'mcr dcisw' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0] +warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7] warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index bb9bfcfdd..6a3bc0040 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:22:42 -gem5 started Jun 21 2014 21:27:42 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:14:55 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 - 0: system.cpu1.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 - 0: system.cpu2.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 + 0: system.cpu0.isa: ISA system set to: 0x5395b00 0x5395b00 + 0: system.cpu1.isa: ISA system set to: 0x5395b00 0x5395b00 + 0: system.cpu2.isa: ISA system set to: 0x5395b00 0x5395b00 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 8dbd1b2bc..3943053d7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.400978 # Number of seconds simulated -sim_ticks 2400977890000 # Number of ticks simulated -final_tick 2400977890000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.817969 # Number of seconds simulated +sim_ticks 2817968959500 # Number of ticks simulated +final_tick 2817968959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187249 # Simulator instruction rate (inst/s) -host_op_rate 225312 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7454963168 # Simulator tick rate (ticks/s) -host_mem_usage 414124 # Number of bytes of host memory used -host_seconds 322.06 # Real time elapsed on the host -sim_insts 60306316 # Number of instructions simulated -sim_ops 72565030 # Number of ops (including micro ops) simulated +host_inst_rate 310224 # Simulator instruction rate (inst/s) +host_op_rate 376688 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6925358539 # Simulator tick rate (ticks/s) +host_mem_usage 560716 # Number of bytes of host memory used +host_seconds 406.91 # Real time elapsed on the host +sim_insts 126231917 # Number of instructions simulated +sim_ops 153276568 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 489736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6827544 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 652900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4386464 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 79168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 799488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 187904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1451008 # Number of bytes read from this memory -system.physmem.bytes_read::total 124654688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 489736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 79168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 187904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 756808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3741376 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1144160 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159264 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1712392 # Number of bytes written to this memory -system.physmem.bytes_written::total 6757192 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13864 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 106706 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 130944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1051396 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 6080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 516160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 4232384 # Number of bytes read from this memory +system.physmem.bytes_read::total 10977672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 652900 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 130944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 516160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1300004 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5945344 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory +system.physmem.bytes_written::total 8281204 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 18655 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 69057 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1237 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 12492 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 22672 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512303 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58459 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 286040 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39816 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 428098 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812413 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47821795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 203974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2843651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 332984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 78261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 604340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51918299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 203974 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 78261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1558272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 476539 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66333 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 713206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2814350 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1558272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47821795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 203974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3320191 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 399317 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 78261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1317546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54732649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13446786 # Number of read requests accepted -system.physmem.writeReqs 485691 # Number of write requests accepted -system.physmem.readBursts 13446786 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 485691 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 860594304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 3023744 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109777664 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3009384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 438423 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2870 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 835534 # Per bank write bursts -system.physmem.perBankRdBursts::1 835708 # Per bank write bursts -system.physmem.perBankRdBursts::2 835573 # Per bank write bursts -system.physmem.perBankRdBursts::3 835895 # Per bank write bursts -system.physmem.perBankRdBursts::4 836820 # Per bank write bursts -system.physmem.perBankRdBursts::5 838059 # Per bank write bursts -system.physmem.perBankRdBursts::6 838590 # Per bank write bursts -system.physmem.perBankRdBursts::7 839423 # Per bank write bursts -system.physmem.perBankRdBursts::8 841113 # Per bank write bursts -system.physmem.perBankRdBursts::9 843484 # Per bank write bursts -system.physmem.perBankRdBursts::10 843775 # Per bank write bursts -system.physmem.perBankRdBursts::11 843709 # Per bank write bursts -system.physmem.perBankRdBursts::12 845212 # Per bank write bursts -system.physmem.perBankRdBursts::13 845578 # Per bank write bursts -system.physmem.perBankRdBursts::14 844651 # Per bank write bursts -system.physmem.perBankRdBursts::15 843662 # Per bank write bursts -system.physmem.perBankWrBursts::0 2614 # Per bank write bursts -system.physmem.perBankWrBursts::1 2619 # Per bank write bursts -system.physmem.perBankWrBursts::2 2845 # Per bank write bursts -system.physmem.perBankWrBursts::3 3084 # Per bank write bursts -system.physmem.perBankWrBursts::4 3522 # Per bank write bursts -system.physmem.perBankWrBursts::5 3545 # Per bank write bursts -system.physmem.perBankWrBursts::6 2950 # Per bank write bursts -system.physmem.perBankWrBursts::7 2539 # Per bank write bursts -system.physmem.perBankWrBursts::8 2638 # Per bank write bursts -system.physmem.perBankWrBursts::9 2619 # Per bank write bursts -system.physmem.perBankWrBursts::10 2391 # Per bank write bursts -system.physmem.perBankWrBursts::11 2507 # Per bank write bursts -system.physmem.perBankWrBursts::12 3740 # Per bank write bursts -system.physmem.perBankWrBursts::13 3837 # Per bank write bursts -system.physmem.perBankWrBursts::14 3267 # Per bank write bursts -system.physmem.perBankWrBursts::15 2529 # Per bank write bursts +system.physmem.num_reads::cpu1.inst 2046 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 95 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 8065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 66131 # Number of read requests responded to by this memory +system.physmem.num_reads::total 180499 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 92896 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133501 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 231692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1556605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 46468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 373104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 2158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 183167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1501927 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3895597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 231692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 46468 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 183167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 461327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2109798 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 822697 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2938714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2109798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 823038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 231692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1562821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 46468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 373107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 2158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 183167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1501927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6834311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 92768 # Number of read requests accepted +system.physmem.writeReqs 67796 # Number of write requests accepted +system.physmem.readBursts 92768 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 67796 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5932800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4352 # Total number of bytes read from write queue +system.physmem.bytesWritten 4337152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5937092 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4338824 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 68 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2466 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6044 # Per bank write bursts +system.physmem.perBankRdBursts::1 5813 # Per bank write bursts +system.physmem.perBankRdBursts::2 5577 # Per bank write bursts +system.physmem.perBankRdBursts::3 6085 # Per bank write bursts +system.physmem.perBankRdBursts::4 5556 # Per bank write bursts +system.physmem.perBankRdBursts::5 5466 # Per bank write bursts +system.physmem.perBankRdBursts::6 6173 # Per bank write bursts +system.physmem.perBankRdBursts::7 6793 # Per bank write bursts +system.physmem.perBankRdBursts::8 6458 # Per bank write bursts +system.physmem.perBankRdBursts::9 6393 # Per bank write bursts +system.physmem.perBankRdBursts::10 5737 # Per bank write bursts +system.physmem.perBankRdBursts::11 5119 # Per bank write bursts +system.physmem.perBankRdBursts::12 5308 # Per bank write bursts +system.physmem.perBankRdBursts::13 5463 # Per bank write bursts +system.physmem.perBankRdBursts::14 5329 # Per bank write bursts +system.physmem.perBankRdBursts::15 5386 # Per bank write bursts +system.physmem.perBankWrBursts::0 4258 # Per bank write bursts +system.physmem.perBankWrBursts::1 3939 # Per bank write bursts +system.physmem.perBankWrBursts::2 4228 # Per bank write bursts +system.physmem.perBankWrBursts::3 4685 # Per bank write bursts +system.physmem.perBankWrBursts::4 4137 # Per bank write bursts +system.physmem.perBankWrBursts::5 4140 # Per bank write bursts +system.physmem.perBankWrBursts::6 4393 # Per bank write bursts +system.physmem.perBankWrBursts::7 4905 # Per bank write bursts +system.physmem.perBankWrBursts::8 4554 # Per bank write bursts +system.physmem.perBankWrBursts::9 4640 # Per bank write bursts +system.physmem.perBankWrBursts::10 4209 # Per bank write bursts +system.physmem.perBankWrBursts::11 3550 # Per bank write bursts +system.physmem.perBankWrBursts::12 4025 # Per bank write bursts +system.physmem.perBankWrBursts::13 4273 # Per bank write bursts +system.physmem.perBankWrBursts::14 3934 # Per bank write bursts +system.physmem.perBankWrBursts::15 3898 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2398976781000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 2816402816000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 13407440 # Read request sizes (log2) +system.physmem.readPktSize::2 1 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 39346 # Read request sizes (log2) +system.physmem.readPktSize::6 92767 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 467914 # Write request sizes (log2) +system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17777 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 878947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 855123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 852879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 944479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 861163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 917283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2393694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2315582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3029092 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 97091 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 88809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 83328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 80474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 16189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 16044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 30 # What read queue length does an incoming req see +system.physmem.writePktSize::6 67794 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 61106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,505 +178,520 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 866162 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 997.062961 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 964.716097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 145.162362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8098 0.93% 0.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8963 1.03% 1.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6105 0.70% 2.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 860 0.10% 2.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 965 0.11% 2.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 764 0.09% 2.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7665 0.88% 3.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 291 0.03% 3.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 832451 96.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 866162 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2588 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 5195.817620 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 249325.060826 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 2587 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2588 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2588 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.255796 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.093626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.104963 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 2 0.08% 0.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 1 0.04% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 3 0.12% 0.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.04% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 2 0.08% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 3 0.12% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 2 0.08% 0.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 2 0.08% 0.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 3 0.12% 0.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 555 21.45% 22.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.23% 22.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 738 28.52% 50.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1040 40.19% 91.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 103 3.98% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 50 1.93% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.54% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.43% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.50% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.19% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 7 0.27% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 6 0.23% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 5 0.19% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 6 0.23% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.15% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 5 0.19% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2588 # Writes before turning the bus around for reads -system.physmem.totQLat 347055171000 # Total ticks spent queuing -system.physmem.totMemAccLat 599182408500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67233930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25809.53 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 32855 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.580247 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.443796 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.847473 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12759 38.83% 38.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7721 23.50% 62.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2992 9.11% 71.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1702 5.18% 76.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1346 4.10% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 768 2.34% 83.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 529 1.61% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 557 1.70% 86.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4481 13.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32855 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3254 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.483712 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 540.107069 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3253 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3254 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3254 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.826060 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.875262 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.591008 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 4 0.12% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 2 0.06% 0.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.06% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 2 0.06% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 2712 83.34% 83.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 41 1.26% 84.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 34 1.04% 85.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 139 4.27% 90.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 131 4.03% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 8 0.25% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 4 0.12% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 9 0.28% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 18 0.55% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.09% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.22% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.12% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 99 3.04% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.06% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.12% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.09% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.09% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.03% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.09% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.06% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.06% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.28% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3254 # Writes before turning the bus around for reads +system.physmem.totQLat 1185317250 # Total ticks spent queuing +system.physmem.totMemAccLat 2923442250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 463500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12786.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44559.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.72 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.25 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31536.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.81 # Data bus utilization in percentage -system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.23 # Average read queue length when enqueuing -system.physmem.avgWrQLen 2.52 # Average write queue length when enqueuing -system.physmem.readRowHits 12587076 # Number of row buffer hits during reads -system.physmem.writeRowHits 40794 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.30 # Row buffer hit rate for writes -system.physmem.avgGap 172185.95 # Average gap between requests -system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2165163855000 # Time in different power states -system.physmem.memoryStateTime::REF 80173860000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.01 # Average write queue length when enqueuing +system.physmem.readRowHits 76736 # Number of row buffer hits during reads +system.physmem.writeRowHits 50876 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes +system.physmem.avgGap 17540686.68 # Average gap between requests +system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2704844342250 # Time in different power states +system.physmem.memoryStateTime::REF 94098160000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 155638381250 # Time in different power states +system.physmem.memoryStateTime::ACT 19026363250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3260847240 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3287337480 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1779232125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1793686125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 52225695600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 52659235200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 153692640 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 152461440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 156820070160 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 156820070160 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 104351437575 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 103839738030 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1349049300750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1349498160000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1667640276090 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1668050688435 # Total energy per rank (pJ) -system.physmem.averagePower::0 694.567634 # Core power per rank (mW) -system.physmem.averagePower::1 694.738569 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 15564561 # Transaction distribution -system.membus.trans_dist::ReadResp 15564561 # Transaction distribution -system.membus.trans_dist::WriteReq 763190 # Transaction distribution -system.membus.trans_dist::WriteResp 763190 # Transaction distribution -system.membus.trans_dist::Writeback 58459 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4572 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4572 # Transaction distribution -system.membus.trans_dist::ReadExReq 131741 # Transaction distribution -system.membus.trans_dist::ReadExResp 131741 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1895349 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4281819 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 28704768 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 28704768 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32986587 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390317 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7020 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16592808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18990169 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 114819072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 114819072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 133809241 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 216296 # Request fanout histogram +system.physmem.actEnergy::0 129865680 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 118518120 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 70859250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 64667625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 370554600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 352489800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 224758800 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 214377840 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184056000960 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184056000960 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 70810444215 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 69981019830 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1628666804250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1629394369500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1884329287755 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1884181443675 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.683537 # Core power per rank (mW) +system.physmem.averagePower::1 668.631072 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 74237 # Transaction distribution +system.membus.trans_dist::ReadResp 74236 # Transaction distribution +system.membus.trans_dist::WriteReq 27571 # Transaction distribution +system.membus.trans_dist::WriteResp 27571 # Transaction distribution +system.membus.trans_dist::Writeback 92896 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4548 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4551 # Transaction distribution +system.membus.trans_dist::ReadExReq 137042 # Transaction distribution +system.membus.trans_dist::ReadExResp 137042 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 579193 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 652020 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16939580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17102703 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2326464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2326464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19429167 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125 # Total snoops (count) +system.membus.snoop_fanout::samples 304844 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 216296 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 304844 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 216296 # Request fanout histogram -system.membus.reqLayer0.occupancy 410119000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 304844 # Request fanout histogram +system.membus.reqLayer0.occupancy 40698500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 415500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 463500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14677410500 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1676192784 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 33189927250 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.4 # Layer utilization (%) +system.membus.reqLayer5.occupancy 735391250 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 906935534 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 23918727 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63154 # number of replacements -system.l2c.tags.tagsinuse 50400.562310 # Cycle average of tags in use -system.l2c.tags.total_refs 1759923 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128542 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.691424 # Average number of references to valid blocks. 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of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1956732500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1667613000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2813363500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4480976500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.032028 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021817 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.007272 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989189 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.963834 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.516781 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.076923 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.066667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420225 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.525365 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.258007 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.146403 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.204977 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.035036 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.146403 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.204977 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035036 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63245.251858 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65302.659517 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62229.853073 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62166.504854 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67896.710660 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 64160.635671 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10005.112939 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.028084 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58243.129952 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61615.600882 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60414.790530 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10006.159475 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.840782 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57672.903132 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62404.844551 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61531.780757 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58718.382551 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62025.745314 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 60774.388564 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58366.318631 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62017.025896 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58718.382551 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62025.745314 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 60774.388564 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58366.318631 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62017.025896 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -823,167 +846,184 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2539315 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2539315 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763190 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763190 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 598065 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2933 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2933 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246953 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246953 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1813392 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5760169 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 30385 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 80672 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7684618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 57608092 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 84067517 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 138604 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 141862677 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 18229 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2196613 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 2443721 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2443718 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 692569 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 22776 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2771 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296449 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296449 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3616609 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484136 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29317 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88397 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6218459 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115187260 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97908723 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49396 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 156136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213301515 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 51755 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3431770 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.010631 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.102558 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 2196613 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3395286 98.94% 98.94% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36484 1.06% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2196613 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2287106157 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3431770 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2368040184 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2054352798 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 553500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 4200557665 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1912625851 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2014921824 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13149443 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11880425 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 33486737 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 39622630 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 15535704 # Transaction distribution -system.iobus.trans_dist::ReadResp 15535704 # Transaction distribution -system.iobus.trans_dist::WriteReq 8154 # Transaction distribution -system.iobus.trans_dist::WriteResp 8154 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 492 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1000 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 30188 # Transaction distribution +system.iobus.trans_dist::ReadResp 30188 # Transaction distribution +system.iobus.trans_dist::WriteReq 59010 # Transaction distribution +system.iobus.trans_dist::WriteResp 45563 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 9 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 13456 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 28704768 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 28704768 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 31087716 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39305 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 984 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2000 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2390317 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 114819072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 114819072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 117209389 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 8534000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159119 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 18213000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1569000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 352708000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 2719000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 13407440000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 717460000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15730000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 205242577 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 39802000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 33785464750 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) +system.iobus.respLayer3.occupancy 23020273 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1007,25 +1047,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6552093 # DTB read hits -system.cpu0.dtb.read_misses 5443 # DTB read misses -system.cpu0.dtb.write_hits 6067983 # DTB write hits -system.cpu0.dtb.write_misses 1816 # DTB write misses -system.cpu0.dtb.flush_tlb 554 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 496 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5219 # Number of entries that have been flushed from TLB +system.cpu0.dtb.read_hits 14476225 # DTB read hits +system.cpu0.dtb.read_misses 4878 # DTB read misses +system.cpu0.dtb.write_hits 11074159 # DTB write hits +system.cpu0.dtb.write_misses 931 # DTB write misses +system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 3272 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 108 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 947 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 162 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6557536 # DTB read accesses -system.cpu0.dtb.write_accesses 6069799 # DTB write accesses +system.cpu0.dtb.perms_faults 215 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14481103 # DTB read accesses +system.cpu0.dtb.write_accesses 11075090 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12620076 # DTB hits -system.cpu0.dtb.misses 7259 # DTB misses -system.cpu0.dtb.accesses 12627335 # DTB accesses +system.cpu0.dtb.hits 25550384 # DTB hits +system.cpu0.dtb.misses 5809 # DTB misses +system.cpu0.dtb.accesses 25556193 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1047,486 +1087,503 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30154576 # ITB inst hits -system.cpu0.itb.inst_misses 2994 # ITB inst misses +system.cpu0.itb.inst_hits 67954631 # ITB inst hits +system.cpu0.itb.inst_misses 2810 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 554 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 496 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2367 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb 189 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2005 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30157570 # ITB inst accesses -system.cpu0.itb.hits 30154576 # DTB hits -system.cpu0.itb.misses 2994 # DTB misses -system.cpu0.itb.accesses 30157570 # DTB accesses -system.cpu0.numCycles 109411317 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 67957441 # ITB inst accesses +system.cpu0.itb.hits 67954631 # DTB hits +system.cpu0.itb.misses 2810 # DTB misses +system.cpu0.itb.accesses 67957441 # DTB accesses +system.cpu0.numCycles 82556870 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29741333 # Number of instructions committed -system.cpu0.committedOps 36475405 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 32123717 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4289 # Number of float alu accesses -system.cpu0.num_func_calls 1120042 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3813280 # number of instructions that are conditional controls -system.cpu0.num_int_insts 32123717 # number of integer instructions -system.cpu0.num_fp_insts 4289 # number of float instructions -system.cpu0.num_int_register_reads 59486063 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21170898 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3327 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 964 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 109224829 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 14221647 # number of times the CC registers were written -system.cpu0.num_mem_refs 13081203 # number of memory refs -system.cpu0.num_load_insts 6727170 # Number of load instructions -system.cpu0.num_store_insts 6354033 # Number of store instructions -system.cpu0.num_idle_cycles 107121976.742744 # Number of idle cycles -system.cpu0.num_busy_cycles 2289340.257256 # Number of busy cycles -system.cpu0.not_idle_fraction 0.020924 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.979076 # Percentage of idle cycles -system.cpu0.Branches 5305474 # Number of branches fetched -system.cpu0.op_class::No_OpClass 11839 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 23401650 64.04% 64.07% # Class of executed instruction -system.cpu0.op_class::IntMult 45463 0.12% 64.20% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1432 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::MemRead 6727170 18.41% 82.61% # Class of executed instruction -system.cpu0.op_class::MemWrite 6354033 17.39% 100.00% # Class of executed instruction +system.cpu0.committedInsts 66160123 # Number of instructions committed +system.cpu0.committedOps 80652277 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 70891568 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5582 # Number of float alu accesses +system.cpu0.num_func_calls 7292026 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 8778447 # number of instructions that are conditional controls +system.cpu0.num_int_insts 70891568 # number of integer instructions +system.cpu0.num_fp_insts 5582 # number of float instructions +system.cpu0.num_int_register_reads 131506227 # number of times the integer registers were read +system.cpu0.num_int_register_writes 49334420 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4358 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 245867738 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 29383073 # number of times the CC registers were written +system.cpu0.num_mem_refs 26220754 # number of memory refs +system.cpu0.num_load_insts 14652166 # Number of load instructions +system.cpu0.num_store_insts 11568588 # Number of store instructions +system.cpu0.num_idle_cycles 77950731.061702 # Number of idle cycles +system.cpu0.num_busy_cycles 4606138.938298 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055794 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944206 # Percentage of idle cycles +system.cpu0.Branches 16465385 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2193 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 55784741 67.97% 67.97% # Class of executed instruction +system.cpu0.op_class::IntMult 58719 0.07% 68.05% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4540 0.01% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::MemRead 14652166 17.85% 85.90% # Class of executed instruction +system.cpu0.op_class::MemWrite 11568588 14.10% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 36541587 # Class of executed instruction +system.cpu0.op_class::total 82070947 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82908 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 899905 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.617888 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 41210869 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 900417 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.768648 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7755633000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.394938 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.639138 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.583812 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967568 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.011014 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020672 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999254 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 216 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43039595 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43039595 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29712798 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7804770 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3693301 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41210869 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29712798 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7804770 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3693301 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41210869 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29712798 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7804770 # number of overall hits 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# number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30156945 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7924396 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4057836 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42139177 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30156945 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7924396 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4057836 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42139177 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30156945 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7924396 # number of overall (read+write) accesses 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cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 104537930 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 104537930 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 67090157 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 21677955 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 12120896 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 100889008 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 67090157 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 21677955 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 12120896 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 100889008 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 67090157 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 21677955 # number of overall hits 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13450125930 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 67956672 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 21928102 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 12853831 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 102738605 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 67956672 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 21928102 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 12853831 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 102738605 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 67956672 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 21928102 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 12853831 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 102738605 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012751 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011408 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057021 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.018003 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012751 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011408 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.057021 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.018003 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012751 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011408 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.057021 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.018003 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13548.350570 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13727.065401 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7271.922440 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13548.350570 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13727.065401 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7271.922440 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13548.350570 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13727.065401 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7271.922440 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5408 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 341 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.896552 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.859238 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed 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overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11896.513401 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11545.382315 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11896.513401 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 630395 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997117 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21342587 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 630907 # Sample count of references to valid blocks. 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system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 92223227 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 92223227 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5368302 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1446025 # number of ReadReq hits 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LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 85070243 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1735296482 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 30586352016 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 32321648498 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1735296482 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 30586352016 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 32321648498 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5510865 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1491285 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4993264 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 11995414 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5652802 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1297317 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3266766 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216885 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 90665 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 31716 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 65444 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 187825 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 128648 # number of LoadLockedReq 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miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023035 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.251161 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.098347 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.408129 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.550731 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.638546 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.512493 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047074 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044020 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050320 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047828 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026603 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.026947 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.130522 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.065290 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029677 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032837 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.134515 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.069040 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13504.512793 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14020.850270 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9481.148188 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37614.851861 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32875.872638 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 27964.070981 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13505.363322 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14623.018737 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7098.651786 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23092.947967 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28370.212840 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22286.934122 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18737.476995 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27311.583864 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 20899.734562 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 35984 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 7309 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 5054 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 190 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.119905 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 38.468421 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 198572858 # Number of tag accesses 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number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 15721299 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 48506360 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013612 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013306 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035838 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.020758 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013434 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.010646 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.228508 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.082522 # miss rate for WriteReq accesses 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latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10902.316965 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38658.293090 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46242.623438 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42156.544929 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14140.986602 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13638.461729 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10253.701888 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13923.153846 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12066.733333 # average StoreCondReq miss latency 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average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 48.563953 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 598065 # number of writebacks -system.cpu0.dcache.writebacks::total 598065 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 80 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146918 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 146998 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 655 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 754285 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 754940 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 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of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28777206403 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42371083972 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71148290375 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.030296 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.022172 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.012996 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.022530 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.020265 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009340 # mshr miss rate for WriteReq accesses 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0.031065 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024109 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.012872 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11510.148296 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12196.929764 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11997.889488 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35333.812891 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32200.637628 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33160.299574 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15449.163132 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18464.335308 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17388.587965 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11503.633218 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12807.176632 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12462.128045 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20868.450282 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19682.264058 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20033.460061 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20051.719117 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19537.817928 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19693.973808 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 692569 # number of writebacks +system.cpu0.dcache.writebacks::total 692569 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 109 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 155609 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 155718 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1409743 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1409743 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1933 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6811 # number of LoadLockedReq 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of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6677175319 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 253255500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 658822506 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 912078006 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 21611000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 35809251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57420251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 154999 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 154999 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2022353867 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7571356914 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9593710781 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2275609367 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8230179420 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10505788787 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1019366000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1693120500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2712486500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 777844500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1314970500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092815000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1797210500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3008091000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4805301500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013282 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018218 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008073 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010646 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017900 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007425 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.244576 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.224044 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121872 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016125 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019870 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.009036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000093 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012184 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018081 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.007793 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014610 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020649 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.009022 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13217.873586 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13255.489335 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13245.359580 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36480.137164 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45391.659659 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43423.981212 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12823.063291 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15002.220335 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14326.207587 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15996.299038 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12420.829344 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13561.703118 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11923 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11923 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21687.673509 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26972.070614 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25654.376888 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20138.314206 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25352.804212 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24006.372550 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1560,25 +1617,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 1733555 # DTB read hits -system.cpu1.dtb.read_misses 1889 # DTB read misses -system.cpu1.dtb.write_hits 1370998 # DTB write hits -system.cpu1.dtb.write_misses 367 # DTB write misses -system.cpu1.dtb.flush_tlb 552 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 248 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1592 # Number of entries that have been flushed from TLB +system.cpu1.dtb.read_hits 4634872 # DTB read hits +system.cpu1.dtb.read_misses 1584 # DTB read misses +system.cpu1.dtb.write_hits 3276619 # DTB write hits +system.cpu1.dtb.write_misses 228 # DTB write misses +system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 104 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1208 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 28 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 77 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 1735444 # DTB read accesses -system.cpu1.dtb.write_accesses 1371365 # DTB write accesses +system.cpu1.dtb.perms_faults 51 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4636456 # DTB read accesses +system.cpu1.dtb.write_accesses 3276847 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3104553 # DTB hits -system.cpu1.dtb.misses 2256 # DTB misses -system.cpu1.dtb.accesses 3106809 # DTB accesses +system.cpu1.dtb.hits 7911491 # DTB hits +system.cpu1.dtb.misses 1812 # DTB misses +system.cpu1.dtb.accesses 7913303 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1600,98 +1657,98 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7924396 # ITB inst hits -system.cpu1.itb.inst_misses 1030 # ITB inst misses +system.cpu1.itb.inst_hits 21928102 # ITB inst hits +system.cpu1.itb.inst_misses 848 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 552 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 248 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 806 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 104 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 700 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7925426 # ITB inst accesses -system.cpu1.itb.hits 7924396 # DTB hits -system.cpu1.itb.misses 1030 # DTB misses -system.cpu1.itb.accesses 7925426 # DTB accesses -system.cpu1.numCycles 582686408 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 21928950 # ITB inst accesses +system.cpu1.itb.hits 21928102 # DTB hits +system.cpu1.itb.misses 848 # DTB misses +system.cpu1.itb.accesses 21928950 # DTB accesses +system.cpu1.numCycles 158012618 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7745878 # Number of instructions committed -system.cpu1.committedOps 9129746 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 8166989 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1689 # Number of float alu accesses -system.cpu1.num_func_calls 287006 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 983778 # number of instructions that are conditional controls -system.cpu1.num_int_insts 8166989 # number of integer instructions -system.cpu1.num_fp_insts 1689 # number of float instructions -system.cpu1.num_int_register_reads 14466592 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5466665 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1177 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 512 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 32997995 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 3759402 # number of times the CC registers were written -system.cpu1.num_mem_refs 3229777 # number of memory refs -system.cpu1.num_load_insts 1791377 # Number of load instructions -system.cpu1.num_store_insts 1438400 # Number of store instructions -system.cpu1.num_idle_cycles 548052403.807954 # Number of idle cycles -system.cpu1.num_busy_cycles 34634004.192046 # Number of busy cycles -system.cpu1.not_idle_fraction 0.059438 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.940562 # Percentage of idle cycles -system.cpu1.Branches 1348409 # Number of branches fetched -system.cpu1.op_class::No_OpClass 4600 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 6037827 65.04% 65.09% # Class of executed instruction -system.cpu1.op_class::IntMult 10088 0.11% 65.20% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 273 0.00% 65.21% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 65.21% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.21% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.21% # Class of executed instruction -system.cpu1.op_class::MemRead 1791377 19.30% 84.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 1438400 15.50% 100.00% # Class of executed instruction +system.cpu1.committedInsts 21219740 # Number of instructions committed +system.cpu1.committedOps 25418010 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22602371 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1626 # Number of float alu accesses +system.cpu1.num_func_calls 2405283 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2700826 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22602371 # number of integer instructions +system.cpu1.num_fp_insts 1626 # number of float instructions +system.cpu1.num_int_register_reads 41665137 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15857681 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1178 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 92378686 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9370916 # number of times the CC registers were written +system.cpu1.num_mem_refs 8126078 # number of memory refs +system.cpu1.num_load_insts 4682102 # Number of load instructions +system.cpu1.num_store_insts 3443976 # Number of store instructions +system.cpu1.num_idle_cycles 151526719.153884 # Number of idle cycles +system.cpu1.num_busy_cycles 6485898.846116 # Number of busy cycles +system.cpu1.not_idle_fraction 0.041047 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.958953 # Percentage of idle cycles +system.cpu1.Branches 5257577 # Number of branches fetched +system.cpu1.op_class::No_OpClass 36 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 17988056 68.83% 68.83% # Class of executed instruction +system.cpu1.op_class::IntMult 19009 0.07% 68.90% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1153 0.00% 68.91% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.91% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.91% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.91% # Class of executed instruction +system.cpu1.op_class::MemRead 4682102 17.92% 86.82% # Class of executed instruction +system.cpu1.op_class::MemWrite 3443976 13.18% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 9282565 # Class of executed instruction +system.cpu1.op_class::total 26134332 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 5846326 # Number of BP lookups -system.cpu2.branchPred.condPredicted 4388844 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 249586 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3633950 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2855743 # Number of BTB hits +system.cpu2.branchPred.lookups 17411527 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9465637 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 400782 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 10870560 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 8144126 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 78.585093 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 589622 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 15464 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 74.919103 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4071344 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21284 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1715,25 +1772,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 13911313 # DTB read hits -system.cpu2.dtb.read_misses 27890 # DTB read misses -system.cpu2.dtb.write_hits 3983127 # DTB write hits -system.cpu2.dtb.write_misses 9793 # DTB write misses -system.cpu2.dtb.flush_tlb 550 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2737 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 484 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch +system.cpu2.dtb.read_hits 9691496 # DTB read hits +system.cpu2.dtb.read_misses 37543 # DTB read misses +system.cpu2.dtb.write_hits 7160478 # DTB write hits +system.cpu2.dtb.write_misses 5658 # DTB write misses +system.cpu2.dtb.flush_tlb 181 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 2438 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 429 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 958 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 13939203 # DTB read accesses -system.cpu2.dtb.write_accesses 3992920 # DTB write accesses +system.cpu2.dtb.perms_faults 432 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 9729039 # DTB read accesses +system.cpu2.dtb.write_accesses 7166136 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 17894440 # DTB hits -system.cpu2.dtb.misses 37683 # DTB misses -system.cpu2.dtb.accesses 17932123 # DTB accesses +system.cpu2.dtb.hits 16851974 # DTB hits +system.cpu2.dtb.misses 43201 # DTB misses +system.cpu2.dtb.accesses 16895175 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1755,353 +1812,417 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4060759 # ITB inst hits -system.cpu2.itb.inst_misses 6577 # ITB inst misses +system.cpu2.itb.inst_hits 12855360 # ITB inst hits +system.cpu2.itb.inst_misses 6344 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 550 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 2055 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb 181 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 1760 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 2376 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1117 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4067336 # ITB inst accesses -system.cpu2.itb.hits 4060759 # DTB hits -system.cpu2.itb.misses 6577 # DTB misses -system.cpu2.itb.accesses 4067336 # DTB accesses -system.cpu2.numCycles 88050542 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 12861704 # ITB inst accesses +system.cpu2.itb.hits 12855360 # DTB hits +system.cpu2.itb.misses 6344 # DTB misses +system.cpu2.itb.accesses 12861704 # DTB accesses +system.cpu2.numCycles 69831868 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10519234 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32939379 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 5846326 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 3445365 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 74770225 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 681136 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 80231 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 505 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 954 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 72091 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 1265694 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 337 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4057838 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 153485 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2814 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 87049769 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 0.444404 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 1.631683 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 26744179 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 69131561 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 17411527 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 12215470 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 39628211 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2071717 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 92420 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 879 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 271 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 329715 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 101746 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 12853833 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 270796 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2796 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 67933721 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.223102 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.347801 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 79735168 91.60% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 627849 0.72% 92.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 697488 0.80% 93.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 764418 0.88% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 855506 0.98% 94.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 578096 0.66% 95.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 986877 1.13% 96.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 299514 0.34% 97.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2504853 2.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 49353657 72.65% 72.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 2396253 3.53% 76.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 1562027 2.30% 78.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4874890 7.18% 85.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1103608 1.62% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 705498 1.04% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 3873607 5.70% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 752096 1.11% 95.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3312085 4.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 87049769 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.066397 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.374096 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8593092 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 72401111 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 4830102 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 941679 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 282689 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 738219 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 58888 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34839136 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 197306 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 282689 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9053752 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 19270728 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13147343 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5254066 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 40040151 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33787886 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 74120 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 29496747 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 37523489 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1004110 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 36611560 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 154353600 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41662755 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 4122 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 28819307 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 7792237 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 344984 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 287406 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 5085187 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6095255 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 4404078 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 715172 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 1132058 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32032092 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 661150 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 38610720 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 45237 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 5536917 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12037471 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 230168 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 87049769 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.443548 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.240485 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 67933721 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.249335 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.989972 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 18652988 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 36886196 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 10385899 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1080677 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 927745 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 1311847 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 109670 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 59354899 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 355527 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 927745 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 19278335 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4338170 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 27085326 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 10827974 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5475942 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 56886251 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2445 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 940623 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 160571 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 3871890 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 58826776 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 261240527 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 63795075 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4266 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 48699577 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10127183 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 954335 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 890664 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 6273875 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 10281967 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 7932177 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 1385446 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1932065 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 54651944 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 672234 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 52014227 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 68047 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7311472 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 18464419 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 69301 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 67933721 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.765661 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.467889 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73601742 84.55% 84.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 4103417 4.71% 89.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2329810 2.68% 91.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2044829 2.35% 94.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2965004 3.41% 97.70% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 800473 0.92% 98.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 744836 0.86% 99.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 295465 0.34% 99.81% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 164193 0.19% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 47467313 69.87% 69.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6842474 10.07% 79.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 5093799 7.50% 87.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4189990 6.17% 93.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1618046 2.38% 95.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1073354 1.58% 97.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1126537 1.66% 99.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 361655 0.53% 99.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 160553 0.24% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 87049769 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 67933721 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 123164 5.43% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 2 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1963174 86.51% 91.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 182867 8.06% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 78426 9.72% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 375416 46.53% 56.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 353014 43.75% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 12079 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 20212271 52.35% 52.38% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 34343 0.09% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 410 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 14161220 36.68% 89.15% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 4190397 10.85% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 108 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 34458488 66.25% 66.25% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 39234 0.08% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 2870 0.01% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 9974787 19.18% 85.51% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 7538730 14.49% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 38610720 # Type of FU issued -system.cpu2.iq.rate 0.438506 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2269207 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.058771 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 166576049 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 38242231 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29605417 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 9604 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 5150 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 4304 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 40862730 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 5118 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 177793 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 52014227 # Type of FU issued +system.cpu2.iq.rate 0.744849 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 806857 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.015512 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 172827620 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 62668492 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 50413992 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9459 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4970 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 4171 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 52815881 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5095 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 266821 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1108149 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2013 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 17977 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 469749 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1614154 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1912 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 38579 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 795080 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5186465 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 3515984 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 131168 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 122536 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 282689 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 17818885 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 827114 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32812972 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 58820 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6095255 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 4404078 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 482366 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 63304 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 726253 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 17977 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 122015 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 106758 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 228773 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 38292590 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 14036165 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 280577 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 927745 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3243473 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 928988 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 55431586 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 93653 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 10281967 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 7932177 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 359829 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 34343 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 885724 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 38579 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 184691 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 163240 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 347931 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 51578613 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 9798052 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 392517 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 119730 # number of nop insts executed -system.cpu2.iew.exec_refs 18176329 # number of memory reference insts executed -system.cpu2.iew.exec_branches 4221740 # Number of branches executed -system.cpu2.iew.exec_stores 4140164 # Number of stores executed -system.cpu2.iew.exec_rate 0.434893 # Inst execution rate -system.cpu2.iew.wb_sent 34848706 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 29609721 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17270580 # num instructions producing a value -system.cpu2.iew.wb_consumers 30711387 # num instructions consuming a value +system.cpu2.iew.exec_nop 107408 # number of nop insts executed +system.cpu2.iew.exec_refs 17263080 # number of memory reference insts executed +system.cpu2.iew.exec_branches 9489180 # Number of branches executed +system.cpu2.iew.exec_stores 7465028 # Number of stores executed +system.cpu2.iew.exec_rate 0.738611 # Inst execution rate +system.cpu2.iew.wb_sent 51120326 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 50418163 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 26486298 # num instructions producing a value +system.cpu2.iew.wb_consumers 46021805 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.336281 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.562351 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.721994 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.575516 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 5477647 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 430982 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 191637 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 86152512 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.313795 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.238508 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8152826 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 602933 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 292644 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 66207639 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.713967 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.618930 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 77159399 89.56% 89.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4186602 4.86% 94.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1295333 1.50% 95.92% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 754876 0.88% 96.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 491618 0.57% 97.37% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 381305 0.44% 97.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 375733 0.44% 98.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 196216 0.23% 98.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1311430 1.52% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 48127363 72.69% 72.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 8089014 12.22% 84.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 3990999 6.03% 90.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 1725382 2.61% 93.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 875466 1.32% 94.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 621285 0.94% 95.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 1255109 1.90% 97.70% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 300211 0.45% 98.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1222810 1.85% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 86152512 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 22893469 # Number of instructions committed -system.cpu2.commit.committedOps 27034243 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 66207639 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 38915831 # Number of instructions committed +system.cpu2.commit.committedOps 47270058 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8921435 # Number of memory references committed -system.cpu2.commit.loads 4987106 # Number of loads committed -system.cpu2.commit.membars 117312 # Number of memory barriers committed -system.cpu2.commit.branches 3648396 # Number of branches committed -system.cpu2.commit.fp_insts 4270 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 23927319 # Number of committed integer instructions. -system.cpu2.commit.function_calls 341825 # Number of function calls committed. +system.cpu2.commit.refs 15804910 # Number of memory references committed +system.cpu2.commit.loads 8667813 # Number of loads committed +system.cpu2.commit.membars 226604 # Number of memory barriers committed +system.cpu2.commit.branches 8912074 # Number of branches committed +system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 41368724 # Number of committed integer instructions. +system.cpu2.commit.function_calls 1635579 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 18080099 66.88% 66.88% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 32299 0.12% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 410 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 4987106 18.45% 85.45% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3934329 14.55% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 31424362 66.48% 66.48% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 37916 0.08% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 2870 0.01% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 8667813 18.34% 84.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 7137097 15.10% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 27034243 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1311430 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 47270058 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1222810 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 116684345 # The number of ROB reads -system.cpu2.rob.rob_writes 65897015 # The number of ROB writes -system.cpu2.timesIdled 179321 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1000773 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3544672545 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 22819105 # Number of Instructions Simulated -system.cpu2.committedOps 26959879 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 3.858633 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 3.858633 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.259159 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.259159 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 45005013 # number of integer regfile reads -system.cpu2.int_regfile_writes 19153075 # number of integer regfile writes -system.cpu2.fp_regfile_reads 47120 # number of floating regfile reads -system.cpu2.fp_regfile_writes 45464 # number of floating regfile writes -system.cpu2.cc_regfile_reads 130804455 # number of cc regfile reads -system.cpu2.cc_regfile_writes 12559622 # number of cc regfile writes -system.cpu2.misc_regfile_reads 122469878 # number of misc regfile reads -system.cpu2.misc_regfile_writes 350259 # number of misc regfile writes -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.cpu2.rob.rob_reads 113043839 # The number of ROB reads +system.cpu2.rob.rob_writes 112575250 # The number of ROB writes +system.cpu2.timesIdled 280666 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1898147 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 5250079706 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 38852054 # Number of Instructions Simulated +system.cpu2.committedOps 47206281 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.797379 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.797379 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.556366 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.556366 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 56467494 # number of integer regfile reads +system.cpu2.int_regfile_writes 31953659 # number of integer regfile writes +system.cpu2.fp_regfile_reads 15852 # number of floating regfile reads +system.cpu2.fp_regfile_writes 13698 # number of floating regfile writes +system.cpu2.cc_regfile_reads 182453688 # number of cc regfile reads +system.cpu2.cc_regfile_writes 19285573 # number of cc regfile writes +system.cpu2.misc_regfile_reads 124185765 # number of misc regfile reads +system.cpu2.misc_regfile_writes 483246 # number of misc regfile writes +system.iocache.tags.replacements 36442 # number of replacements +system.iocache.tags.tagsinuse 0.992778 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 245004243009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.992778 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062049 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062049 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328356 # Number of tag accesses +system.iocache.tags.data_accesses 328356 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses +system.iocache.ReadReq_misses::total 252 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 9 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 9 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses +system.iocache.demand_misses::total 252 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 252 # number of overall misses +system.iocache.overall_misses::total 252 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 14192930 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 14192930 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 14192930 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14192930 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 14192930 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14192930 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36233 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36233 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000248 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000248 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 56321.150794 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 56321.150794 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 56321.150794 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 56321.150794 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536462300750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1536462300750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536462300750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1536462300750 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.ReadReq_mshr_misses::realview.ide 125 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 125 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 125 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 125 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 125 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 125 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 7692930 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 7692930 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 1401235920 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1401235920 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 7692930 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7692930 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 7692930 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7692930 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.496032 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.496032 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.496032 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61543.440000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 61543.440000 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal Binary files differindex f40477dbc..b3be0ec54 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal |