diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full')
3 files changed, 2140 insertions, 2151 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index 75a35f3bf..392d7b9c9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -48,13 +48,13 @@ Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is not active! -Command: 1, Timestamp: 3080, Bank: 4 +Command: 1, Timestamp: 3178, Bank: 4 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 7386, Bank: 2 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 2 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: Returning zero for read from miscreg pmcr @@ -66,12 +66,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[2] -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -92,22 +86,18 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index c781fe644..6d0661457 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 29 2015 17:36:13 -gem5 started Jul 29 2015 17:36:59 +gem5 compiled Jul 31 2015 14:34:49 +gem5 started Jul 31 2015 14:34:58 gem5 executing on e104799-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5/outgoing/gem5_3/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index d3cb3428e..c5b3bbc72 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,164 +1,164 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.823452 # Number of seconds simulated -sim_ticks 2823451688000 # Number of ticks simulated -final_tick 2823451688000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.823474 # Number of seconds simulated +sim_ticks 2823473696000 # Number of ticks simulated +final_tick 2823473696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 255579 # Simulator instruction rate (inst/s) -host_op_rate 310019 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5872606908 # Simulator tick rate (ticks/s) -host_mem_usage 578280 # Number of bytes of host memory used -host_seconds 480.78 # Real time elapsed on the host -sim_insts 122878254 # Number of instructions simulated -sim_ops 149051775 # Number of ops (including micro ops) simulated +host_inst_rate 536168 # Simulator instruction rate (inst/s) +host_op_rate 650376 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12315198448 # Simulator tick rate (ticks/s) +host_mem_usage 577764 # Number of bytes of host memory used +host_seconds 229.27 # Real time elapsed on the host +sim_insts 122925898 # Number of instructions simulated +sim_ops 149109939 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 538148 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3049124 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 121344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 892800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 537380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3052900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 121024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 891264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 373376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2020416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 355840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 3621312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 373952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2012736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 356480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 3623360 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10980232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 538148 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 121344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 373376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 355840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1388708 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8266880 # Number of bytes written to this memory +system.physmem.bytes_read::total 10976712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 537380 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 121024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 373952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 356480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1388836 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8247936 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8284404 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8265460 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16862 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 48162 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13950 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 33 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16850 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 48221 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1891 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13926 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5834 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 31569 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 69 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 5560 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 56583 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5843 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 31449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 66 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 5570 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 56615 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180539 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 129170 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180484 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 128874 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133551 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 133255 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 190599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1079928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 42977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 316209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 190326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1081257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 42864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 315662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 703 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 132241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 715584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 126030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1282583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 132444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 712858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 126256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1283299 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3888939 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 190599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 42977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 132241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 126030 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2927934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3887662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 190326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 42864 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 132444 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 126256 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 491889 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2921202 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6207 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2934141 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2927934 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2927408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2921202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 190599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1086134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 42977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 316209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 190326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1087463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 42864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 315662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 703 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 132241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 715584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 126030 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1282583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 132444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 712858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 126256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1283299 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6823080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 115495 # Number of read requests accepted -system.physmem.writeReqs 70322 # Number of write requests accepted -system.physmem.readBursts 115495 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 70322 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 7384064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue -system.physmem.bytesWritten 4499904 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 7391680 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4500608 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6815070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 115392 # Number of read requests accepted +system.physmem.writeReqs 70006 # Number of write requests accepted +system.physmem.readBursts 115392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 70006 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 7377600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue +system.physmem.bytesWritten 4479552 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 7385088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4480384 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 16728 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 7953 # Per bank write bursts -system.physmem.perBankRdBursts::1 7174 # Per bank write bursts -system.physmem.perBankRdBursts::2 7640 # Per bank write bursts -system.physmem.perBankRdBursts::3 7504 # Per bank write bursts -system.physmem.perBankRdBursts::4 7829 # Per bank write bursts -system.physmem.perBankRdBursts::5 7364 # Per bank write bursts -system.physmem.perBankRdBursts::6 7486 # Per bank write bursts -system.physmem.perBankRdBursts::7 7817 # Per bank write bursts -system.physmem.perBankRdBursts::8 7059 # Per bank write bursts -system.physmem.perBankRdBursts::9 7674 # Per bank write bursts -system.physmem.perBankRdBursts::10 7129 # Per bank write bursts -system.physmem.perBankRdBursts::11 6171 # Per bank write bursts -system.physmem.perBankRdBursts::12 6502 # Per bank write bursts -system.physmem.perBankRdBursts::13 7092 # Per bank write bursts -system.physmem.perBankRdBursts::14 6785 # Per bank write bursts -system.physmem.perBankRdBursts::15 6197 # Per bank write bursts -system.physmem.perBankWrBursts::0 4825 # Per bank write bursts -system.physmem.perBankWrBursts::1 4280 # Per bank write bursts -system.physmem.perBankWrBursts::2 4678 # Per bank write bursts -system.physmem.perBankWrBursts::3 4464 # Per bank write bursts -system.physmem.perBankWrBursts::4 4644 # Per bank write bursts -system.physmem.perBankWrBursts::5 4512 # Per bank write bursts -system.physmem.perBankWrBursts::6 4517 # Per bank write bursts -system.physmem.perBankWrBursts::7 4571 # Per bank write bursts -system.physmem.perBankWrBursts::8 4335 # Per bank write bursts -system.physmem.perBankWrBursts::9 5017 # Per bank write bursts -system.physmem.perBankWrBursts::10 4515 # Per bank write bursts -system.physmem.perBankWrBursts::11 3667 # Per bank write bursts -system.physmem.perBankWrBursts::12 3925 # Per bank write bursts -system.physmem.perBankWrBursts::13 4539 # Per bank write bursts -system.physmem.perBankWrBursts::14 4104 # Per bank write bursts -system.physmem.perBankWrBursts::15 3718 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 16729 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 7736 # Per bank write bursts +system.physmem.perBankRdBursts::1 7063 # Per bank write bursts +system.physmem.perBankRdBursts::2 7688 # Per bank write bursts +system.physmem.perBankRdBursts::3 7632 # Per bank write bursts +system.physmem.perBankRdBursts::4 7697 # Per bank write bursts +system.physmem.perBankRdBursts::5 7461 # Per bank write bursts +system.physmem.perBankRdBursts::6 7652 # Per bank write bursts +system.physmem.perBankRdBursts::7 7853 # Per bank write bursts +system.physmem.perBankRdBursts::8 7016 # Per bank write bursts +system.physmem.perBankRdBursts::9 7651 # Per bank write bursts +system.physmem.perBankRdBursts::10 6943 # Per bank write bursts +system.physmem.perBankRdBursts::11 6411 # Per bank write bursts +system.physmem.perBankRdBursts::12 6488 # Per bank write bursts +system.physmem.perBankRdBursts::13 7344 # Per bank write bursts +system.physmem.perBankRdBursts::14 6713 # Per bank write bursts +system.physmem.perBankRdBursts::15 5927 # Per bank write bursts +system.physmem.perBankWrBursts::0 4604 # Per bank write bursts +system.physmem.perBankWrBursts::1 4172 # Per bank write bursts +system.physmem.perBankWrBursts::2 4724 # Per bank write bursts +system.physmem.perBankWrBursts::3 4597 # Per bank write bursts +system.physmem.perBankWrBursts::4 4526 # Per bank write bursts +system.physmem.perBankWrBursts::5 4564 # Per bank write bursts +system.physmem.perBankWrBursts::6 4573 # Per bank write bursts +system.physmem.perBankWrBursts::7 4592 # Per bank write bursts +system.physmem.perBankWrBursts::8 4263 # Per bank write bursts +system.physmem.perBankWrBursts::9 4993 # Per bank write bursts +system.physmem.perBankWrBursts::10 4344 # Per bank write bursts +system.physmem.perBankWrBursts::11 3939 # Per bank write bursts +system.physmem.perBankWrBursts::12 3901 # Per bank write bursts +system.physmem.perBankWrBursts::13 4724 # Per bank write bursts +system.physmem.perBankWrBursts::14 4019 # Per bank write bursts +system.physmem.perBankWrBursts::15 3458 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2821880880500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 2821902889500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 115495 # Read request sizes (log2) +system.physmem.readPktSize::6 115392 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 70322 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 87424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 24888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 550 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 70006 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 87082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 25035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -188,125 +188,129 @@ system.physmem.rdQLenPdf::30 0 # Wh system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 70 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 64 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 62 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 60 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 59 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.674709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.286017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.421202 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15628 39.28% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9455 23.76% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3888 9.77% 72.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2213 5.56% 78.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1604 4.03% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 939 2.36% 84.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 730 1.83% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 629 1.58% 88.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4703 11.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39789 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3745 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.804539 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 621.520984 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 3744 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.819355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.296873 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.728623 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15567 39.23% 39.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9452 23.82% 63.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3895 9.82% 72.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2106 5.31% 78.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1684 4.24% 82.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 926 2.33% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 731 1.84% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 606 1.53% 88.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4713 11.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39680 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3702 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 31.134792 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 625.115005 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 3701 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3745 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3745 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.774633 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.746790 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.292289 # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 3702 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3702 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.906807 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.729572 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.893119 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::0-3 6 0.16% 0.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 3 0.08% 0.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.03% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.13% 0.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3351 89.48% 89.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 51 1.36% 91.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 76 2.03% 93.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 45 1.20% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 29 0.77% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 68 1.82% 97.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 12 0.32% 97.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.27% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 5 0.13% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.11% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.08% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.03% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 57 1.52% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.11% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.13% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.08% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3745 # Writes before turning the bus around for reads -system.physmem.totQLat 1373444750 # Total ticks spent queuing -system.physmem.totMemAccLat 3536744750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 576880000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11904.08 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::4-7 2 0.05% 0.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.05% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 7 0.19% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3319 89.65% 90.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 56 1.51% 91.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 61 1.65% 93.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 52 1.40% 94.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 33 0.89% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 54 1.46% 97.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.38% 97.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 4 0.11% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.27% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.05% 97.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.03% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.03% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 54 1.46% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.08% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.08% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.05% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.03% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.14% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.11% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3702 # Writes before turning the bus around for reads +system.physmem.totQLat 1386684000 # Total ticks spent queuing +system.physmem.totMemAccLat 3548090250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 576375000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12029.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30654.08 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.62 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30779.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.61 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.62 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s @@ -315,40 +319,40 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 28.79 # Average write queue length when enqueuing -system.physmem.readRowHits 95547 # Number of row buffer hits during reads -system.physmem.writeRowHits 50351 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.60 # Row buffer hit rate for writes -system.physmem.avgGap 15186343.99 # Average gap between requests -system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 160211520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 87256125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 473982600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 236461680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179691539040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72230311935 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1621102009500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1873981772400 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.506366 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2640519481750 # Time in different power states -system.physmem_0.memoryStateTime::REF 91866840000 # Time in different power states +system.physmem.avgWrQLen 19.44 # Average write queue length when enqueuing +system.physmem.readRowHits 95329 # Number of row buffer hits during reads +system.physmem.writeRowHits 50259 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.79 # Row buffer hit rate for writes +system.physmem.avgGap 15220783.88 # Average gap between requests +system.physmem.pageHitRate 78.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 160733160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 87536625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 474099600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 235560960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179692556160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 72207385965 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1621122462750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1873980335220 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.505718 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2640566607500 # Time in different power states +system.physmem_0.memoryStateTime::REF 91867360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18811132750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18778047250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140593320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76547625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 425950200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 219153600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179691539040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 71075732760 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1618530580500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1870160097045 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.565551 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2642231800750 # Time in different power states -system.physmem_1.memoryStateTime::REF 91866840000 # Time in different power states +system.physmem_1.actEnergy 139247640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 75805125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 425045400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 217993680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179692556160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 71111774430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1616695526250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1868357948685 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.638582 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2642185763250 # Time in different power states +system.physmem_1.memoryStateTime::REF 91867360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17099623500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17159721000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -398,47 +402,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5044 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5044 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5044 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5044 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5044 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 56727881876 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.269097 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -15265283124 -26.91% -26.91% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993165000 126.91% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 56727881876 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2868 68.19% 68.19% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1338 31.81% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4206 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5044 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 5013 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5013 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5013 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5013 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5013 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 56727642376 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.269102 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -15265500874 -26.91% -26.91% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993143250 126.91% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 56727642376 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2853 68.40% 68.40% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1318 31.60% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4171 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5013 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5044 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4206 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5013 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4171 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4206 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9250 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4171 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9184 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12055693 # DTB read hits -system.cpu0.dtb.read_misses 4324 # DTB read misses -system.cpu0.dtb.write_hits 9053768 # DTB write hits -system.cpu0.dtb.write_misses 720 # DTB write misses +system.cpu0.dtb.read_hits 12054005 # DTB read hits +system.cpu0.dtb.read_misses 4307 # DTB read misses +system.cpu0.dtb.write_hits 9056572 # DTB write hits +system.cpu0.dtb.write_misses 706 # DTB write misses system.cpu0.dtb.flush_tlb 172 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 358 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2916 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2897 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 817 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 829 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 183 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12060017 # DTB read accesses -system.cpu0.dtb.write_accesses 9054488 # DTB write accesses +system.cpu0.dtb.perms_faults 179 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12058312 # DTB read accesses +system.cpu0.dtb.write_accesses 9057278 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21109461 # DTB hits -system.cpu0.dtb.misses 5044 # DTB misses -system.cpu0.dtb.accesses 21114505 # DTB accesses +system.cpu0.dtb.hits 21110577 # DTB hits +system.cpu0.dtb.misses 5013 # DTB misses +system.cpu0.dtb.accesses 21115590 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,650 +472,648 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2455 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2455 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2455 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2455 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2455 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 56727881876 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.269099 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -15265389124 -26.91% -26.91% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993271000 126.91% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 56727881876 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1346 75.11% 75.11% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 446 24.89% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1792 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2456 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2456 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2456 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2456 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2456 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 56727642376 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.269104 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -15265627374 -26.91% -26.91% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993269750 126.91% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 56727642376 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1347 75.13% 75.13% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 446 24.87% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1793 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2455 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2455 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2456 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2456 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1792 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1792 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4247 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56652194 # ITB inst hits -system.cpu0.itb.inst_misses 2455 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1793 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1793 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4249 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56651895 # ITB inst hits +system.cpu0.itb.inst_misses 2456 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 172 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 358 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1791 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1793 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56654649 # ITB inst accesses -system.cpu0.itb.hits 56652194 # DTB hits -system.cpu0.itb.misses 2455 # DTB misses -system.cpu0.itb.accesses 56654649 # DTB accesses -system.cpu0.numCycles 68394939 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56654351 # ITB inst accesses +system.cpu0.itb.hits 56651895 # DTB hits +system.cpu0.itb.misses 2456 # DTB misses +system.cpu0.itb.accesses 56654351 # DTB accesses +system.cpu0.numCycles 68396174 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 55195414 # Number of instructions committed -system.cpu0.committedOps 66855615 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58673965 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4653 # Number of float alu accesses -system.cpu0.num_func_calls 5764786 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7314754 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58673965 # number of integer instructions -system.cpu0.num_fp_insts 4653 # number of float instructions -system.cpu0.num_int_register_reads 108155823 # number of times the integer registers were read -system.cpu0.num_int_register_writes 40952580 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3548 # number of times the floating registers were read +system.cpu0.committedInsts 55195315 # Number of instructions committed +system.cpu0.committedOps 66856964 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58675450 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4621 # Number of float alu accesses +system.cpu0.num_func_calls 5764530 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7314757 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58675450 # number of integer instructions +system.cpu0.num_fp_insts 4621 # number of float instructions +system.cpu0.num_int_register_reads 108161484 # number of times the integer registers were read +system.cpu0.num_int_register_writes 40950551 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3516 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1106 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 203459813 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 24562816 # number of times the CC registers were written -system.cpu0.num_mem_refs 21693456 # number of memory refs -system.cpu0.num_load_insts 12204686 # Number of load instructions -system.cpu0.num_store_insts 9488770 # Number of store instructions -system.cpu0.num_idle_cycles 64604124.391568 # Number of idle cycles -system.cpu0.num_busy_cycles 3790814.608432 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055425 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944575 # Percentage of idle cycles -system.cpu0.Branches 13394268 # Number of branches fetched +system.cpu0.num_cc_register_reads 203464939 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 24566154 # number of times the CC registers were written +system.cpu0.num_mem_refs 21694661 # number of memory refs +system.cpu0.num_load_insts 12202966 # Number of load instructions +system.cpu0.num_store_insts 9491695 # Number of store instructions +system.cpu0.num_idle_cycles 64604771.704346 # Number of idle cycles +system.cpu0.num_busy_cycles 3791402.295654 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055433 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944567 # Percentage of idle cycles +system.cpu0.Branches 13394190 # Number of branches fetched system.cpu0.op_class::No_OpClass 2179 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46192687 67.99% 67.99% # Class of executed instruction -system.cpu0.op_class::IntMult 50556 0.07% 68.07% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3909 0.01% 68.07% # Class of executed instruction +system.cpu0.op_class::IntAlu 46192822 67.99% 67.99% # Class of executed instruction +system.cpu0.op_class::IntMult 50582 0.07% 68.06% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.06% # 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Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 45958483 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 834002 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.105963 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.291122 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.712491 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.320971 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 14.672094 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938069 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022876 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010393 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.028656 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.294893 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.112781 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.133577 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 11.455419 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.943935 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.021705 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011980 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.022374 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193272549 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193272549 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11424997 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 3591571 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4056566 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6785067 # 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number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70208 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 90799 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 193340724 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 193340724 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11422910 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 3593204 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4066922 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 6785601 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25868637 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 8719261 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 2659250 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 3172966 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 4237084 # 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number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 72811 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 95206 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460595 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20141573 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 6243916 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7229425 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 11024749 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44639663 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20318776 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 6297641 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7297487 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 11112719 # number of overall hits -system.cpu0.dcache.overall_hits::total 45026623 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170763 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 51416 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 83405 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 222894 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 528478 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 111802 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 33494 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 105638 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 1237063 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1487997 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54554 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 16796 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 18757 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 47065 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 137172 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3717 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2279 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3522 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8436 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17954 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 17 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 282565 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 7007961 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26386679 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 8828378 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 2685839 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3278497 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu3.data 5476745 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 20269459 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 231757 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 70521 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 86819 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 135035 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 524132 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 219659 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 76282 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 73730 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 99235 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 468906 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216983 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 75596 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 72811 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 95223 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460613 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 20424138 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 6328826 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7418468 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 12484706 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 46656138 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 20655895 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 6399347 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7505287 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 12619741 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 47180270 # 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miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.020210 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031820 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.020064 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012674 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.012497 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.032203 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.225732 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.073314 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.235097 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.238430 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.216786 # 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number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3884752500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 7036068902 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13117689902 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 706453000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1317087500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1529047000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3552587500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 543393000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 982352000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1199505482 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725250482 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1249846000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2299439500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2728552482 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6277837982 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014111 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018160 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016042 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012497 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017351 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017706 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009245 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.233908 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.175708 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.238923 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.122092 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.009139 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.014888 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.031110 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010403 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000221 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013425 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017803 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016772 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.009142 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.015860 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019628 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019141 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.010395 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15038.475778 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13385.873329 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14347.964026 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14193.907574 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35905.609960 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47073.005392 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50597.498590 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46904.040263 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12835.468399 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13687.762881 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15503.614533 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14383.788604 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12699.852507 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14433.696639 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16595.117311 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15577.336307 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 26352.941176 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26352.941176 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23279.335471 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27913.900313 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 31142.117848 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28579.218129 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21580.916837 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26443.840026 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29058.350364 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26729.093921 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172546.316557 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 194811.925245 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202408.387353 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192956.989247 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169928.615863 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 190084.563107 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200023.659723 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189725.600863 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171397.857533 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 192764.673730 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 201353.022271 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191540.817023 # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15030.672759 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13366.759973 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14326.459549 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14175.467416 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35922.176329 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46929.420244 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50865.031911 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46987.629724 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12986.466892 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13599.298912 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15455.931307 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14373.790203 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12677.857143 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14793.339416 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16682.186892 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15683.169332 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 27500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23293.918879 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27801.761615 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 31239.640092 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28589.474404 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21615.275250 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26332.484901 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29138.601237 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26736.365827 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172389.702294 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 194864.255067 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202388.749173 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192949.570932 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169651.264440 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 190193.998064 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200017.589128 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189714.617612 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171188.330366 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 192841.286481 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 201339.468861 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191531.805290 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1978248 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.476093 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 92919349 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1978760 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 46.958372 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12310007500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 437.578218 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 12.969081 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 27.366613 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 33.562181 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.854645 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025330 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.053450 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.065551 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1976565 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.476096 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 92948208 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1977077 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 47.012943 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 12310006500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 437.069776 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 12.930889 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 27.368710 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 34.106720 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.853652 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025256 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.053455 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu3.inst 0.066615 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998977 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 253 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 260 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 96919206 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 96919206 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 55909224 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 17523727 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 10076714 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu3.inst 9409684 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 92919349 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 55909224 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 17523727 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 10076714 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu3.inst 9409684 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 92919349 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 55909224 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 17523727 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 10076714 # number of overall hits -system.cpu0.icache.overall_hits::cpu3.inst 9409684 # number of overall hits -system.cpu0.icache.overall_hits::total 92919349 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 744762 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 210607 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 478701 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu3.inst 586999 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2021069 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 744762 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 210607 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 478701 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu3.inst 586999 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2021069 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 744762 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 210607 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 478701 # number of overall misses -system.cpu0.icache.overall_misses::cpu3.inst 586999 # number of overall misses -system.cpu0.icache.overall_misses::total 2021069 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2873833000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6639070000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 7864379492 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 17377282492 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2873833000 # 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number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 15750211492 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011887 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045177 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.054386 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012976 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011887 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045177 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.054386 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012976 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011887 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045177 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054386 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012976 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12641.969806 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12873.409573 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12753.797074 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.025821 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12641.969806 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12873.409573 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12753.797074 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.025821 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12641.969806 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12873.409573 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12753.797074 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.025821 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1142,62 +1144,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 1892 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 1892 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 543 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1348 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 1891 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 1891 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 1891 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1530 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11241.830065 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9576.039480 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6337.675963 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.98% 0.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-6143 582 38.04% 39.02% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::10240-12287 519 33.92% 72.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-14335 132 8.63% 81.57% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::14336-16383 18 1.18% 82.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::22528-24575 264 17.25% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1530 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1775778416 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.436843 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.495995 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000042500 56.32% 56.32% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 775735916 43.68% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1775778416 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 996 65.14% 65.14% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 533 34.86% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1529 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1892 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 1944 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1944 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 547 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1397 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1944 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1944 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1944 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1569 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12632.887189 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11014.350507 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6231.121643 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.96% 0.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-6143 406 25.88% 26.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::10240-12287 522 33.27% 60.10% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-14335 230 14.66% 74.76% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::14336-16383 77 4.91% 79.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::22528-24575 319 20.33% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1569 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1032 65.77% 65.77% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 537 34.23% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1569 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1944 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1892 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1529 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1944 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1569 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1529 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3421 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1569 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3513 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3793903 # DTB read hits -system.cpu1.dtb.read_misses 1653 # DTB read misses -system.cpu1.dtb.write_hits 2764720 # DTB write hits -system.cpu1.dtb.write_misses 239 # DTB write misses +system.cpu1.dtb.read_hits 3796186 # DTB read hits +system.cpu1.dtb.read_misses 1676 # DTB read misses +system.cpu1.dtb.write_hits 2772085 # DTB write hits +system.cpu1.dtb.write_misses 268 # DTB write misses system.cpu1.dtb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 168 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1225 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1249 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 236 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 70 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3795556 # DTB read accesses -system.cpu1.dtb.write_accesses 2764959 # DTB write accesses +system.cpu1.dtb.perms_faults 75 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3797862 # DTB read accesses +system.cpu1.dtb.write_accesses 2772353 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6558623 # DTB hits -system.cpu1.dtb.misses 1892 # DTB misses -system.cpu1.dtb.accesses 6560515 # DTB accesses +system.cpu1.dtb.hits 6568271 # DTB hits +system.cpu1.dtb.misses 1944 # DTB misses +system.cpu1.dtb.accesses 6570215 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1227,128 +1225,128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 978 # Table walker walks requested -system.cpu1.itb.walker.walksShort 978 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walks 1001 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1001 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 197 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 781 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 978 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 978 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 978 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 708 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11807.909605 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9972.994087 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6711.668965 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 268 37.85% 37.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 195 27.54% 65.40% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 96 13.56% 78.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 3 0.42% 79.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 146 20.62% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 708 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1000001500 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000001500 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000001500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 511 72.18% 72.18% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 197 27.82% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 708 # Table walker page sizes translated +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 804 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1001 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1001 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1001 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 723 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12766.251729 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11015.623409 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6540.201330 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 211 29.18% 29.18% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 195 26.97% 56.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 151 20.89% 77.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 4 0.55% 77.59% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 162 22.41% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 723 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 526 72.75% 72.75% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 197 27.25% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 723 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 978 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 978 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1001 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1001 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 708 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 708 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1686 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 17734334 # ITB inst hits -system.cpu1.itb.inst_misses 978 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 723 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 723 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1724 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 17742437 # ITB inst hits +system.cpu1.itb.inst_misses 1001 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 168 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 735 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 750 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 17735312 # ITB inst accesses -system.cpu1.itb.hits 17734334 # DTB hits -system.cpu1.itb.misses 978 # DTB misses -system.cpu1.itb.accesses 17735312 # DTB accesses -system.cpu1.numCycles 143538852 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 17743438 # ITB inst accesses +system.cpu1.itb.hits 17742437 # DTB hits +system.cpu1.itb.misses 1001 # DTB misses +system.cpu1.itb.accesses 17743438 # DTB accesses +system.cpu1.numCycles 143583360 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 17131755 # Number of instructions committed -system.cpu1.committedOps 20672467 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18427801 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1229 # Number of float alu accesses -system.cpu1.num_func_calls 2005849 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2182476 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18427801 # number of integer instructions -system.cpu1.num_fp_insts 1229 # number of float instructions -system.cpu1.num_int_register_reads 34218314 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12924255 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 840 # number of times the floating registers were read +system.cpu1.committedInsts 17142475 # Number of instructions committed +system.cpu1.committedOps 20690900 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18446976 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1261 # Number of float alu accesses +system.cpu1.num_func_calls 2007420 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2180791 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18446976 # number of integer instructions +system.cpu1.num_fp_insts 1261 # number of float instructions +system.cpu1.num_int_register_reads 34256544 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12938178 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 872 # number of times the floating registers were read system.cpu1.num_fp_register_writes 390 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 75293665 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7369592 # number of times the CC registers were written -system.cpu1.num_mem_refs 6757135 # number of memory refs -system.cpu1.num_load_insts 3837451 # Number of load instructions -system.cpu1.num_store_insts 2919684 # Number of store instructions -system.cpu1.num_idle_cycles 136561451.428475 # Number of idle cycles -system.cpu1.num_busy_cycles 6977400.571525 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048610 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951390 # Percentage of idle cycles -system.cpu1.Branches 4295209 # Number of branches fetched +system.cpu1.num_cc_register_reads 75360742 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7365753 # number of times the CC registers were written +system.cpu1.num_mem_refs 6767228 # number of memory refs +system.cpu1.num_load_insts 3839902 # Number of load instructions +system.cpu1.num_store_insts 2927326 # Number of store instructions +system.cpu1.num_idle_cycles 136602426.841061 # Number of idle cycles +system.cpu1.num_busy_cycles 6980933.158939 # Number of busy cycles +system.cpu1.not_idle_fraction 0.048619 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.951381 # Percentage of idle cycles +system.cpu1.Branches 4294582 # Number of branches fetched system.cpu1.op_class::No_OpClass 47 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14510863 68.17% 68.17% # Class of executed instruction -system.cpu1.op_class::IntMult 16280 0.08% 68.25% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 958 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.25% # Class of executed instruction -system.cpu1.op_class::MemRead 3837451 18.03% 86.28% # Class of executed instruction -system.cpu1.op_class::MemWrite 2919684 13.72% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14519635 68.15% 68.15% # Class of executed instruction +system.cpu1.op_class::IntMult 16307 0.08% 68.23% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 962 0.00% 68.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.24% # Class of executed instruction +system.cpu1.op_class::MemRead 3839902 18.02% 86.26% # Class of executed instruction +system.cpu1.op_class::MemWrite 2927326 13.74% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21285283 # Class of executed instruction +system.cpu1.op_class::total 21304179 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 5610171 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2857915 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 501995 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3283896 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2333083 # Number of BTB hits +system.cpu2.branchPred.lookups 5611894 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2863788 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 506095 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3300567 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2344817 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.046190 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1583798 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 327364 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.042854 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1575596 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 331093 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1378,56 +1376,56 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 12445 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 12445 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7726 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4719 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 12445 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 12445 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 12445 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2100 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 12636.428571 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 10856.238054 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 6881.912938 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 609 29.00% 29.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1011 48.14% 77.14% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 478 22.76% 99.90% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walks 12465 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 12465 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7792 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4673 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 12465 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 12465 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 12465 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2089 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 13064.145524 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 11307.663622 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 6855.441685 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 538 25.75% 25.75% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1043 49.93% 75.68% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 506 24.22% 99.90% # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.10% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2100 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 2000071000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0 2000071000 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 2000071000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1328 63.24% 63.24% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 772 36.76% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2100 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12445 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkCompletionTime::total 2089 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 2000070000 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0 2000070000 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 2000070000 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 1323 63.33% 63.33% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 766 36.67% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2089 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12465 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12445 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2100 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12465 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2089 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2100 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 14545 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2089 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 14554 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4343761 # DTB read hits -system.cpu2.dtb.read_misses 11112 # DTB read misses -system.cpu2.dtb.write_hits 3378115 # DTB write hits -system.cpu2.dtb.write_misses 1333 # DTB write misses +system.cpu2.dtb.read_hits 4354485 # DTB read hits +system.cpu2.dtb.read_misses 11147 # DTB read misses +system.cpu2.dtb.write_hits 3379229 # DTB write hits +system.cpu2.dtb.write_misses 1318 # DTB write misses system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1535 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 222 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 1531 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 193 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 294 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 123 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4354873 # DTB read accesses -system.cpu2.dtb.write_accesses 3379448 # DTB write accesses +system.cpu2.dtb.perms_faults 117 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4365632 # DTB read accesses +system.cpu2.dtb.write_accesses 3380547 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 7721876 # DTB hits -system.cpu2.dtb.misses 12445 # DTB misses -system.cpu2.dtb.accesses 7734321 # DTB accesses +system.cpu2.dtb.hits 7733714 # DTB hits +system.cpu2.dtb.misses 12465 # DTB misses +system.cpu2.dtb.accesses 7746179 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1457,80 +1455,80 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 1343 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1343 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 245 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1098 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1343 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1343 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1343 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 890 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12592.696629 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 10799.035256 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6603.898577 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 278 31.24% 31.24% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 236 26.52% 57.75% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 167 18.76% 76.52% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 5 0.56% 77.08% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 204 22.92% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 890 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 2000056500 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 2000056500 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 2000056500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 648 72.81% 72.81% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 242 27.19% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 890 # Table walker page sizes translated +system.cpu2.itb.walker.walks 1328 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1328 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 246 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1082 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1328 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1328 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1328 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 881 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 12986.379115 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 11270.183591 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6464.618437 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 240 27.24% 27.24% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 238 27.01% 54.26% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 191 21.68% 75.94% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 6 0.68% 76.62% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 206 23.38% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 881 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 2000055500 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2000055500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 2000055500 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 640 72.64% 72.64% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 241 27.36% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 881 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1343 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1343 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1328 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1328 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 890 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 890 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2233 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10557278 # ITB inst hits -system.cpu2.itb.inst_misses 1343 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 881 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 881 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2209 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10575904 # ITB inst hits +system.cpu2.itb.inst_misses 1328 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 930 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 923 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1750 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1777 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10558621 # ITB inst accesses -system.cpu2.itb.hits 10557278 # DTB hits -system.cpu2.itb.misses 1343 # DTB misses -system.cpu2.itb.accesses 10558621 # DTB accesses -system.cpu2.numCycles 1381989702 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 10577232 # ITB inst accesses +system.cpu2.itb.hits 10575904 # DTB hits +system.cpu2.itb.misses 1328 # DTB misses +system.cpu2.itb.accesses 10577232 # DTB accesses +system.cpu2.numCycles 1381990575 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 19375420 # Number of instructions committed -system.cpu2.committedOps 23493929 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1397443 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.committedInsts 19415856 # Number of instructions committed +system.cpu2.committedOps 23538274 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1407481 # Number of ops (including micro ops) which were discarded before commit system.cpu2.numFetchSuspends 550 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 4259392331 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 71.326955 # CPI: cycles per instruction -system.cpu2.ipc 0.014020 # IPC: instructions per cycle +system.cpu2.quiesceCycles 4259391923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 71.178452 # CPI: cycles per instruction +system.cpu2.ipc 0.014049 # IPC: instructions per cycle system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 41311098 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 1340678604 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13646054 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7543734 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 320434 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8619119 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 6472050 # Number of BTB hits +system.cpu2.tickCycles 41337448 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 1340653127 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13659827 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7557018 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 321485 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 8617850 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 6480530 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 75.089461 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3094994 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 16257 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 75.198919 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3094736 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 16291 # Number of incorrect RAS predictions. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1560,85 +1558,88 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 35143 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 35143 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 12076 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7806 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 15261 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19882 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 462.453476 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 3227.731349 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-16383 19738 99.28% 99.28% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-32767 120 0.60% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-49151 15 0.08% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::49152-65535 2 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-81919 3 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walks 35471 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 35471 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11945 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7769 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 15757 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 19714 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 617.099523 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 4045.428418 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-16383 19501 98.92% 98.92% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-32767 152 0.77% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-49151 42 0.21% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::49152-65535 8 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-81919 7 0.04% 99.98% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::81920-98303 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::131072-147455 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19882 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6311 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 11174.694977 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 9013.738443 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 7509.952707 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-16383 5234 82.93% 82.93% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::16384-32767 989 15.67% 98.61% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-49151 83 1.32% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::49152-65535 2 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6311 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8699062064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.943227 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8742325064 100.50% 100.50% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 30532500 -0.35% 100.15% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 6165000 -0.07% 100.08% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 1932500 -0.02% 100.05% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1510500 -0.02% 100.04% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 932000 -0.01% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 478000 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 1202000 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 269000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 118500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 46500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 12000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 31500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 8000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-29 6000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 19000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8699062064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1800 71.51% 71.51% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 717 28.49% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2517 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 35143 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkWaitTime::total 19714 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6425 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 12552.451362 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 10392.470797 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 7297.231216 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-8191 1902 29.60% 29.60% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::8192-16383 3093 48.14% 77.74% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::16384-24575 1290 20.08% 97.82% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::24576-32767 56 0.87% 98.69% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-40959 42 0.65% 99.35% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::40960-49151 37 0.58% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::49152-57343 1 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::57344-65535 3 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::81920-90111 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 6425 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8701578064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 1.155310 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8749138564 100.55% 100.55% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 32608500 -0.37% 100.17% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 7394500 -0.08% 100.09% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 2262500 -0.03% 100.06% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1618000 -0.02% 100.04% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 1153500 -0.01% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 459000 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 1335500 -0.02% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 300000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 181000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 108000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 25500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 53500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 12000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-29 19000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::30-31 30000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8701578064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1781 71.41% 71.41% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 713 28.59% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2494 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 35471 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 35143 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2517 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 35471 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2494 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2517 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 37660 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2494 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 37965 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7578904 # DTB read hits -system.cpu3.dtb.read_misses 29166 # DTB read misses -system.cpu3.dtb.write_hits 5839969 # DTB write hits -system.cpu3.dtb.write_misses 5977 # DTB write misses +system.cpu3.dtb.read_hits 7577935 # DTB read hits +system.cpu3.dtb.read_misses 29413 # DTB read misses +system.cpu3.dtb.write_hits 5839655 # DTB write hits +system.cpu3.dtb.write_misses 6058 # DTB write misses system.cpu3.dtb.flush_tlb 158 # Number of times complete TLB was flushed -system.cpu3.dtb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA +system.cpu3.dtb.flush_tlb_mva 224 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1718 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 425 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 723 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 415 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 739 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 310 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7608070 # DTB read accesses -system.cpu3.dtb.write_accesses 5845946 # DTB write accesses +system.cpu3.dtb.perms_faults 327 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7607348 # DTB read accesses +system.cpu3.dtb.write_accesses 5845713 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 13418873 # DTB hits -system.cpu3.dtb.misses 35143 # DTB misses -system.cpu3.dtb.accesses 13454016 # DTB accesses +system.cpu3.dtb.hits 13417590 # DTB hits +system.cpu3.dtb.misses 35471 # DTB misses +system.cpu3.dtb.accesses 13453061 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1668,180 +1669,180 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 4732 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4732 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1951 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2718 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 63 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 4669 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1610.409081 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 7290.700462 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-16383 4501 96.40% 96.40% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-32767 127 2.72% 99.12% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-49151 19 0.41% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-65535 9 0.19% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-81919 6 0.13% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::81920-98303 3 0.06% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-114687 2 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walks 4217 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4217 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1465 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2667 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 85 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 4132 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1732.090997 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 7203.300582 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-16383 3973 96.15% 96.15% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-32767 122 2.95% 99.10% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-49151 16 0.39% 99.49% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-65535 12 0.29% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-81919 4 0.10% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::81920-98303 2 0.05% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-114687 1 0.02% 99.95% # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkWaitTime::114688-131071 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::147456-163839 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 4669 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 1251 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 12846.922462 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 10663.579337 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7853.199891 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-4095 16 1.28% 1.28% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::4096-8191 403 32.21% 33.49% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-12287 333 26.62% 60.11% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::12288-16383 200 15.99% 76.10% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-20479 15 1.20% 77.30% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::20480-24575 250 19.98% 97.28% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-28671 6 0.48% 97.76% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::28672-32767 4 0.32% 98.08% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-36863 2 0.16% 98.24% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::36864-40959 7 0.56% 98.80% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-45055 12 0.96% 99.76% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkWaitTime::131072-147455 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 4132 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 1265 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 13666.007905 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 11737.085754 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 7328.478477 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-4095 21 1.66% 1.66% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::4096-8191 283 22.37% 24.03% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-12287 342 27.04% 51.07% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::12288-16383 308 24.35% 75.42% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-20479 17 1.34% 76.76% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::20480-24575 261 20.63% 97.39% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-28671 6 0.47% 97.87% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::28672-32767 7 0.55% 98.42% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-36863 1 0.08% 98.50% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::36864-40959 7 0.55% 99.05% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-45055 9 0.71% 99.76% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::45056-49151 2 0.16% 99.92% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::57344-61439 1 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 1251 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -394920472 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean -1.156632 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -848106296 214.75% 214.75% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 450855824 -114.16% 100.59% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1608500 -0.41% 100.18% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 392000 -0.10% 100.08% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 207000 -0.05% 100.03% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 65000 -0.02% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::6 26500 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::7 31000 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -394920472 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 859 72.31% 72.31% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 329 27.69% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1188 # Table walker page sizes translated +system.cpu3.itb.walker.walkCompletionTime::total 1265 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -8974548064 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.863052 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.342327 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -1226005296 13.66% 13.66% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -7750612268 86.36% 100.02% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1421000 -0.02% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 452500 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 116500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 31500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::6 48000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -8974548064 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 850 72.03% 72.03% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 330 27.97% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1180 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4732 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4732 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4217 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4217 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1188 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1188 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5920 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9997642 # ITB inst hits -system.cpu3.itb.inst_misses 4732 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1180 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1180 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5397 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9998093 # ITB inst hits +system.cpu3.itb.inst_misses 4217 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses system.cpu3.itb.flush_tlb 158 # Number of times complete TLB was flushed -system.cpu3.itb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb_mva 224 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1217 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1209 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 676 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 709 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 10002374 # ITB inst accesses -system.cpu3.itb.hits 9997642 # DTB hits -system.cpu3.itb.misses 4732 # DTB misses -system.cpu3.itb.accesses 10002374 # DTB accesses -system.cpu3.numCycles 55587045 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 10002310 # ITB inst accesses +system.cpu3.itb.hits 9998093 # DTB hits +system.cpu3.itb.misses 4217 # DTB misses +system.cpu3.itb.accesses 10002310 # DTB accesses +system.cpu3.numCycles 55588609 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20927206 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 54552679 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13646054 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9567044 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 32032256 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1608040 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 79957 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 938 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 213 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 310222 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 78152 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 195 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9996683 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 215580 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2118 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 54233142 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.214742 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.347105 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 20911805 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 54608834 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13659827 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9575266 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 32188027 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1609304 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 73500 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 188 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 174621 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 79934 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 246 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9997086 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 214812 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2061 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 54233591 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.215961 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.348203 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 39601274 73.02% 73.02% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1868483 3.45% 76.47% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1208105 2.23% 78.69% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3698353 6.82% 85.51% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 956006 1.76% 87.28% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 647778 1.19% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2970918 5.48% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 646722 1.19% 95.14% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2635503 4.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 39592641 73.00% 73.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1866738 3.44% 76.45% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1209172 2.23% 78.68% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3694476 6.81% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 961111 1.77% 87.26% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 647261 1.19% 88.45% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2977203 5.49% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 646450 1.19% 95.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2638539 4.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 54233142 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.245490 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.981392 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14598894 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 29797113 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 8084772 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 1033348 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 718831 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 1078244 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 86337 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 47705679 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 276961 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 718831 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15136583 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3024863 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 21172664 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8572569 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 5607363 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 45758805 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 705 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1147656 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 110939 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 3950348 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 47566105 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 210305694 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 51528880 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 3583 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 39455162 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 8110943 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 731184 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 676901 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5765226 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 8100915 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 6455257 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1173886 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1646906 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 43984199 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 534989 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 41793570 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 55806 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6489424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 14897600 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 57980 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 54233142 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.770628 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.467625 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 54233591 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.245731 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.982375 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14602129 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 29778773 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 8106369 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 1026636 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 719503 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 1079419 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 86358 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 47749839 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 276699 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 719503 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15137242 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3025598 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 21153466 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8589840 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 5607720 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 45799280 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 610 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1145187 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 113658 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 3954911 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 47609045 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 210470711 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 51575848 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 3589 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 39452126 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 8156919 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 730493 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 676284 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5731608 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 8102362 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 6460033 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1172202 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1643889 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 44018542 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 534103 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 41806723 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 56092 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 6528844 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 14989618 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 58298 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 54233591 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.770864 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.468112 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 37814670 69.73% 69.73% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5400070 9.96% 79.68% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 4120767 7.60% 87.28% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3382476 6.24% 93.52% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1384183 2.55% 96.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 849283 1.57% 97.64% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 885452 1.63% 99.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 261249 0.48% 99.75% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 134992 0.25% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 37808852 69.71% 69.71% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5406123 9.97% 79.68% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 4124283 7.60% 87.29% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3378417 6.23% 93.52% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1383474 2.55% 96.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 844457 1.56% 97.63% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 890959 1.64% 99.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 261360 0.48% 99.75% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 135666 0.25% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 54233142 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 54233591 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 63553 10.11% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 64650 10.11% 10.11% # attempts to use FU when none available system.cpu3.iq.fu_full::IntMult 0 0.00% 10.11% # attempts to use FU when none available system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.11% # attempts to use FU when none available system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.11% # attempts to use FU when none available @@ -1870,131 +1871,131 @@ system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.11% # at system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.11% # attempts to use FU when none available system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.11% # attempts to use FU when none available system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 286976 45.65% 55.76% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 278158 44.24% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 286710 44.85% 54.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 287936 45.04% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 64 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 27814370 66.55% 66.55% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 30310 0.07% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.62% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2311 0.01% 66.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.63% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7807777 18.68% 85.31% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 6138736 14.69% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 27827699 66.56% 66.56% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 30281 0.07% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2306 0.01% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.64% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7806443 18.67% 85.31% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 6139930 14.69% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 41793570 # Type of FU issued -system.cpu3.iq.rate 0.751858 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 628687 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015043 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 138497118 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 51032224 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 40586618 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 7657 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 4185 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3350 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 42418091 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4102 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 178986 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 41806723 # Type of FU issued +system.cpu3.iq.rate 0.752074 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 639296 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015292 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 138534759 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 51105205 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 40599791 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 7666 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 4221 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3348 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 42441848 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4107 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 178912 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1277727 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1461 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 28401 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 648748 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1280236 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1538 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 28536 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 657537 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 106985 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 49122 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 107166 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 47571 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 718831 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 2574270 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 340639 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 44583748 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 79881 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 8100915 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 6455257 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 277620 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 23691 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 310856 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 28401 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 151779 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 129603 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 281382 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 41441394 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7665414 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 317113 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 719503 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 2584673 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 329572 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 44617850 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 80448 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 8102362 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 6460033 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 277261 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 23890 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 299738 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 28536 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 153085 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 129623 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 282708 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 41453550 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7664420 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 317790 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 64560 # number of nop insts executed -system.cpu3.iew.exec_refs 13741668 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7578657 # Number of branches executed -system.cpu3.iew.exec_stores 6076254 # Number of stores executed -system.cpu3.iew.exec_rate 0.745523 # Inst execution rate -system.cpu3.iew.wb_sent 41128495 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 40589968 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 21345679 # num instructions producing a value -system.cpu3.iew.wb_consumers 37833149 # num instructions consuming a value +system.cpu3.iew.exec_nop 65205 # number of nop insts executed +system.cpu3.iew.exec_refs 13740951 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7582733 # Number of branches executed +system.cpu3.iew.exec_stores 6076531 # Number of stores executed +system.cpu3.iew.exec_rate 0.745720 # Inst execution rate +system.cpu3.iew.wb_sent 41141473 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 40603139 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 21356385 # num instructions producing a value +system.cpu3.iew.wb_consumers 37848912 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 0.730206 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.564206 # average fanout of values written-back +system.cpu3.iew.wb_rate 0.730422 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.564254 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 6509597 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 477009 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 235228 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 52878842 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.719887 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.616953 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 6551591 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 475805 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 236318 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 52873966 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.719843 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.617254 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 38356720 72.54% 72.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6383323 12.07% 84.61% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3220180 6.09% 90.70% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1427186 2.70% 93.40% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 783029 1.48% 94.88% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 553691 1.05% 95.93% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 963741 1.82% 97.75% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 249255 0.47% 98.22% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 941717 1.78% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 38351228 72.53% 72.53% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6390419 12.09% 84.62% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3217103 6.08% 90.70% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1425073 2.70% 93.40% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 785450 1.49% 94.88% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 547204 1.03% 95.92% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 964459 1.82% 97.74% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 247730 0.47% 98.21% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 945300 1.79% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 52878842 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 31212680 # Number of instructions committed -system.cpu3.commit.committedOps 38066779 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 52873966 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 31209379 # Number of instructions committed +system.cpu3.commit.committedOps 38060928 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 12629697 # Number of memory references committed -system.cpu3.commit.loads 6823188 # Number of loads committed -system.cpu3.commit.membars 185407 # Number of memory barriers committed -system.cpu3.commit.branches 7131780 # Number of branches committed +system.cpu3.commit.refs 12624622 # Number of memory references committed +system.cpu3.commit.loads 6822126 # Number of loads committed +system.cpu3.commit.membars 184951 # Number of memory barriers committed +system.cpu3.commit.branches 7133186 # Number of branches committed system.cpu3.commit.fp_insts 3315 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 33217803 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1242593 # Number of function calls committed. +system.cpu3.commit.int_insts 33210326 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1242319 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 25405548 66.74% 66.74% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 29226 0.08% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 25404774 66.75% 66.75% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 29228 0.08% 66.82% # Class of committed instruction system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.82% # Class of committed instruction system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.82% # Class of committed instruction system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.82% # Class of committed instruction @@ -2018,35 +2019,35 @@ system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.82% # system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.82% # Class of committed instruction system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.82% # Class of committed instruction system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2308 0.01% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6823188 17.92% 84.75% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5806509 15.25% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2304 0.01% 66.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6822126 17.92% 84.75% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5802496 15.25% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 38066779 # Class of committed instruction -system.cpu3.commit.bw_lim_events 941717 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 90938636 # The number of ROB reads -system.cpu3.rob.rob_writes 90509785 # The number of ROB writes -system.cpu3.timesIdled 219189 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1353903 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5161759281 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 31175665 # Number of Instructions Simulated -system.cpu3.committedOps 38029764 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.783027 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.783027 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.560844 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.560844 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 45482682 # number of integer regfile reads -system.cpu3.int_regfile_writes 25425363 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14224 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12010 # number of floating regfile writes -system.cpu3.cc_regfile_reads 146149493 # number of cc regfile reads -system.cpu3.cc_regfile_writes 16057585 # number of cc regfile writes -system.cpu3.misc_regfile_reads 75089133 # number of misc regfile reads -system.cpu3.misc_regfile_writes 354942 # number of misc regfile writes +system.cpu3.commit.op_class_0::total 38060928 # Class of committed instruction +system.cpu3.commit.bw_lim_events 945300 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 90970787 # The number of ROB reads +system.cpu3.rob.rob_writes 90587481 # The number of ROB writes +system.cpu3.timesIdled 219785 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1355018 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5161755203 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 31172252 # Number of Instructions Simulated +system.cpu3.committedOps 38023801 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.783272 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.783272 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.560767 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.560767 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 45496208 # number of integer regfile reads +system.cpu3.int_regfile_writes 25431004 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14216 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12004 # number of floating regfile writes +system.cpu3.cc_regfile_reads 146184815 # number of cc regfile reads +system.cpu3.cc_regfile_writes 16067235 # number of cc regfile writes +system.cpu3.misc_regfile_reads 75058867 # number of misc regfile reads +system.cpu3.misc_regfile_writes 353976 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30152 # Transaction distribution system.iobus.trans_dist::ReadResp 30152 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution @@ -2101,7 +2102,7 @@ system.iobus.pkt_size_system.bridge.master::total 159093 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 23980000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 23971000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2117,31 +2118,31 @@ system.iobus.reqLayer19.occupancy 2000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 3354000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 3350000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 18876000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 18885000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 75000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 72450078 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 72461073 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 50566000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 50561000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.001831 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.001949 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 248566208509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.001831 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062614 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062614 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 248566131009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.001949 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062622 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062622 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2157,8 +2158,8 @@ system.iocache.overall_misses::realview.ide 220 # system.iocache.overall_misses::total 220 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 16046914 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 16046914 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1650207164 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1650207164 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 1649931159 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1649931159 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ide 16046914 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 16046914 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 16046914 # number of overall miss cycles @@ -2181,8 +2182,8 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 72940.518182 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 72940.518182 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 45555.630632 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 45555.630632 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 45548.011236 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 45548.011236 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 72940.518182 # average overall miss latency system.iocache.demand_avg_miss_latency::total 72940.518182 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 72940.518182 # average overall miss latency @@ -2207,8 +2208,8 @@ system.iocache.overall_mshr_misses::realview.ide 135 system.iocache.overall_mshr_misses::total 135 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 9296914 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 9296914 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 951007164 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 951007164 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 950731159 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 950731159 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 9296914 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 9296914 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 9296914 # number of overall MSHR miss cycles @@ -2223,392 +2224,390 @@ system.iocache.overall_mshr_miss_rate::realview.ide 0.613636 system.iocache.overall_mshr_miss_rate::total 0.613636 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68866.029630 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68866.029630 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68006.805206 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68006.805206 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67987.068006 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67987.068006 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 68866.029630 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 68866.029630 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 68866.029630 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 68866.029630 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 101303 # number of replacements -system.l2c.tags.tagsinuse 65108.070418 # Cycle average of tags in use -system.l2c.tags.total_refs 5168936 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166462 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 31.051748 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 79214811500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48981.200793 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.935125 # Average occupied blocks per requestor +system.l2c.tags.replacements 101236 # number of replacements +system.l2c.tags.tagsinuse 65107.326464 # Cycle average of tags in use +system.l2c.tags.total_refs 5169585 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 166405 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 31.066284 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 79214835000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 49083.542399 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902823 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4737.303132 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1924.234554 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 793.012275 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 757.975635 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 22.711590 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.006773 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2669.581018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 709.597353 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 49.846649 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2547.275002 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1913.390425 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.747394 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4686.027695 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1888.757570 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 762.533127 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 823.027459 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 21.612176 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.006778 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2605.585835 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 671.628280 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 48.673794 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2617.148912 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1895.879520 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.748955 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.072286 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.029361 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.012100 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011566 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000347 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.071503 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.028820 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.011635 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012558 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000330 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.040735 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.010828 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000761 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.038868 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.029196 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993470 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65109 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 50 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu2.inst 0.039758 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.010248 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000743 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.039935 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 922952500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 1130501000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2560012000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1161786500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2155550500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3.data 2565110000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5882447000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002335 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000827 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003013 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.001921 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.987730 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985447 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.966533 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.600716 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.523810 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.356320 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.533578 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.544975 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.318020 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.008966 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012238 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010246 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006731 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.035104 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.018815 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.032448 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016611 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008966 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.139701 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002335 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000827 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012238 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.214814 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003013 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010246 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.234582 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.040757 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008966 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.139701 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002335 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000827 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012238 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.214814 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003013 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010246 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.234582 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.040757 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74516.129032 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 73000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 76530.303030 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 75857.142857 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20754.658385 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20765.822785 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20772.160665 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20765.336510 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 30090.909091 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 30090.909091 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67798.468308 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66141.326378 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 71958.416824 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 69580.904416 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71681.649921 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 71534.040369 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72389.766607 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71913.203577 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72097.055164 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72303.592121 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 76645.689835 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74577.900986 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71681.649921 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68526.883610 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74516.129032 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 73000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 71534.040369 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66475.552274 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 76530.303030 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72389.766607 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72351.071828 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 70234.701838 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159889.702294 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 182363.959166 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 189888.682991 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180449.435151 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 158151.264440 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 178693.610842 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 188511.088878 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178211.764706 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 159127.037392 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 180774.111037 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 189279.073200 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 179468.743326 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 75574 # Transaction distribution +system.membus.trans_dist::ReadResp 75602 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::Writeback 129170 # Transaction distribution -system.membus.trans_dist::CleanEvict 8408 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4537 # Transaction distribution -system.membus.trans_dist::ReadExReq 135995 # Transaction distribution -system.membus.trans_dist::ReadExResp 135995 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35460 # Transaction distribution +system.membus.trans_dist::Writeback 128874 # Transaction distribution +system.membus.trans_dist::CleanEvict 8637 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4529 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4540 # Transaction distribution +system.membus.trans_dist::ReadExReq 135912 # Transaction distribution +system.membus.trans_dist::ReadExResp 135912 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 35488 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 480552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 588004 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 480381 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 587833 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109028 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109028 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 697032 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 696861 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16952892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17116017 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16930428 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17093553 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19437617 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19415153 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 336 # Total snoops (count) -system.membus.snoop_fanout::samples 417611 # Request fanout histogram +system.membus.snoop_fanout::samples 417491 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 417611 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 417491 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 417611 # Request fanout histogram -system.membus.reqLayer0.occupancy 56684000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 417491 # Request fanout histogram +system.membus.reqLayer0.occupancy 56695500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 698000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 701000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 502688198 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 501323202 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 664974257 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 664397755 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 25114094 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 25144064 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2923,53 +2922,53 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 112988 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2628707 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 112246 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2626935 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 762046 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2097370 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2799 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2817 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296581 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296581 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1978788 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 536947 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 762585 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2095941 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2795 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 21 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2816 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296569 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296569 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1977107 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 537598 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 13984 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5930770 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2618508 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27177 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 101121 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8677576 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126672504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97797817 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 44504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 177192 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224692017 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 129673 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5878617 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.031442 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.174509 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5926014 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2620361 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26770 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102262 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8675407 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126565496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97893497 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 45160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 182440 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224686593 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 127382 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5875721 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.031320 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.174182 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 5693781 96.86% 96.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 184836 3.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 5691691 96.87% 96.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 184030 3.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5878617 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2191894997 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5875721 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2190361997 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 178500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1851402273 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1848817301 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 767013811 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 767245312 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11591991 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11020987 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 48212755 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 48078267 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed |