diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini | 211 |
1 files changed, 206 insertions, 5 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 0865afb47..bd21d2c8f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -184,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -206,18 +218,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -226,15 +241,18 @@ port=system.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -243,16 +261,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -261,22 +282,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu0.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu0.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -285,22 +310,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu0.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu0.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -309,10 +338,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -321,124 +352,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu0.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu0.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu0.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu0.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu0.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu0.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu0.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu0.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu0.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu0.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu0.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu0.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu0.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu0.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu0.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu0.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu0.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -447,10 +499,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -459,16 +513,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu0.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -477,10 +534,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -491,6 +550,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -513,14 +573,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -539,18 +602,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=DerivO3CPU @@ -581,6 +647,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -643,6 +711,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -655,12 +724,14 @@ predType=tournament [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system @@ -668,15 +739,18 @@ sys=system type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -685,16 +759,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -703,22 +780,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu1.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu1.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -727,22 +808,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu1.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu1.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -751,10 +836,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -763,124 +850,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu1.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu1.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu1.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu1.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu1.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu1.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu1.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu1.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu1.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu1.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu1.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu1.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu1.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu1.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu1.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu1.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu1.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -889,10 +997,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -901,16 +1011,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu1.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -919,16 +1032,19 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -947,30 +1063,36 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -983,6 +1105,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1005,6 +1128,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1014,6 +1138,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1036,6 +1161,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1043,6 +1169,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1054,6 +1181,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1080,6 +1208,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1091,19 +1220,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -1113,6 +1246,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -1122,6 +1256,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -1150,6 +1285,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -1159,8 +1295,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1172,6 +1340,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -1187,6 +1356,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -1201,6 +1372,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -1210,6 +1382,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -1231,8 +1404,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1241,6 +1416,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -1251,6 +1427,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1261,6 +1438,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1271,6 +1449,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1285,6 +1464,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1298,6 +1478,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1315,6 +1496,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1327,6 +1509,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1338,6 +1521,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1348,6 +1532,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1360,6 +1545,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1373,6 +1559,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1383,6 +1570,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1393,6 +1581,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1403,6 +1592,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1415,6 +1605,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1429,6 +1620,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1441,6 +1633,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1455,6 +1648,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1465,6 +1659,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1475,6 +1670,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1485,6 +1681,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1493,6 +1690,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1501,6 +1699,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1510,11 +1709,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 |