diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | 3478 |
1 files changed, 1613 insertions, 1865 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 1944dbbec..ef9bf74a4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.550456 # Number of seconds simulated -sim_ticks 2550455693500 # Number of ticks simulated -final_tick 2550455693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.550648 # Number of seconds simulated +sim_ticks 2550647964000 # Number of ticks simulated +final_tick 2550647964000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59744 # Simulator instruction rate (inst/s) -host_op_rate 76873 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2526372396 # Simulator tick rate (ticks/s) -host_mem_usage 427472 # Number of bytes of host memory used -host_seconds 1009.53 # Real time elapsed on the host -sim_insts 60313472 # Number of instructions simulated -sim_ops 77606209 # Number of ops (including micro ops) simulated +host_inst_rate 57676 # Simulator instruction rate (inst/s) +host_op_rate 74213 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2439007396 # Simulator tick rate (ticks/s) +host_mem_usage 470664 # Number of bytes of host memory used +host_seconds 1045.77 # Real time elapsed on the host +sim_insts 60315890 # Number of instructions simulated +sim_ops 77609880 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory @@ -26,142 +26,142 @@ system.realview.nvmem.bw_inst_read::total 25 # I system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 504320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5079000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 295488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4015064 # Number of bytes read from this memory -system.physmem.bytes_read::total 131007536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 504320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 295488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786368 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1520720 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1495380 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802468 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 483008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5043284 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 315584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4051356 # Number of bytes read from this memory +system.physmem.bytes_read::total 131006576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 483008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 315584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785856 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521376 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494724 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801956 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7880 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 79395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4617 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 62741 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293498 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59162 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380180 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373845 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813187 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47485839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 853 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7547 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 78836 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 63309 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293483 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59154 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380344 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373681 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813179 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47482259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 803 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 197737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1991409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 115857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1574254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51366325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 197737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 115857 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484585 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596254 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586319 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2667158 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47485839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 189367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1977256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 123727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1588363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51362077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 189367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 123727 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313094 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596466 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586017 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2666756 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47482259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 803 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 197737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2587663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 115857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2160572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54033483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293498 # Number of read requests accepted -system.physmem.writeReqs 813187 # Number of write requests accepted -system.physmem.readBursts 15293498 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813187 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978241024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 542848 # Total number of bytes read from write queue -system.physmem.bytesWritten 6911808 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131007536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6802468 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8482 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705190 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955869 # Per bank write bursts -system.physmem.perBankRdBursts::1 955539 # Per bank write bursts -system.physmem.perBankRdBursts::2 954667 # Per bank write bursts -system.physmem.perBankRdBursts::3 954789 # Per bank write bursts -system.physmem.perBankRdBursts::4 955759 # Per bank write bursts -system.physmem.perBankRdBursts::5 955951 # Per bank write bursts -system.physmem.perBankRdBursts::6 954859 # Per bank write bursts -system.physmem.perBankRdBursts::7 954668 # Per bank write bursts -system.physmem.perBankRdBursts::8 956272 # Per bank write bursts -system.physmem.perBankRdBursts::9 955769 # Per bank write bursts -system.physmem.perBankRdBursts::10 954516 # Per bank write bursts -system.physmem.perBankRdBursts::11 954114 # Per bank write bursts -system.physmem.perBankRdBursts::12 956222 # Per bank write bursts -system.physmem.perBankRdBursts::13 955973 # Per bank write bursts -system.physmem.perBankRdBursts::14 955087 # Per bank write bursts -system.physmem.perBankRdBursts::15 954962 # Per bank write bursts -system.physmem.perBankWrBursts::0 6687 # Per bank write bursts -system.physmem.perBankWrBursts::1 6466 # Per bank write bursts -system.physmem.perBankWrBursts::2 6605 # Per bank write bursts -system.physmem.perBankWrBursts::3 6628 # Per bank write bursts -system.physmem.perBankWrBursts::4 6579 # Per bank write bursts -system.physmem.perBankWrBursts::5 6834 # Per bank write bursts -system.physmem.perBankWrBursts::6 6823 # Per bank write bursts -system.physmem.perBankWrBursts::7 6763 # Per bank write bursts -system.physmem.perBankWrBursts::8 7134 # Per bank write bursts -system.physmem.perBankWrBursts::9 6882 # Per bank write bursts -system.physmem.perBankWrBursts::10 6543 # Per bank write bursts -system.physmem.perBankWrBursts::11 6191 # Per bank write bursts -system.physmem.perBankWrBursts::12 7147 # Per bank write bursts -system.physmem.perBankWrBursts::13 6760 # Per bank write bursts -system.physmem.perBankWrBursts::14 7044 # Per bank write bursts -system.physmem.perBankWrBursts::15 6911 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 189367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2573722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 123727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2174381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54028833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293483 # Number of read requests accepted +system.physmem.writeReqs 813179 # Number of write requests accepted +system.physmem.readBursts 15293483 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813179 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 976671488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2111424 # Total number of bytes read from write queue +system.physmem.bytesWritten 6834624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131006576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801956 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 32991 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706366 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4694 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955809 # Per bank write bursts +system.physmem.perBankRdBursts::1 953120 # Per bank write bursts +system.physmem.perBankRdBursts::2 953063 # Per bank write bursts +system.physmem.perBankRdBursts::3 953290 # Per bank write bursts +system.physmem.perBankRdBursts::4 955524 # Per bank write bursts +system.physmem.perBankRdBursts::5 952811 # Per bank write bursts +system.physmem.perBankRdBursts::6 952747 # Per bank write bursts +system.physmem.perBankRdBursts::7 952554 # Per bank write bursts +system.physmem.perBankRdBursts::8 956154 # Per bank write bursts +system.physmem.perBankRdBursts::9 953015 # Per bank write bursts +system.physmem.perBankRdBursts::10 952848 # Per bank write bursts +system.physmem.perBankRdBursts::11 952579 # Per bank write bursts +system.physmem.perBankRdBursts::12 956184 # Per bank write bursts +system.physmem.perBankRdBursts::13 953741 # Per bank write bursts +system.physmem.perBankRdBursts::14 953594 # Per bank write bursts +system.physmem.perBankRdBursts::15 953459 # Per bank write bursts +system.physmem.perBankWrBursts::0 6616 # Per bank write bursts +system.physmem.perBankWrBursts::1 6407 # Per bank write bursts +system.physmem.perBankWrBursts::2 6542 # Per bank write bursts +system.physmem.perBankWrBursts::3 6564 # Per bank write bursts +system.physmem.perBankWrBursts::4 6491 # Per bank write bursts +system.physmem.perBankWrBursts::5 6761 # Per bank write bursts +system.physmem.perBankWrBursts::6 6753 # Per bank write bursts +system.physmem.perBankWrBursts::7 6706 # Per bank write bursts +system.physmem.perBankWrBursts::8 7029 # Per bank write bursts +system.physmem.perBankWrBursts::9 6806 # Per bank write bursts +system.physmem.perBankWrBursts::10 6476 # Per bank write bursts +system.physmem.perBankWrBursts::11 6118 # Per bank write bursts +system.physmem.perBankWrBursts::12 7056 # Per bank write bursts +system.physmem.perBankWrBursts::13 6677 # Per bank write bursts +system.physmem.perBankWrBursts::14 6959 # Per bank write bursts +system.physmem.perBankWrBursts::15 6830 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2550454486000 # Total gap between requests +system.physmem.totGap 2550646795500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 44 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154638 # Read request sizes (log2) +system.physmem.readPktSize::6 154623 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754025 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59162 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1173632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1113468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1067801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3688063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2661485 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2656312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2669345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 52900 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59154 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1055042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 994364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 947765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 947544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 945397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 945218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2783572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2783267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3699218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 24042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 23218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 23233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 22770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 22263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21886 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 21619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -173,717 +173,457 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11341.188281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1014.168764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16824.493217 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23628 27.20% 27.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14156 16.30% 43.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2700 3.11% 46.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2166 2.49% 49.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1318 1.52% 50.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1170 1.35% 51.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 896 1.03% 52.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 913 1.05% 54.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 566 0.65% 54.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 606 0.70% 55.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 521 0.60% 55.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 631 0.73% 56.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 271 0.31% 57.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 267 0.31% 57.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 154 0.18% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 590 0.68% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 110 0.13% 58.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 147 0.17% 58.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 73 0.08% 58.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 151 0.17% 58.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 55 0.06% 58.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 532 0.61% 59.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 32 0.04% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 226 0.26% 59.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 18 0.02% 59.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 114 0.13% 59.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 25 0.03% 59.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 112 0.13% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 26 0.03% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 51 0.06% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 19 0.02% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 424 0.49% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 10 0.01% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 29 0.03% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 12 0.01% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 47 0.05% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 15 0.02% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 23 0.03% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 12 0.01% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 153 0.18% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 13 0.01% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 8 0.01% 61.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 30 0.03% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 14 0.02% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 22 0.03% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 8 0.01% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 344 0.40% 61.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 8 0.01% 61.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 12 0.01% 61.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 150 0.17% 61.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 12 0.01% 61.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 8 0.01% 61.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 14 0.02% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 136 0.16% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 11 0.01% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 13 0.01% 61.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 10 0.01% 61.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 83 0.10% 62.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 12 0.01% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 470 0.54% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 7 0.01% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 13 0.01% 62.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 83 0.10% 62.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 13 0.01% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 10 0.01% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 11 0.01% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 20 0.02% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 11 0.01% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 7 0.01% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 8 0.01% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 151 0.17% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 7 0.01% 63.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 10 0.01% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 397 0.46% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 3 0.00% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 13 0.01% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 7 0.01% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 18 0.02% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 13 0.01% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 9 0.01% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 10 0.01% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 76 0.09% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 6 0.01% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 11 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 5 0.01% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 208 0.24% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 5 0.01% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 13 0.01% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 7 0.01% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 368 0.42% 64.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 3 0.00% 64.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 4 0.00% 64.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 73 0.08% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 2 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 7 0.01% 64.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 137 0.16% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 10 0.01% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 24 0.03% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 2 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 60 0.07% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 5 0.01% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 5 0.01% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 7 0.01% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 270 0.31% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 5 0.01% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 10 0.01% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 9 0.01% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 215 0.25% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 8 0.01% 65.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 21 0.02% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 7 0.01% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 8 0.01% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 2 0.00% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 69 0.08% 65.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 4 0.00% 65.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 6 0.01% 65.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 602 0.69% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8391 1 0.00% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 67 0.08% 66.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 2 0.00% 66.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 203 0.23% 66.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 262 0.30% 66.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9287 1 0.00% 66.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 56 0.06% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 129 0.15% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 65 0.07% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 354 0.41% 67.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 1 0.00% 67.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 132 0.15% 67.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 66 0.08% 67.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 2 0.00% 67.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 377 0.43% 68.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 143 0.16% 68.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 1 0.00% 68.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 65 0.07% 68.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 444 0.51% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 65 0.07% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 1 0.00% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 120 0.14% 69.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 129 0.15% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 321 0.37% 69.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 4 0.00% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 137 0.16% 69.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 1 0.00% 69.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 5 0.01% 69.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14151 1 0.00% 69.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 1 0.00% 69.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 386 0.44% 70.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 64 0.07% 70.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 71 0.08% 70.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 56 0.06% 70.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 1 0.00% 70.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 386 0.44% 70.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 121 0.14% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 5 0.01% 71.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 125 0.14% 71.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 641 0.74% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16455 1 0.00% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16519 1 0.00% 72.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 125 0.14% 72.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 7 0.01% 72.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 120 0.14% 72.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17223 1 0.00% 72.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 386 0.44% 72.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 54 0.06% 72.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 71 0.08% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17991 1 0.00% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 1 0.00% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 65 0.07% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18375 1 0.00% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 384 0.44% 73.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 5 0.01% 73.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 132 0.15% 73.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 6 0.01% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 1 0.00% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 322 0.37% 73.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 129 0.15% 74.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 120 0.14% 74.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 65 0.07% 74.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 442 0.51% 74.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 64 0.07% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 1 0.00% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21120-21127 1 0.00% 74.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 144 0.17% 75.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 377 0.43% 75.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 65 0.07% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 131 0.15% 75.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 354 0.41% 76.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 66 0.08% 76.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 128 0.15% 76.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 55 0.06% 76.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 261 0.30% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23616-23623 1 0.00% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 203 0.23% 76.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 2 0.00% 76.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24256-24263 1 0.00% 76.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 67 0.08% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24512-24519 1 0.00% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 495 0.57% 77.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 66 0.08% 77.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 2 0.00% 77.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 204 0.23% 77.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 262 0.30% 78.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 56 0.06% 78.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 129 0.15% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 67 0.08% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 355 0.41% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26752-26759 1 0.00% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 131 0.15% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26944-26951 1 0.00% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27072-27079 1 0.00% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 64 0.07% 79.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27328-27335 2 0.00% 79.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 3 0.00% 79.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 1 0.00% 79.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 377 0.43% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 143 0.16% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 65 0.07% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 441 0.51% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 65 0.07% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 119 0.14% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 128 0.15% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 321 0.37% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 6 0.01% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 134 0.15% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 4 0.00% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 385 0.44% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 66 0.08% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 71 0.08% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31296-31303 2 0.00% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 54 0.06% 81.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 385 0.44% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 120 0.14% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 4 0.00% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 124 0.14% 82.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 640 0.74% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 124 0.14% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 4 0.00% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 121 0.14% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 386 0.44% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 54 0.06% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 71 0.08% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 66 0.08% 84.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 384 0.44% 84.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35008-35015 1 0.00% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 4 0.00% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 134 0.15% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 5 0.01% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35776-35783 1 0.00% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 321 0.37% 85.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 128 0.15% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 120 0.14% 85.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 65 0.07% 85.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 441 0.51% 86.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 64 0.07% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 1 0.00% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 143 0.16% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37760-37767 1 0.00% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37824-37831 1 0.00% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 377 0.43% 86.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 1 0.00% 86.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38208-38215 1 0.00% 86.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 64 0.07% 86.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38464-38471 1 0.00% 86.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 130 0.15% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 355 0.41% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 66 0.08% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 128 0.15% 87.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 55 0.06% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 261 0.30% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40007 1 0.00% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 203 0.23% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 1 0.00% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 66 0.08% 88.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 496 0.57% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 67 0.08% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41280-41287 1 0.00% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 2 0.00% 89.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 203 0.23% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41920-41927 1 0.00% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 260 0.30% 89.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 55 0.06% 89.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42304-42311 1 0.00% 89.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 128 0.15% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 67 0.08% 89.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42880-42887 1 0.00% 89.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 353 0.41% 90.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 131 0.15% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 65 0.07% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 379 0.44% 90.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 143 0.16% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44416-44423 2 0.00% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 67 0.08% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 443 0.51% 91.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 67 0.08% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 122 0.14% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 1 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 130 0.15% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46016-46023 1 0.00% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 322 0.37% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 4 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 131 0.15% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 5 0.01% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 384 0.44% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 64 0.07% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 72 0.08% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 54 0.06% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 385 0.44% 93.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 121 0.14% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48576-48583 1 0.00% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 5 0.01% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48832-48839 1 0.00% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 123 0.14% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 2 0.00% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5211 6.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49536-49543 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50112-50119 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51648-51655 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51719 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86865 # Bytes accessed per row activation -system.physmem.totQLat 369784547000 # Total ticks spent queuing -system.physmem.totMemAccLat 463560559500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76425080000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17350932500 # Total ticks spent accessing banks -system.physmem.avgQLat 24192.62 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1135.16 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 965273 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1013.486813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 999.850047 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 92.541667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 4202 0.44% 0.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 3517 0.36% 0.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1855 0.19% 0.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1291 0.13% 1.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 949 0.10% 1.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 717 0.07% 1.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 589 0.06% 1.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 765 0.08% 1.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 951388 98.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 965273 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5001 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3051.486103 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 52637.524815 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 4974 99.46% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.48% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 8 0.16% 99.64% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 6 0.12% 99.76% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 2 0.04% 99.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.84% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.14% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5001 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5001 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.353929 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.695200 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.701170 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 8 0.16% 0.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 2 0.04% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 3 0.06% 0.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.02% 0.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 8 0.16% 0.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 1 0.02% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 1 0.02% 0.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 3 0.06% 0.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 5 0.10% 0.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 2 0.04% 0.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 5 0.10% 0.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 2 0.04% 0.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 1 0.02% 0.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 1 0.02% 0.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 10 0.20% 1.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2816 56.31% 57.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 26 0.52% 57.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 135 2.70% 60.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 879 17.58% 78.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 49 0.98% 79.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 23 0.46% 79.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.30% 79.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 25 0.50% 80.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 14 0.28% 80.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 18 0.36% 81.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.14% 81.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 15 0.30% 81.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 16 0.32% 81.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 18 0.36% 82.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 15 0.30% 82.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 8 0.16% 82.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 16 0.32% 82.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 10 0.20% 83.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.02% 83.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.02% 83.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 3 0.06% 83.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 243 4.86% 88.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 480 9.60% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 27 0.54% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 20 0.40% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 27 0.54% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 21 0.42% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 16 0.32% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5001 # Writes before turning the bus around for reads +system.physmem.totQLat 577566851750 # Total ticks spent queuing +system.physmem.totMemAccLat 682115428000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76302460000 # Total ticks spent in databus transfers +system.physmem.totBankLat 28246116250 # Total ticks spent accessing banks +system.physmem.avgQLat 37847.20 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1850.93 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30327.78 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44698.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 382.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.02 # Data bus utilization in percentage -system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.01 # Data bus utilization in percentage +system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing -system.physmem.readRowHits 15213014 # Number of row buffer hits during reads -system.physmem.writeRowHits 93134 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.24 # Row buffer hit rate for writes -system.physmem.avgGap 158347.57 # Average gap between requests -system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.65 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54973753 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346163 # Transaction distribution -system.membus.trans_dist::ReadResp 16346166 # Transaction distribution +system.physmem.avgRdQLen 6.73 # Average read queue length when enqueuing +system.physmem.avgWrQLen 15.38 # Average write queue length when enqueuing +system.physmem.readRowHits 14274135 # Number of row buffer hits during reads +system.physmem.writeRowHits 91331 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.51 # Row buffer hit rate for writes +system.physmem.avgGap 158359.74 # Average gap between requests +system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.60 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 54969038 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346130 # Transaction distribution +system.membus.trans_dist::ReadResp 16346133 # Transaction distribution system.membus.trans_dist::WriteReq 763365 # Transaction distribution system.membus.trans_dist::WriteResp 763365 # Transaction distribution -system.membus.trans_dist::Writeback 59162 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4696 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution -system.membus.trans_dist::ReadExReq 131412 # Transaction distribution -system.membus.trans_dist::ReadExResp 131412 # Transaction distribution +system.membus.trans_dist::Writeback 59154 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4694 # Transaction distribution +system.membus.trans_dist::ReadExReq 131434 # Transaction distribution +system.membus.trans_dist::ReadExResp 131434 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383052 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383060 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885968 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885926 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550446 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390470 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550412 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390486 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16699476 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19097594 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16698004 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19096138 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140208122 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140208122 # Total data (bytes) +system.membus.tot_pkt_size::total 140206666 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140206666 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487391000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487459000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3584500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3645000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17566049500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17565357500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4736056592 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4737629056 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34187486731 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.membus.respLayer2.occupancy 37816335199 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64408 # number of replacements -system.l2c.tags.tagsinuse 51449.796153 # Cycle average of tags in use -system.l2c.tags.total_refs 1905827 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129798 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.683023 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2540137710500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36969.006628 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 22.725284 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4879.693838 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3326.753767 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.863300 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3332.963946 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2906.789020 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564102 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000347 # Average percentage of cache occupancy +system.l2c.tags.replacements 64394 # number of replacements +system.l2c.tags.tagsinuse 51423.269942 # Cycle average of tags in use +system.l2c.tags.total_refs 1904392 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129782 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.673776 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2513283956500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36971.606132 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 22.825180 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000372 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4577.267389 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3052.603978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.951997 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3614.635006 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3176.379887 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564142 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000348 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074458 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050762 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000181 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.050857 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044354 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.785062 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65368 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.069844 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046579 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.055155 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.048468 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784657 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 21 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65367 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3071 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6835 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55083 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997437 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18939251 # Number of tag accesses -system.l2c.tags.data_accesses 18939251 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 33125 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6695 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 507433 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 188763 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 31491 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7375 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 463939 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198427 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1437248 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 607832 # number of Writeback hits -system.l2c.Writeback_hits::total 607832 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 21 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 20 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 41 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60764 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52147 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112911 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 33125 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6695 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 507433 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 249527 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 31491 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7375 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 463939 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 250574 # number of demand (read+write) hits -system.l2c.demand_hits::total 1550159 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 33125 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6695 # number of overall hits -system.l2c.overall_hits::cpu0.inst 507433 # number of overall hits -system.l2c.overall_hits::cpu0.data 249527 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 31491 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7375 # number of overall hits -system.l2c.overall_hits::cpu1.inst 463939 # number of overall hits -system.l2c.overall_hits::cpu1.data 250574 # number of overall hits -system.l2c.overall_hits::total 1550159 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 34 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1024::2 3070 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6838 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55080 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000320 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997421 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18929537 # Number of tag accesses +system.l2c.tags.data_accesses 18929537 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 32378 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6463 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 508619 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 187861 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 31368 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7240 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 462078 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 199585 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435592 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608227 # number of Writeback hits +system.l2c.Writeback_hits::total 608227 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 20 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 19 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 39 # 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average ReadReq mshr uncacheable latency @@ -1066,49 +814,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58427801 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2677013 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2677015 # Transaction distribution +system.toL2Bus.throughput 58424320 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2676714 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2676716 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 607832 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2952 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2962 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246108 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246108 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608227 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2954 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246181 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246181 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968942 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796822 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 150646 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7954400 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62968576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85534266 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 56288 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 258652 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148817782 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148817782 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 199736 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4962135725 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967568 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5797861 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37552 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149979 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7952960 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62924224 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85579658 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 54820 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 255152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148813854 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148813854 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 206020 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4963822946 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4435783766 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4432706696 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4484209498 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4484503287 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23967895 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23902881 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86426354 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86618127 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48423111 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322165 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322165 # Transaction distribution +system.iobus.throughput 48419467 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322169 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322169 # Transaction distribution system.iobus.trans_dist::WriteReq 8177 # Transaction distribution system.iobus.trans_dist::WriteResp 8177 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7932 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1130,12 +878,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383060 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660692 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15864 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1157,14 +905,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390470 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390486 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500998 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500998 # Total data (bytes) +system.iobus.tot_pkt_size::total 123501014 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123501014 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3971000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1210,19 +958,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374875000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374883000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41493951269 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7524637 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6008547 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 377377 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4829480 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3929632 # Number of BTB hits +system.iobus.respLayer1.occupancy 37825687801 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.cpu0.branchPred.lookups 7508483 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5992866 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 375676 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4822577 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3918936 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.367601 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 723615 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39097 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.262279 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 722501 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39246 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1246,25 +994,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25732063 # DTB read hits -system.cpu0.dtb.read_misses 40060 # DTB read misses -system.cpu0.dtb.write_hits 6173955 # DTB write hits -system.cpu0.dtb.write_misses 10391 # DTB write misses +system.cpu0.dtb.read_hits 25709068 # DTB read hits +system.cpu0.dtb.read_misses 39624 # DTB read misses +system.cpu0.dtb.write_hits 6152335 # DTB write hits +system.cpu0.dtb.write_misses 10221 # DTB write misses system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5654 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1384 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 265 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 760 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5608 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1406 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 264 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 665 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25772123 # DTB read accesses -system.cpu0.dtb.write_accesses 6184346 # DTB write accesses +system.cpu0.dtb.perms_faults 646 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25748692 # DTB read accesses +system.cpu0.dtb.write_accesses 6162556 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31906018 # DTB hits -system.cpu0.dtb.misses 50451 # DTB misses -system.cpu0.dtb.accesses 31956469 # DTB accesses +system.cpu0.dtb.hits 31861403 # DTB hits +system.cpu0.dtb.misses 49845 # DTB misses +system.cpu0.dtb.accesses 31911248 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1286,664 +1034,664 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5897367 # ITB inst hits -system.cpu0.itb.inst_misses 7084 # ITB inst misses +system.cpu0.itb.inst_hits 5876098 # ITB inst hits +system.cpu0.itb.inst_misses 7014 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2660 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 760 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2644 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1482 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1469 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5904451 # ITB inst accesses -system.cpu0.itb.hits 5897367 # DTB hits -system.cpu0.itb.misses 7084 # DTB misses -system.cpu0.itb.accesses 5904451 # DTB accesses -system.cpu0.numCycles 242280954 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5883112 # ITB inst accesses +system.cpu0.itb.hits 5876098 # DTB hits +system.cpu0.itb.misses 7014 # DTB misses +system.cpu0.itb.accesses 5883112 # DTB accesses +system.cpu0.numCycles 242192321 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15560897 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45618983 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7524637 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4653247 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10311307 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2438027 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 82681 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 50295736 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2004 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 47904 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1479659 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 328 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5895435 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 368728 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2960 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 79463748 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.723138 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.071375 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15567613 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45445847 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7508483 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4641437 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10272972 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2435180 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 81106 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 50250706 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1544 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1986 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 48114 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1489776 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 378 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5874191 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 367063 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2900 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 79394723 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.721041 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.068559 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 69159455 87.03% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 678650 0.85% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 874708 1.10% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1176149 1.48% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1117399 1.41% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 558232 0.70% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1283192 1.61% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 380865 0.48% 94.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4235098 5.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 69128739 87.07% 87.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 676261 0.85% 87.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 870795 1.10% 89.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1169302 1.47% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1115285 1.40% 91.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 553948 0.70% 92.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1287197 1.62% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 378519 0.48% 94.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4214677 5.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79463748 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031057 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.188290 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16659746 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 51317609 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9233971 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 657554 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1592691 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1005769 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91409 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 54704033 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 304298 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1592691 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17554490 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20340792 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27693159 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8932278 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3348216 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 52126479 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 377 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 497478 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2175969 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 155 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 53794326 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 241736924 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 220533984 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5031 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39400219 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14394106 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 593139 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 541531 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6973197 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10037020 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 7000202 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1050357 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1288163 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 48430994 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1028168 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62176930 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 89712 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9957065 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24599714 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 276838 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 79463748 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.782457 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.501316 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 79394723 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031002 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.187644 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16658432 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 51288095 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9197431 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 656874 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1591763 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1006093 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91406 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 54494283 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 303520 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1591763 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17551658 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20345183 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27653568 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8896202 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3354292 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 51932303 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 196 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 500448 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2179621 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 261 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 53595851 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 240832893 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 219678051 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5082 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39195467 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14400384 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 591696 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 540219 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6961736 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10014185 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6974197 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1050889 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1353332 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 48232956 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1025841 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 61971057 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 88766 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9957722 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24611703 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 275811 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 79394723 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.780544 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.499047 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 56925517 71.64% 71.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7350450 9.25% 80.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3522799 4.43% 85.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2913274 3.67% 88.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6168473 7.76% 96.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1495817 1.88% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 789992 0.99% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 231277 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 66149 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 56910995 71.68% 71.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7345017 9.25% 80.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3503110 4.41% 85.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2918035 3.68% 89.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6157997 7.76% 96.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1482939 1.87% 98.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 783446 0.99% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 227116 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 66068 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 79463748 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 79394723 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 30568 0.69% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4194749 94.30% 94.98% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 223174 5.02% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29670 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4193006 94.32% 94.99% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 222912 5.01% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 15922 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29222200 47.00% 47.02% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47810 0.08% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1242 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26409099 42.47% 89.58% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6480639 10.42% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 15869 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29065604 46.90% 46.93% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46869 0.08% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1239 0.00% 47.01% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.01% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.01% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.01% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26385475 42.58% 89.58% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6455974 10.42% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62176930 # Type of FU issued -system.cpu0.iq.rate 0.256632 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4448493 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.071546 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208394864 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59425365 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43388237 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11204 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6101 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5139 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66603600 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5901 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 313863 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 61971057 # Type of FU issued +system.cpu0.iq.rate 0.255875 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4445589 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.071737 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 207909567 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59225484 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43186225 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11292 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6130 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5133 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66394829 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5948 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 311727 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2132926 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3897 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15826 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 851086 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2130667 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3740 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15655 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 850179 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17067174 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 347980 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17067257 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348827 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1592691 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15703960 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 239689 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 49567887 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107700 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10037020 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 7000202 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 730031 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 54998 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4795 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15826 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 184371 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 145167 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 329538 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61108768 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26079506 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1068162 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1591763 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15715155 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 239745 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 49373573 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105603 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10014185 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6974197 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 727713 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 55741 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4727 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15655 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 183161 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 144870 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 328031 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 60906320 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26058550 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1064737 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 108725 # number of nop insts executed -system.cpu0.iew.exec_refs 32501673 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5985971 # Number of branches executed -system.cpu0.iew.exec_stores 6422167 # Number of stores executed -system.cpu0.iew.exec_rate 0.252223 # Inst execution rate -system.cpu0.iew.wb_sent 60615706 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43393376 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23422073 # num instructions producing a value -system.cpu0.iew.wb_consumers 43067972 # num instructions consuming a value +system.cpu0.iew.exec_nop 114776 # number of nop insts executed +system.cpu0.iew.exec_refs 32455686 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5967734 # Number of branches executed +system.cpu0.iew.exec_stores 6397136 # Number of stores executed +system.cpu0.iew.exec_rate 0.251479 # Inst execution rate +system.cpu0.iew.wb_sent 60414213 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43191358 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23287316 # num instructions producing a value +system.cpu0.iew.wb_consumers 42834885 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.179104 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.543840 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.178335 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.543653 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9785974 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 751330 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 287324 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 77871057 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.504327 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.472133 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9785836 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 750030 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 285660 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 77802960 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.502286 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.465598 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 63445664 81.48% 81.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7408180 9.51% 90.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1965702 2.52% 93.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1101219 1.41% 94.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 850042 1.09% 96.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 579839 0.74% 96.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 741280 0.95% 97.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 350840 0.45% 98.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1428291 1.83% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 63388396 81.47% 81.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7400911 9.51% 90.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1988257 2.56% 93.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1098992 1.41% 94.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 865715 1.11% 96.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 575312 0.74% 96.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 733525 0.94% 97.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 350428 0.45% 98.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1401424 1.80% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 77871057 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30068673 # Number of instructions committed -system.cpu0.commit.committedOps 39272492 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 77802960 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29900744 # Number of instructions committed +system.cpu0.commit.committedOps 39079359 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14053210 # Number of memory references committed -system.cpu0.commit.loads 7904094 # Number of loads committed -system.cpu0.commit.membars 209520 # Number of memory barriers committed -system.cpu0.commit.branches 5180571 # Number of branches committed -system.cpu0.commit.fp_insts 5103 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34976585 # Number of committed integer instructions. -system.cpu0.commit.function_calls 508087 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1428291 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14007536 # Number of memory references committed +system.cpu0.commit.loads 7883518 # Number of loads committed +system.cpu0.commit.membars 209346 # Number of memory barriers committed +system.cpu0.commit.branches 5162239 # Number of branches committed +system.cpu0.commit.fp_insts 5086 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34792812 # Number of committed integer instructions. +system.cpu0.commit.function_calls 507721 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1401424 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124525442 # The number of ROB reads -system.cpu0.rob.rob_writes 99752707 # The number of ROB writes -system.cpu0.timesIdled 907289 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 162817206 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2250738250 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29995072 # Number of Instructions Simulated -system.cpu0.committedOps 39198891 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29995072 # Number of Instructions Simulated -system.cpu0.cpi 8.077359 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.077359 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.123803 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.123803 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 277602258 # number of integer regfile reads -system.cpu0.int_regfile_writes 44085175 # number of integer regfile writes -system.cpu0.fp_regfile_reads 44877 # number of floating regfile reads -system.cpu0.fp_regfile_writes 42488 # number of floating regfile writes -system.cpu0.misc_regfile_reads 138395505 # number of misc regfile reads -system.cpu0.misc_regfile_writes 582325 # number of misc regfile writes -system.cpu0.icache.tags.replacements 984398 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.534546 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10515921 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984910 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.677037 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7008829000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 316.868268 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 194.666278 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.618883 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.380208 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999091 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 124291086 # The number of ROB reads +system.cpu0.rob.rob_writes 99365166 # The number of ROB writes +system.cpu0.timesIdled 908697 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 162797598 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2248209209 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 29823122 # Number of Instructions Simulated +system.cpu0.committedOps 39001737 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 29823122 # Number of Instructions Simulated +system.cpu0.cpi 8.120958 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.120958 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.123138 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.123138 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 276680521 # number of integer regfile reads +system.cpu0.int_regfile_writes 43875243 # number of integer regfile writes +system.cpu0.fp_regfile_reads 44965 # number of floating regfile reads +system.cpu0.fp_regfile_writes 42348 # number of floating regfile writes +system.cpu0.misc_regfile_reads 137565982 # number of misc regfile reads +system.cpu0.misc_regfile_writes 581037 # number of misc regfile writes +system.cpu0.icache.tags.replacements 983714 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.569506 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10510100 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 984226 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.678543 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7060452000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 317.023627 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 194.545879 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.619187 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.379972 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999159 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 163 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 12566693 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 12566693 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5337223 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5178698 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10515921 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5337223 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5178698 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10515921 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5337223 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5178698 # number of overall hits -system.cpu0.icache.overall_hits::total 10515921 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 558087 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 507747 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065834 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 558087 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 507747 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065834 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 558087 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 507747 # number of overall misses -system.cpu0.icache.overall_misses::total 1065834 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7713442509 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6842687514 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14556130023 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7713442509 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6842687514 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14556130023 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7713442509 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6842687514 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14556130023 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5895310 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5686445 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11581755 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5895310 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5686445 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11581755 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5895310 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5686445 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11581755 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094666 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089291 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.092027 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094666 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089291 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.092027 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094666 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089291 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.092027 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.218751 # 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average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643530 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993287 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21531295 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644042 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.431508 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 43200250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 257.568714 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 254.424573 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.503064 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.496923 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 643844 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.993221 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21529454 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644356 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.412359 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 43687250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 256.274589 # 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number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5999 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13528 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 101648096 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 101648096 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7014056 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6760706 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13774762 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3747600 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3513292 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7260892 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116614 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 126440 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243054 # 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number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1327358 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2962646 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7514 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6065 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13579 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1987963 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1722242 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3710205 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1987963 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1722242 # number of overall misses -system.cpu0.dcache.overall_misses::total 3710205 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5452544877 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5973510192 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11426055069 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85021863209 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 64469772613 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 149491635822 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 108104498 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 79946495 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 188050993 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 78000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 52000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 130000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 90474408086 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 70443282805 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 160917690891 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 90474408086 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 70443282805 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 160917690891 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7368208 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7156618 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14524826 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5404446 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4818547 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10222993 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124500 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 131972 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256472 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 119750 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 127885 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247635 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12772654 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11975165 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24747819 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12772654 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11975165 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24747819 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.046062 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057154 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051527 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.305040 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.272533 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289718 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060474 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045457 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052746 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1968779 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1742221 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3711000 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1968779 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1742221 # 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number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 78000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 168501 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 89347652079 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 70940705755 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 160288357834 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 89347652079 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 70940705755 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 160288357834 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7347547 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 7175569 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14523116 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5382888 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4840650 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10223538 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124128 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 132505 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 256633 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 119397 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 128251 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247648 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12730435 # 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number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3473 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 273 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.690469 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 81.571429 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 607832 # number of writebacks -system.cpu0.dcache.writebacks::total 607832 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 151038 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 211492 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 362530 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1512262 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1200569 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2712831 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 756 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 622 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1378 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1663300 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1412061 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3075361 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1663300 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1412061 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3075361 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188355 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 197536 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 385891 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 136308 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 112645 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248953 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6773 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5377 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12150 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 608227 # number of writebacks +system.cpu0.dcache.writebacks::total 608227 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 146313 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 215949 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 362262 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1499850 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1213774 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2713624 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 765 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 618 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1383 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1646163 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1429723 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3075886 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1646163 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1429723 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3075886 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187178 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 198914 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386092 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 135438 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 113584 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6749 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5447 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12196 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 324663 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 310181 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 634844 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 324663 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 310181 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 634844 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2624519460 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2624606109 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5249125569 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6430877605 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5124459707 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11555337312 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 85490752 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 61868005 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147358757 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 66000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 110000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9055397065 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7749065816 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16804462881 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9055397065 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7749065816 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16804462881 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91527132501 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90809770250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336902751 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13691854278 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13083150967 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26775005245 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 141500 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 141500 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 322616 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 312498 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635114 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 322616 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 312498 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635114 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2596085748 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2657791594 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5253877342 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6365986816 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5155346718 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11521333534 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84972752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62985504 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147958256 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 144499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8962072564 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7813138312 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16775210876 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8962072564 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7813138312 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16775210876 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91546998750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90791256750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182338255500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13710487847 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13068639684 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26779127531 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105218986779 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103892921217 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209111907996 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025563 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027602 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026568 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025221 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023377 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054402 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040743 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047374 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105257486597 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103859896434 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209117383031 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025475 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027721 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026585 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025161 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023465 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054371 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041108 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047523 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000031 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025419 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025902 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025653 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025419 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025902 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025653 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13933.898543 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13286.722972 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.612056 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47179.018143 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45492.118665 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46415.738360 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12622.287317 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11506.045192 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12128.292757 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000047 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025342 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026006 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025665 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025342 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026006 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025665 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13869.609399 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.510975 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13607.837878 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47002.959406 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45387.965893 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46266.328011 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12590.421099 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11563.338351 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.703509 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27891.681728 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24982.400005 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26470.223994 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27891.681728 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24982.400005 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26470.223994 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12041.583333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27779.380328 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25002.202612 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26412.913077 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27779.380328 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25002.202612 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26412.913077 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1958,15 +1706,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7303181 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5881126 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 346154 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4653929 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3750959 # Number of BTB hits +system.cpu1.branchPred.lookups 7323132 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5902490 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 346200 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4511574 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3765481 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 80.597684 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 679679 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34597 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 83.462690 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 676459 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34463 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1990,25 +1738,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25488049 # DTB read hits -system.cpu1.dtb.read_misses 36227 # DTB read misses -system.cpu1.dtb.write_hits 5538132 # DTB write hits -system.cpu1.dtb.write_misses 8320 # DTB write misses -system.cpu1.dtb.flush_tlb 512 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 25506602 # DTB read hits +system.cpu1.dtb.read_misses 36488 # DTB read misses +system.cpu1.dtb.write_hits 5558527 # DTB write hits +system.cpu1.dtb.write_misses 8439 # DTB write misses +system.cpu1.dtb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5495 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1338 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 228 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 679 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5463 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2276 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 677 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25524276 # DTB read accesses -system.cpu1.dtb.write_accesses 5546452 # DTB write accesses +system.cpu1.dtb.perms_faults 679 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25543090 # DTB read accesses +system.cpu1.dtb.write_accesses 5566966 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31026181 # DTB hits -system.cpu1.dtb.misses 44547 # DTB misses -system.cpu1.dtb.accesses 31070728 # DTB accesses +system.cpu1.dtb.hits 31065129 # DTB hits +system.cpu1.dtb.misses 44927 # DTB misses +system.cpu1.dtb.accesses 31110056 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2030,294 +1778,294 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5688452 # ITB inst hits -system.cpu1.itb.inst_misses 7006 # ITB inst misses +system.cpu1.itb.inst_hits 5703436 # ITB inst hits +system.cpu1.itb.inst_misses 7020 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 512 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2704 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 679 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2688 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1448 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5695458 # ITB inst accesses -system.cpu1.itb.hits 5688452 # DTB hits -system.cpu1.itb.misses 7006 # DTB misses -system.cpu1.itb.accesses 5695458 # DTB accesses -system.cpu1.numCycles 236990378 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5710456 # ITB inst accesses +system.cpu1.itb.hits 5703436 # DTB hits +system.cpu1.itb.misses 7020 # DTB misses +system.cpu1.itb.accesses 5710456 # DTB accesses +system.cpu1.numCycles 237056909 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14445279 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45031495 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7303181 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4430638 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9912685 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2288075 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 85272 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 49385810 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1038 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1883 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 43903 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1235955 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5686448 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 352687 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3068 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76688585 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.724367 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.076407 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14419718 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45234990 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7323132 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4441940 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9947853 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2287798 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 84999 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 49482147 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1272 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1896 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 44871 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1235484 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 189 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5701379 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 352457 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3064 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76794959 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.726229 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.078871 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66784675 87.09% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 633491 0.83% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 843387 1.10% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1127901 1.47% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 993338 1.30% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 549443 0.72% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1277588 1.67% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 369483 0.48% 94.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4109279 5.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66855647 87.06% 87.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 632615 0.82% 87.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 843009 1.10% 88.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1133482 1.48% 90.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1002056 1.30% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 554704 0.72% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1272745 1.66% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 372184 0.48% 94.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4128517 5.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76688585 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030816 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.190014 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15549027 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 50133952 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8864377 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 645129 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1493916 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 964413 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85194 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 52934695 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 283965 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1493916 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16391230 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19303163 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27652687 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8622958 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3222506 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 50466149 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 174 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 593171 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 1994496 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 690 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 52886950 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 233487672 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 213429055 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5328 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39332432 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13554518 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 579559 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 536966 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6477487 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9753455 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6333018 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 895982 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1122035 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 46958561 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 957421 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60864798 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 86364 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9232524 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23424717 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 226140 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76688585 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.793662 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.504660 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76794959 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030892 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.190819 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15530724 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50222847 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8895356 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 650267 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1493551 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 963840 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85500 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53154493 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286161 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1493551 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16374919 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19306160 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27715779 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8656578 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3245827 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 50687701 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 339 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 605911 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2002092 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 648 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53113804 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 234485879 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 214384735 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5365 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39540919 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13572884 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 579809 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 536931 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6499660 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9772559 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6360216 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 888468 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1099515 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47171321 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 962588 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 61070577 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 91971 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9248404 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23463374 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 229936 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76794959 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.795242 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.505673 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54509370 71.08% 71.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7300848 9.52% 80.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3460717 4.51% 85.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2863086 3.73% 88.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6124123 7.99% 96.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1373475 1.79% 98.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 772006 1.01% 99.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 222325 0.29% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 62635 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54534134 71.01% 71.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7328500 9.54% 80.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3483988 4.54% 85.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2874889 3.74% 88.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6131286 7.98% 96.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1377966 1.79% 98.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 776904 1.01% 99.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 225300 0.29% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 61992 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76688585 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76794959 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28981 0.66% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4176523 94.96% 95.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 192832 4.38% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29712 0.67% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 3 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4180230 94.88% 95.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 195658 4.44% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 12596 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28808168 47.33% 47.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45770 0.08% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 867 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26145062 42.96% 90.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5852305 9.62% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 12649 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28971083 47.44% 47.46% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46630 0.08% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 875 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.54% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26162080 42.84% 90.38% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5877234 9.62% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60864798 # Type of FU issued -system.cpu1.iq.rate 0.256824 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4398340 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072264 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 202935847 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57156855 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42177968 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11410 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6319 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5146 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65244557 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5985 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 312441 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 61070577 # Type of FU issued +system.cpu1.iq.rate 0.257620 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4405603 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072140 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 203466895 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57390461 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42382296 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11528 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6422 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5160 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65457468 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6063 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 311906 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2001655 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2943 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15220 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 749307 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1999074 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3048 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15122 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 750838 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17042804 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 332523 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17042744 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 332080 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1493916 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14868856 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 223350 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48029034 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96518 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9753455 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6333018 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 681732 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49156 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 5134 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15220 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 168778 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 134493 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 303271 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59837987 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25827716 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1026811 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1493551 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14864582 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 222698 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48241525 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 96453 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9772559 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6360216 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 687199 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 48610 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4313 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15122 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 168053 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 134565 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 302618 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 60042253 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25845364 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1028324 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 113052 # number of nop insts executed -system.cpu1.iew.exec_refs 31629861 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5852394 # Number of branches executed -system.cpu1.iew.exec_stores 5802145 # Number of stores executed -system.cpu1.iew.exec_rate 0.252491 # Inst execution rate -system.cpu1.iew.wb_sent 59370669 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42183114 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23501476 # num instructions producing a value -system.cpu1.iew.wb_consumers 42733790 # num instructions consuming a value +system.cpu1.iew.exec_nop 107616 # number of nop insts executed +system.cpu1.iew.exec_refs 31671376 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5872062 # Number of branches executed +system.cpu1.iew.exec_stores 5826012 # Number of stores executed +system.cpu1.iew.exec_rate 0.253282 # Inst execution rate +system.cpu1.iew.wb_sent 59578158 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42387456 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23643387 # num instructions producing a value +system.cpu1.iew.wb_consumers 43005248 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.177995 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.549951 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178807 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.549779 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9169088 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 731281 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 262316 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 75194669 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.511793 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.483255 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9166908 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 732652 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 262014 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 75301408 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.513681 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.486972 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60941986 81.05% 81.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7448338 9.91% 90.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1921902 2.56% 93.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1064941 1.42% 94.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 820613 1.09% 96.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 497482 0.66% 96.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 699016 0.93% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 369953 0.49% 98.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1430438 1.90% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60995111 81.00% 81.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7470337 9.92% 90.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1928698 2.56% 93.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1074141 1.43% 94.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 820415 1.09% 96.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 494186 0.66% 96.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 699344 0.93% 97.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 371316 0.49% 98.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1447860 1.92% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 75194669 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30395180 # Number of instructions committed -system.cpu1.commit.committedOps 38484098 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 75301408 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 30565527 # Number of instructions committed +system.cpu1.commit.committedOps 38680902 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13335511 # Number of memory references committed -system.cpu1.commit.loads 7751800 # Number of loads committed -system.cpu1.commit.membars 194141 # Number of memory barriers committed -system.cpu1.commit.branches 5126394 # Number of branches committed -system.cpu1.commit.fp_insts 5109 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34219487 # Number of committed integer instructions. -system.cpu1.commit.function_calls 483277 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1430438 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13382863 # Number of memory references committed +system.cpu1.commit.loads 7773485 # Number of loads committed +system.cpu1.commit.membars 194338 # Number of memory barriers committed +system.cpu1.commit.branches 5145142 # Number of branches committed +system.cpu1.commit.fp_insts 5126 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 34406663 # Number of committed integer instructions. +system.cpu1.commit.function_calls 483721 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1447860 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120543738 # The number of ROB reads -system.cpu1.rob.rob_writes 96843723 # The number of ROB writes -system.cpu1.timesIdled 866392 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 160301793 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2319061347 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 30318400 # Number of Instructions Simulated -system.cpu1.committedOps 38407318 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 30318400 # Number of Instructions Simulated -system.cpu1.cpi 7.816718 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.816718 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.127931 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.127931 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 271568545 # number of integer regfile reads -system.cpu1.int_regfile_writes 43555908 # number of integer regfile writes -system.cpu1.fp_regfile_reads 45194 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42320 # number of floating regfile writes -system.cpu1.misc_regfile_reads 132647791 # number of misc regfile reads -system.cpu1.misc_regfile_writes 591619 # number of misc regfile writes +system.cpu1.rob.rob_reads 120827478 # The number of ROB reads +system.cpu1.rob.rob_writes 97232532 # The number of ROB writes +system.cpu1.timesIdled 865086 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 160261950 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2316983227 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 30492768 # Number of Instructions Simulated +system.cpu1.committedOps 38608143 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 30492768 # Number of Instructions Simulated +system.cpu1.cpi 7.774201 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.774201 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.128631 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.128631 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 272500909 # number of integer regfile reads +system.cpu1.int_regfile_writes 43779735 # number of integer regfile writes +system.cpu1.fp_regfile_reads 45015 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42294 # number of floating regfile writes +system.cpu1.misc_regfile_reads 133085319 # number of misc regfile reads +system.cpu1.misc_regfile_writes 592959 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2334,17 +2082,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518507680269 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1518507680269 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518507680269 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1518507680269 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736889440801 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736889440801 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736889440801 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736889440801 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83057 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83061 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |