diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | 3293 |
1 files changed, 1658 insertions, 1635 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index ef9bf74a4..2ae3638d8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,166 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.550648 # Number of seconds simulated -sim_ticks 2550647964000 # Number of ticks simulated -final_tick 2550647964000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.550603 # Number of seconds simulated +sim_ticks 2550603285500 # Number of ticks simulated +final_tick 2550603285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57676 # Simulator instruction rate (inst/s) -host_op_rate 74213 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2439007396 # Simulator tick rate (ticks/s) -host_mem_usage 470664 # Number of bytes of host memory used -host_seconds 1045.77 # Real time elapsed on the host -sim_insts 60315890 # Number of instructions simulated -sim_ops 77609880 # Number of ops (including micro ops) simulated +host_inst_rate 56179 # Simulator instruction rate (inst/s) +host_op_rate 72287 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2375661490 # Simulator tick rate (ticks/s) +host_mem_usage 471120 # Number of bytes of host memory used +host_seconds 1073.64 # Real time elapsed on the host +sim_insts 60315997 # Number of instructions simulated +sim_ops 77609994 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1984 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 483008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5043284 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 315584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4051356 # Number of bytes read from this memory -system.physmem.bytes_read::total 131006576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 483008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 315584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785856 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521376 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494724 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801956 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 487168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5091220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 310848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4002308 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 487168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 310848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785472 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521388 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494684 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801544 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 31 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7547 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 78836 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4931 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 63309 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293483 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59154 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380344 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373681 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813179 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47482259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 803 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7612 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 79585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4857 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 62537 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293452 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59148 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380347 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373671 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813166 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47483091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 778 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 189367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1977256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 123727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1588363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51362077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 189367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 123727 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313094 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596466 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586017 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2666756 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47482259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 191001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1996085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 121872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1569161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51362340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 191001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 121872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 312873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596482 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2666641 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47483091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 778 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 189367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2573722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 123727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2174381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54028833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293483 # Number of read requests accepted -system.physmem.writeReqs 813179 # Number of write requests accepted -system.physmem.readBursts 15293483 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813179 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 976671488 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2111424 # Total number of bytes read from write queue -system.physmem.bytesWritten 6834624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131006576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801956 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 32991 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706366 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4694 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955809 # Per bank write bursts -system.physmem.perBankRdBursts::1 953120 # Per bank write bursts -system.physmem.perBankRdBursts::2 953063 # Per bank write bursts -system.physmem.perBankRdBursts::3 953290 # Per bank write bursts -system.physmem.perBankRdBursts::4 955524 # Per bank write bursts -system.physmem.perBankRdBursts::5 952811 # Per bank write bursts -system.physmem.perBankRdBursts::6 952747 # Per bank write bursts -system.physmem.perBankRdBursts::7 952554 # Per bank write bursts -system.physmem.perBankRdBursts::8 956154 # Per bank write bursts -system.physmem.perBankRdBursts::9 953015 # Per bank write bursts -system.physmem.perBankRdBursts::10 952848 # Per bank write bursts -system.physmem.perBankRdBursts::11 952579 # Per bank write bursts -system.physmem.perBankRdBursts::12 956184 # Per bank write bursts -system.physmem.perBankRdBursts::13 953741 # Per bank write bursts -system.physmem.perBankRdBursts::14 953594 # Per bank write bursts -system.physmem.perBankRdBursts::15 953459 # Per bank write bursts -system.physmem.perBankWrBursts::0 6616 # Per bank write bursts -system.physmem.perBankWrBursts::1 6407 # Per bank write bursts -system.physmem.perBankWrBursts::2 6542 # Per bank write bursts -system.physmem.perBankWrBursts::3 6564 # Per bank write bursts -system.physmem.perBankWrBursts::4 6491 # Per bank write bursts -system.physmem.perBankWrBursts::5 6761 # Per bank write bursts -system.physmem.perBankWrBursts::6 6753 # Per bank write bursts -system.physmem.perBankWrBursts::7 6706 # Per bank write bursts -system.physmem.perBankWrBursts::8 7029 # Per bank write bursts -system.physmem.perBankWrBursts::9 6806 # Per bank write bursts -system.physmem.perBankWrBursts::10 6476 # Per bank write bursts -system.physmem.perBankWrBursts::11 6118 # Per bank write bursts -system.physmem.perBankWrBursts::12 7056 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 191001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2592566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 121872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2155173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54028981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293452 # Number of read requests accepted +system.physmem.writeReqs 813166 # Number of write requests accepted +system.physmem.readBursts 15293452 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813166 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 977025792 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1755136 # Total number of bytes read from write queue +system.physmem.bytesWritten 6829888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131004952 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801544 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 27424 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706426 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4680 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955870 # Per bank write bursts +system.physmem.perBankRdBursts::1 953353 # Per bank write bursts +system.physmem.perBankRdBursts::2 953267 # Per bank write bursts +system.physmem.perBankRdBursts::3 953402 # Per bank write bursts +system.physmem.perBankRdBursts::4 955744 # Per bank write bursts +system.physmem.perBankRdBursts::5 953745 # Per bank write bursts +system.physmem.perBankRdBursts::6 953482 # Per bank write bursts +system.physmem.perBankRdBursts::7 953247 # Per bank write bursts +system.physmem.perBankRdBursts::8 956258 # Per bank write bursts +system.physmem.perBankRdBursts::9 953771 # Per bank write bursts +system.physmem.perBankRdBursts::10 953551 # Per bank write bursts +system.physmem.perBankRdBursts::11 953111 # Per bank write bursts +system.physmem.perBankRdBursts::12 956206 # Per bank write bursts +system.physmem.perBankRdBursts::13 953857 # Per bank write bursts +system.physmem.perBankRdBursts::14 953612 # Per bank write bursts +system.physmem.perBankRdBursts::15 953552 # Per bank write bursts +system.physmem.perBankWrBursts::0 6609 # Per bank write bursts +system.physmem.perBankWrBursts::1 6381 # Per bank write bursts +system.physmem.perBankWrBursts::2 6537 # Per bank write bursts +system.physmem.perBankWrBursts::3 6560 # Per bank write bursts +system.physmem.perBankWrBursts::4 6488 # Per bank write bursts +system.physmem.perBankWrBursts::5 6754 # Per bank write bursts +system.physmem.perBankWrBursts::6 6745 # Per bank write bursts +system.physmem.perBankWrBursts::7 6685 # Per bank write bursts +system.physmem.perBankWrBursts::8 7023 # Per bank write bursts +system.physmem.perBankWrBursts::9 6801 # Per bank write bursts +system.physmem.perBankWrBursts::10 6470 # Per bank write bursts +system.physmem.perBankWrBursts::11 6120 # Per bank write bursts +system.physmem.perBankWrBursts::12 7060 # Per bank write bursts system.physmem.perBankWrBursts::13 6677 # Per bank write bursts -system.physmem.perBankWrBursts::14 6959 # Per bank write bursts -system.physmem.perBankWrBursts::15 6830 # Per bank write bursts +system.physmem.perBankWrBursts::14 6963 # Per bank write bursts +system.physmem.perBankWrBursts::15 6844 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2550646795500 # Total gap between requests +system.physmem.totGap 2550602119500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 44 # Read request sizes (log2) +system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154623 # Read request sizes (log2) +system.physmem.readPktSize::6 154598 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754025 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59154 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1055042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 994364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 947765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 947544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 945397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 945218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2783572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2783267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3699218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 24042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 23218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 23233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 22263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 21619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59148 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1066844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1005139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 964469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1068011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 971384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1033822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2692544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2602827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3401172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 102949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 95927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 92392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -174,61 +162,61 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -237,93 +225,76 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 965273 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1013.486813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 999.850047 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 92.541667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 4202 0.44% 0.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 3517 0.36% 0.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1855 0.19% 0.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1291 0.13% 1.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 949 0.10% 1.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 717 0.07% 1.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 589 0.06% 1.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 765 0.08% 1.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 951388 98.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 965273 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5001 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3051.486103 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 52637.524815 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 4974 99.46% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 8 0.16% 99.64% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 6 0.12% 99.76% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 2 0.04% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.84% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.14% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1010962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.187598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 908.669037 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 201.227455 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22588 2.23% 2.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20116 1.99% 4.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8785 0.87% 5.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2331 0.23% 5.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2167 0.21% 5.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1761 0.17% 5.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9115 0.90% 6.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 858 0.08% 6.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943241 93.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1010962 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2514.580135 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 47785.198367 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6044 99.56% 99.56% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.57% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 6 0.10% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 2 0.03% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5001 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5001 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.353929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.695200 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.701170 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 8 0.16% 0.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 2 0.04% 0.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 3 0.06% 0.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.02% 0.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 8 0.16% 0.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 1 0.02% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 1 0.02% 0.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 3 0.06% 0.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 5 0.10% 0.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 2 0.04% 0.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 5 0.10% 0.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 2 0.04% 0.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 1 0.02% 0.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 1 0.02% 0.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 10 0.20% 1.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2816 56.31% 57.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 26 0.52% 57.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 135 2.70% 60.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 879 17.58% 78.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 49 0.98% 79.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 23 0.46% 79.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.30% 79.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 25 0.50% 80.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 14 0.28% 80.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 18 0.36% 81.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 7 0.14% 81.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 15 0.30% 81.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 16 0.32% 81.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 18 0.36% 82.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 15 0.30% 82.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 8 0.16% 82.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 16 0.32% 82.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 10 0.20% 83.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.02% 83.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.02% 83.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 3 0.06% 83.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 243 4.86% 88.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 480 9.60% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 27 0.54% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 20 0.40% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 27 0.54% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 21 0.42% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 16 0.32% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5001 # Writes before turning the bus around for reads -system.physmem.totQLat 577566851750 # Total ticks spent queuing -system.physmem.totMemAccLat 682115428000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76302460000 # Total ticks spent in databus transfers -system.physmem.totBankLat 28246116250 # Total ticks spent accessing banks -system.physmem.avgQLat 37847.20 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1850.93 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6071 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6071 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.578158 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.392553 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.387042 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 4 0.07% 0.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.03% 0.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 7 0.12% 0.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 3 0.05% 0.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 4 0.07% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 6 0.10% 0.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 2 0.03% 0.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 3 0.05% 0.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 2 0.03% 0.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 4 0.07% 0.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 12 0.20% 0.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2739 45.12% 46.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 35 0.58% 46.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1542 25.40% 72.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1308 21.55% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 93 1.53% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 45 0.74% 95.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 49 0.81% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 58 0.96% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 25 0.41% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 17 0.28% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 20 0.33% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 16 0.26% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 13 0.21% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 14 0.23% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 14 0.23% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 16 0.26% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 10 0.16% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6071 # Writes before turning the bus around for reads +system.physmem.totQLat 393355196000 # Total ticks spent queuing +system.physmem.totMemAccLat 679593221000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76330140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25766.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44698.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 382.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44516.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.06 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s @@ -331,299 +302,308 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.01 # Data bus utilization in percentage system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.73 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.38 # Average write queue length when enqueuing -system.physmem.readRowHits 14274135 # Number of row buffer hits during reads -system.physmem.writeRowHits 91331 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.51 # Row buffer hit rate for writes -system.physmem.avgGap 158359.74 # Average gap between requests -system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.60 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54969038 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346130 # Transaction distribution -system.membus.trans_dist::ReadResp 16346133 # Transaction distribution -system.membus.trans_dist::WriteReq 763365 # Transaction distribution -system.membus.trans_dist::WriteResp 763365 # Transaction distribution -system.membus.trans_dist::Writeback 59154 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4694 # Transaction distribution -system.membus.trans_dist::ReadExReq 131434 # Transaction distribution -system.membus.trans_dist::ReadExResp 131434 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution -system.membus.trans_dist::StoreCondReq 3 # Transaction distribution -system.membus.trans_dist::StoreCondResp 3 # Transaction distribution +system.physmem.avgRdQLen 6.51 # Average read queue length when enqueuing +system.physmem.avgWrQLen 15.34 # Average write queue length when enqueuing +system.physmem.readRowHits 14270645 # Number of row buffer hits during reads +system.physmem.writeRowHits 91138 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.38 # Row buffer hit rate for writes +system.physmem.avgGap 158357.40 # Average gap between requests +system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2202343950500 # Time in different power states +system.physmem.memoryStateTime::REF 85170020000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 263082705750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54969203 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346092 # Transaction distribution +system.membus.trans_dist::ReadResp 16346092 # Transaction distribution +system.membus.trans_dist::WriteReq 763361 # Transaction distribution +system.membus.trans_dist::WriteResp 763361 # Transaction distribution +system.membus.trans_dist::Writeback 59148 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4680 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4680 # Transaction distribution +system.membus.trans_dist::ReadExReq 131444 # Transaction distribution +system.membus.trans_dist::ReadExResp 131444 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383060 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885926 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272780 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885816 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272670 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550412 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34550302 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390486 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16698004 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19096138 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16695968 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19094102 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140206666 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140206666 # Total data (bytes) +system.membus.tot_pkt_size::total 140204630 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140204630 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487459000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486938500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3645000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3616000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17565357500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17564463000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4737629056 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4735162713 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37816335199 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37454635709 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64394 # number of replacements -system.l2c.tags.tagsinuse 51423.269942 # Cycle average of tags in use -system.l2c.tags.total_refs 1904392 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129782 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.673776 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2513283956500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36971.606132 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 22.825180 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000372 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4577.267389 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3052.603978 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.951997 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3614.635006 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3176.379887 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564142 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000348 # Average percentage of cache occupancy +system.l2c.tags.replacements 64370 # number of replacements +system.l2c.tags.tagsinuse 51446.531370 # Cycle average of tags in use +system.l2c.tags.total_refs 1904863 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129760 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.679894 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2513258094500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36996.902854 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 21.266230 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4638.850911 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3223.219228 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.615555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3561.358912 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2994.317308 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564528 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000324 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.069844 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046579 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.055155 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.048468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784657 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 21 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65367 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.070783 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.049182 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.054342 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.045690 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.785012 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65368 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3070 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6838 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55080 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000320 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997421 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18929537 # Number of tag accesses -system.l2c.tags.data_accesses 18929537 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 32378 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6463 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 508619 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 187861 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 31368 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7240 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 462078 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 199585 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435592 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608227 # number of Writeback hits -system.l2c.Writeback_hits::total 608227 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 20 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 19 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 39 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60126 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52843 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112969 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32378 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6463 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 508619 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 247987 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 31368 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7240 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 462078 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 252428 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548561 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32378 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6463 # number of overall hits -system.l2c.overall_hits::cpu0.inst 508619 # number of overall hits -system.l2c.overall_hits::cpu0.data 247987 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 31368 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7240 # number of overall hits -system.l2c.overall_hits::cpu1.inst 462078 # number of overall hits -system.l2c.overall_hits::cpu1.data 252428 # number of overall hits -system.l2c.overall_hits::total 1548561 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 32 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3064 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6835 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55083 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997437 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18932032 # Number of tag accesses +system.l2c.tags.data_accesses 18932032 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 32158 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6860 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 505744 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 187679 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 31450 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7231 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 465794 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 199404 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1436320 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 607907 # number of Writeback hits +system.l2c.Writeback_hits::total 607907 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 19 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 58462 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 54465 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112927 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32158 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6860 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 505744 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 246141 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 31450 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7231 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 465794 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 253869 # number of demand (read+write) hits +system.l2c.demand_hits::total 1549247 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32158 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6860 # number of overall hits +system.l2c.overall_hits::cpu0.inst 505744 # number of overall hits +system.l2c.overall_hits::cpu0.data 246141 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 31450 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7231 # number of overall hits +system.l2c.overall_hits::cpu1.inst 465794 # number of overall hits +system.l2c.overall_hits::cpu1.data 253869 # number of overall hits +system.l2c.overall_hits::total 1549247 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 31 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7439 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6013 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4938 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4716 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23150 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 763750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 288530250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3881249868 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9573515275 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6521499 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83889052500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83054276000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166949849999 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8950146108 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8426611000 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010320 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022163 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015784 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988464 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988381 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.988428 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.559767 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.519493 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541221 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000963 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014601 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.246315 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010320 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.199825 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091614 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000963 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014601 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.246315 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010320 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.199825 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091614 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60965.563562 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62849.336283 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60431.379102 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.332037 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.028816 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61909.037929 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61530.932970 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61740.166261 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59382.099596 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61974.555949 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60166.599067 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61748.237856 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61701.909837 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59382.099596 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61974.555949 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60166.599067 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61748.237856 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61701.909837 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.566614 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.688361 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61669.274080 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61089.105156 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61412.836106 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61615.745339 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61214.590057 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61268.145063 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61615.745339 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61214.590057 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61268.145063 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -799,10 +767,6 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency -system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency -system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency @@ -814,43 +778,40 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58424320 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676714 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676716 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608227 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2954 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246181 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246181 # Transaction distribution -system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution -system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution -system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967568 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5797861 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37552 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149979 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7952960 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62924224 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85579658 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 54820 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 255152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148813854 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148813854 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 206020 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4963822946 # Layer occupancy (ticks) +system.toL2Bus.throughput 58427348 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677396 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677395 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763361 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763361 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 607907 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2938 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2945 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246147 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246147 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1969203 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796633 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38454 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149595 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7953885 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62977408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85532246 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 56372 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254604 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148820630 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148820630 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 204356 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4962673723 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4432706696 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4436346984 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4484503287 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4483051170 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23902881 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24406904 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86618127 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86367392 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48419467 # Throughput (bytes/s) +system.iobus.throughput 48420315 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322169 # Transaction distribution system.iobus.trans_dist::ReadResp 16322169 # Transaction distribution system.iobus.trans_dist::WriteReq 8177 # Transaction distribution @@ -960,17 +921,17 @@ system.iobus.reqLayer25.occupancy 15138816000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374883000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37825687801 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38146923291 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7508483 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5992866 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 375676 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4822577 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3918936 # Number of BTB hits +system.cpu0.branchPred.lookups 7527303 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6005482 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 376664 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4812068 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3910560 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.262279 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 722501 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39246 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.265685 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 724420 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 38989 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -994,25 +955,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25709068 # DTB read hits -system.cpu0.dtb.read_misses 39624 # DTB read misses -system.cpu0.dtb.write_hits 6152335 # DTB write hits -system.cpu0.dtb.write_misses 10221 # DTB write misses +system.cpu0.dtb.read_hits 25762472 # DTB read hits +system.cpu0.dtb.read_misses 39475 # DTB read misses +system.cpu0.dtb.write_hits 6143291 # DTB write hits +system.cpu0.dtb.write_misses 10324 # DTB write misses system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 760 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5608 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1406 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 264 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5580 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1376 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 646 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25748692 # DTB read accesses -system.cpu0.dtb.write_accesses 6162556 # DTB write accesses +system.cpu0.dtb.perms_faults 639 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25801947 # DTB read accesses +system.cpu0.dtb.write_accesses 6153615 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31861403 # DTB hits -system.cpu0.dtb.misses 49845 # DTB misses -system.cpu0.dtb.accesses 31911248 # DTB accesses +system.cpu0.dtb.hits 31905763 # DTB hits +system.cpu0.dtb.misses 49799 # DTB misses +system.cpu0.dtb.accesses 31955562 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1034,687 +995,714 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5876098 # ITB inst hits -system.cpu0.itb.inst_misses 7014 # ITB inst misses +system.cpu0.itb.inst_hits 5893431 # ITB inst hits +system.cpu0.itb.inst_misses 7431 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 760 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2644 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2617 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1469 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1506 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5883112 # ITB inst accesses -system.cpu0.itb.hits 5876098 # DTB hits -system.cpu0.itb.misses 7014 # DTB misses -system.cpu0.itb.accesses 5883112 # DTB accesses -system.cpu0.numCycles 242192321 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5900862 # ITB inst accesses +system.cpu0.itb.hits 5893431 # DTB hits +system.cpu0.itb.misses 7431 # DTB misses +system.cpu0.itb.accesses 5900862 # DTB accesses +system.cpu0.numCycles 242264674 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15567613 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45445847 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7508483 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4641437 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10272972 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2435180 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 81106 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 50250706 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1544 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1986 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 48114 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1489776 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 378 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5874191 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 367063 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2900 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 79394723 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.721041 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.068559 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15531926 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45587183 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7527303 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4634980 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10285875 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2434733 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 89107 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 50171859 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2068 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 54478 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1474048 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 435 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5891523 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 366856 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3025 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 79291736 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.723314 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.072188 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 69128739 87.07% 87.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 676261 0.85% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 870795 1.10% 89.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1169302 1.47% 90.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1115285 1.40% 91.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 553948 0.70% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1287197 1.62% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 378519 0.48% 94.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4214677 5.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 69012854 87.04% 87.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 680232 0.86% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 874808 1.10% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1172230 1.48% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1090891 1.38% 91.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 557599 0.70% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1295199 1.63% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 379880 0.48% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4228043 5.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79394723 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031002 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.187644 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16658432 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 51288095 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9197431 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 656874 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1591763 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1006093 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91406 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 54494283 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 303520 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1591763 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17551658 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20345183 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27653568 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8896202 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3354292 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 51932303 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 196 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 500448 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2179621 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 261 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 53595851 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 240832893 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 219678051 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5082 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39195467 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14400384 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 591696 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 540219 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6961736 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10014185 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6974197 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1050889 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1353332 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 48232956 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1025841 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 61971057 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 88766 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9957722 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24611703 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 275811 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 79394723 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.780544 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.499047 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 79291736 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031071 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.188171 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16635366 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 51194908 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9213198 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 653944 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1592125 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1010665 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90813 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 54600074 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 300654 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1592125 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17527482 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20299787 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27625200 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8910460 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3334547 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 52031373 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 331 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 485563 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2176301 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 182 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 53736698 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 241285167 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 220106334 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4864 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39390817 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14345881 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 590593 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 539084 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6947132 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10055649 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6962422 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1056834 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1358453 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 48348288 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1003135 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62086915 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 89013 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9905639 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24691410 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 254686 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 79291736 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.783019 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.501466 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 56910995 71.68% 71.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7345017 9.25% 80.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3503110 4.41% 85.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2918035 3.68% 89.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6157997 7.76% 96.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1482939 1.87% 98.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 783446 0.99% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 227116 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 66068 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 56790483 71.62% 71.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7331291 9.25% 80.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3517102 4.44% 85.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2900884 3.66% 88.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6182474 7.80% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1488398 1.88% 98.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 785922 0.99% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 230106 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 65076 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 79394723 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 79291736 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29670 0.67% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4193006 94.32% 94.99% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 222912 5.01% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 31039 0.70% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4198728 94.33% 95.03% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 221343 4.97% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 15869 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29065604 46.90% 46.93% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46869 0.08% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1239 0.00% 47.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26385475 42.58% 89.58% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6455974 10.42% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14970 0.02% 0.02% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29137192 46.93% 46.95% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47374 0.08% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1226 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26440432 42.59% 89.62% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6445693 10.38% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 61971057 # Type of FU issued -system.cpu0.iq.rate 0.255875 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4445589 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.071737 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 207909567 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59225484 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43186225 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11292 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6130 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5133 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66394829 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5948 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 311727 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62086915 # Type of FU issued +system.cpu0.iq.rate 0.256277 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4451111 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.071692 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208044448 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59266351 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43285904 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 10871 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5830 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4924 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66517304 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5752 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 316537 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2130667 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3740 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15655 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 850179 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2144033 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4052 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15721 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 849604 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17067257 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348827 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17082730 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 349385 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1591763 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15715155 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 239745 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 49373573 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105603 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10014185 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6974197 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 727713 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 55741 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4727 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15655 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 183161 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 144870 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 328031 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 60906320 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26058550 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1064737 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1592125 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15682380 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 239912 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 49471978 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105539 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10055649 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6962422 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 704937 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56286 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4027 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15721 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 184221 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 145235 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 329456 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61023718 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26110824 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1063197 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 114776 # number of nop insts executed -system.cpu0.iew.exec_refs 32455686 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5967734 # Number of branches executed -system.cpu0.iew.exec_stores 6397136 # Number of stores executed -system.cpu0.iew.exec_rate 0.251479 # Inst execution rate -system.cpu0.iew.wb_sent 60414213 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43191358 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23287316 # num instructions producing a value -system.cpu0.iew.wb_consumers 42834885 # num instructions consuming a value +system.cpu0.iew.exec_nop 120555 # number of nop insts executed +system.cpu0.iew.exec_refs 32498156 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5982225 # Number of branches executed +system.cpu0.iew.exec_stores 6387332 # Number of stores executed +system.cpu0.iew.exec_rate 0.251889 # Inst execution rate +system.cpu0.iew.wb_sent 60528797 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43290828 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23369621 # num instructions producing a value +system.cpu0.iew.wb_consumers 42956226 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.178335 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.543653 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.178692 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544033 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9785836 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 750030 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 285660 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 77802960 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.502286 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.465598 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9786876 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 748449 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 287258 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 77699611 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.504830 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.472024 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 63388396 81.47% 81.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7400911 9.51% 90.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1988257 2.56% 93.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1098992 1.41% 94.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 865715 1.11% 96.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 575312 0.74% 96.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 733525 0.94% 97.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 350428 0.45% 98.20% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1401424 1.80% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 63277588 81.44% 81.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7407512 9.53% 90.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1967451 2.53% 93.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1105852 1.42% 94.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 852897 1.10% 96.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 576328 0.74% 96.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 737114 0.95% 97.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 349768 0.45% 98.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1425101 1.83% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 77802960 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29900744 # Number of instructions committed -system.cpu0.commit.committedOps 39079359 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 77699611 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30084753 # Number of instructions committed +system.cpu0.commit.committedOps 39225066 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14007536 # Number of memory references committed -system.cpu0.commit.loads 7883518 # Number of loads committed -system.cpu0.commit.membars 209346 # Number of memory barriers committed -system.cpu0.commit.branches 5162239 # Number of branches committed -system.cpu0.commit.fp_insts 5086 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34792812 # Number of committed integer instructions. -system.cpu0.commit.function_calls 507721 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1401424 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14024434 # Number of memory references committed +system.cpu0.commit.loads 7911616 # Number of loads committed +system.cpu0.commit.membars 209739 # Number of memory barriers committed +system.cpu0.commit.branches 5192960 # Number of branches committed +system.cpu0.commit.fp_insts 4874 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34907078 # Number of committed integer instructions. +system.cpu0.commit.function_calls 509367 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 25154804 64.13% 64.13% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 44602 0.11% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 1226 0.00% 64.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.25% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7911616 20.17% 84.42% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 6112818 15.58% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::total 39225066 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1425101 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124291086 # The number of ROB reads -system.cpu0.rob.rob_writes 99365166 # The number of ROB writes -system.cpu0.timesIdled 908697 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 162797598 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2248209209 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29823122 # Number of Instructions Simulated -system.cpu0.committedOps 39001737 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29823122 # Number of Instructions Simulated -system.cpu0.cpi 8.120958 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.120958 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.123138 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.123138 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 276680521 # number of integer regfile reads -system.cpu0.int_regfile_writes 43875243 # number of integer regfile writes -system.cpu0.fp_regfile_reads 44965 # number of floating regfile reads -system.cpu0.fp_regfile_writes 42348 # number of floating regfile writes -system.cpu0.misc_regfile_reads 137565982 # number of misc regfile reads -system.cpu0.misc_regfile_writes 581037 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983714 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.569506 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10510100 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984226 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.678543 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7060452000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 317.023627 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 194.545879 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.619187 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.379972 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999159 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 124324951 # The number of ROB reads +system.cpu0.rob.rob_writes 99658992 # The number of ROB writes +system.cpu0.timesIdled 907419 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 162972938 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2247980405 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 30002566 # Number of Instructions Simulated +system.cpu0.committedOps 39142879 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 30002566 # Number of Instructions Simulated +system.cpu0.cpi 8.074798 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.074798 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.123842 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.123842 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 277224657 # number of integer regfile reads +system.cpu0.int_regfile_writes 43993248 # number of integer regfile writes +system.cpu0.fp_regfile_reads 44815 # number of floating regfile reads +system.cpu0.fp_regfile_writes 42286 # number of floating regfile writes +system.cpu0.misc_regfile_reads 137449038 # number of misc regfile reads +system.cpu0.misc_regfile_writes 580454 # number of misc regfile writes +system.cpu0.icache.tags.replacements 984532 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.571226 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10502635 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 985044 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.662097 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7040991250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 317.697202 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 193.874025 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.620502 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.378660 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999163 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 163 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 12559701 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 12559701 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5314791 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5195309 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10510100 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5314791 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5195309 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10510100 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5314791 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5195309 # number of overall hits -system.cpu0.icache.overall_hits::total 10510100 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 559278 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 506065 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065343 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 559278 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 506065 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065343 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 559278 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 506065 # number of overall misses -system.cpu0.icache.overall_misses::total 1065343 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7693667190 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6830219775 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14523886965 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7693667190 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6830219775 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14523886965 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7693667190 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6830219775 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14523886965 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5874069 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5701374 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11575443 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5874069 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5701374 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11575443 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5874069 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5701374 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11575443 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.095211 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.088762 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.095211 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.088762 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.095211 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.088762 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13756.427376 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13496.724284 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13633.061807 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13756.427376 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13496.724284 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13633.061807 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13756.427376 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13496.724284 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13633.061807 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6850 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 406 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.871921 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 12553911 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 12553911 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 5335132 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5167503 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10502635 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5335132 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5167503 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10502635 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5335132 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5167503 # number of overall hits +system.cpu0.icache.overall_hits::total 10502635 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 556266 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 509949 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1066215 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 556266 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 509949 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1066215 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 556266 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 509949 # number of overall misses +system.cpu0.icache.overall_misses::total 1066215 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7659182978 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6870398274 # 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number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5677452 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11568850 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5891398 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5677452 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11568850 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094420 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089820 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.092163 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094420 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089820 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.092163 # 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number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5591223594 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11815789982 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6224566388 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5591223594 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11815789982 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6224566388 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5591223594 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11815789982 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8993000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8993000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8993000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8993000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087219 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082999 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085148 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087219 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.082999 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085148 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087219 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.082999 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085148 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12113.798603 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11994.970857 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12113.798603 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11994.970857 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12113.798603 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11994.970857 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643844 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993221 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21529454 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644356 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.412359 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 43687250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 256.274589 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 255.718633 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.500536 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.499450 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 643424 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.993257 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21526419 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 643936 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.429439 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 43468250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.820066 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.173192 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497695 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502291 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 101648096 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 101648096 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7014056 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6760706 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13774762 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3747600 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3513292 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7260892 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116614 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 126440 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243054 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 119391 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 128245 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247636 # 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Number of tag accesses +system.cpu0.dcache.tags.data_accesses 101635836 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7044250 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6727132 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13771382 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3751595 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3509581 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261176 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116856 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 126271 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243127 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 119516 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 128128 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247644 # 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average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14564.877994 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15211.386729 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 52038.246168 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 47922.572947 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50174.521862 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14208.327160 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13440.945024 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13860.574333 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14041.750000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45382.265901 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40718.545899 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43192.766864 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45382.265901 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40718.545899 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43192.766864 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 37128 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 22269 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3473 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 273 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5155346718 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11521333534 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84972752 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62985504 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147958256 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 144499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8962072564 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7813138312 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16775210876 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8962072564 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7813138312 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16775210876 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91546998750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90791256750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182338255500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13710487847 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13068639684 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26779127531 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105257486597 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103859896434 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209117383031 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025475 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027721 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026585 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025161 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023465 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054371 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041108 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047523 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000047 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025342 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026006 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025665 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025342 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026006 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025665 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13869.609399 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.510975 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13607.837878 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47002.959406 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45387.965893 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46266.328011 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12590.421099 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11563.338351 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.703509 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 607907 # number of writebacks +system.cpu0.dcache.writebacks::total 607907 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 148329 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 214670 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 362999 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1486511 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1226891 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2713402 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 703 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 661 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1364 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1634840 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1441561 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3076401 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1634840 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1441561 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3076401 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187197 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 198540 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 385737 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 134395 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 114579 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248974 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6694 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5469 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12163 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 321592 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 313119 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 634711 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 321592 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 313119 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 634711 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2595681199 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2634071602 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5229752801 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6377279279 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5102642760 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11479922039 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 83521753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63731007 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147252760 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 77000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8972960478 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7736714362 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16709674840 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8972960478 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7736714362 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16709674840 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91614967500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90722197000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182337164500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13706653581 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13072228739 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26778882320 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105321621081 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103794425739 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209116046820 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025366 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027805 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026566 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025015 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023619 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053874 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041306 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047391 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000039 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025218 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026112 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025651 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025218 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026112 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025651 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13866.040583 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13267.208633 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13557.819968 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47451.759954 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44533.839185 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46108.919160 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12477.106812 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11653.137137 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12106.615144 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12041.583333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27779.380328 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25002.202612 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26412.913077 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27779.380328 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25002.202612 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26412.913077 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27901.690583 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24708.543276 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26326.430202 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27901.690583 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24708.543276 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26326.430202 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency -system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency -system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7323132 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5902490 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 346200 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4511574 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3765481 # Number of BTB hits +system.cpu1.branchPred.lookups 7300035 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5887077 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 345091 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4651296 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3771120 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 83.462690 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 676459 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34463 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 81.076758 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 673548 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34495 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1738,25 +1726,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25506602 # DTB read hits -system.cpu1.dtb.read_misses 36488 # DTB read misses -system.cpu1.dtb.write_hits 5558527 # DTB write hits -system.cpu1.dtb.write_misses 8439 # DTB write misses +system.cpu1.dtb.read_hits 25450161 # DTB read hits +system.cpu1.dtb.read_misses 36388 # DTB read misses +system.cpu1.dtb.write_hits 5568332 # DTB write hits +system.cpu1.dtb.write_misses 8538 # DTB write misses system.cpu1.dtb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 679 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5463 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2276 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5495 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2244 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 247 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 679 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25543090 # DTB read accesses -system.cpu1.dtb.write_accesses 5566966 # DTB write accesses +system.cpu1.dtb.perms_faults 710 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25486549 # DTB read accesses +system.cpu1.dtb.write_accesses 5576870 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31065129 # DTB hits -system.cpu1.dtb.misses 44927 # DTB misses -system.cpu1.dtb.accesses 31110056 # DTB accesses +system.cpu1.dtb.hits 31018493 # DTB hits +system.cpu1.dtb.misses 44926 # DTB misses +system.cpu1.dtb.accesses 31063419 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1778,294 +1766,329 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5703436 # ITB inst hits -system.cpu1.itb.inst_misses 7020 # ITB inst misses +system.cpu1.itb.inst_hits 5679651 # ITB inst hits +system.cpu1.itb.inst_misses 6870 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 679 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2688 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2692 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1570 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5710456 # ITB inst accesses -system.cpu1.itb.hits 5703436 # DTB hits -system.cpu1.itb.misses 7020 # DTB misses -system.cpu1.itb.accesses 5710456 # DTB accesses -system.cpu1.numCycles 237056909 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5686521 # ITB inst accesses +system.cpu1.itb.hits 5679651 # DTB hits +system.cpu1.itb.misses 6870 # DTB misses +system.cpu1.itb.accesses 5686521 # DTB accesses +system.cpu1.numCycles 236844574 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14419718 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45234990 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7323132 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4441940 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9947853 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2287798 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 84999 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 49482147 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1272 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1896 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 44871 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1235484 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 189 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5701379 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 352457 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3064 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76794959 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.726229 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.078871 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14466322 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45074741 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7300035 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4444668 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9928510 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2284755 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 83810 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 49428019 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1085 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1865 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 44064 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1232877 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5677454 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 353029 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3058 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76760101 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.724873 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.076516 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66855647 87.06% 87.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 632615 0.82% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 843009 1.10% 88.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1133482 1.48% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1002056 1.30% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 554704 0.72% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1272745 1.66% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 372184 0.48% 94.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4128517 5.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66839787 87.08% 87.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 628644 0.82% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 837705 1.09% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1128430 1.47% 90.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1025116 1.34% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 549692 0.72% 92.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1265677 1.65% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 371391 0.48% 94.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4113659 5.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76794959 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030892 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.190819 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15530724 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 50222847 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8895356 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 650267 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1493551 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 963840 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85500 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53154493 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286161 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1493551 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16374919 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19306160 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27715779 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8656578 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3245827 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 50687701 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 339 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 605911 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2002092 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 648 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53113804 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 234485879 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 214384735 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5365 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39540919 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13572884 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 579809 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 536931 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6499660 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9772559 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6360216 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 888468 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1099515 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47171321 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 962588 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 61070577 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91971 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9248404 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23463374 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 229936 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76794959 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.795242 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.505673 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76760101 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030822 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.190314 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15575790 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50164874 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8875530 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 651724 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1490012 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 958602 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85804 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53028773 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286820 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1490012 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16419373 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19259514 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27698423 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8639214 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3251470 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 50560580 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 221 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 607469 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2007282 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 572 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 52946210 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 233908561 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 213841042 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5698 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39345682 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13600527 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 580708 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 537933 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6505084 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9729570 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6369599 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 877361 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1114434 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47034811 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 984793 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60942495 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 91566 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9279731 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23349761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 250555 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76760101 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.793935 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.504235 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54534134 71.01% 71.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7328500 9.54% 80.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3483988 4.54% 85.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2874889 3.74% 88.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6131286 7.98% 96.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1377966 1.79% 98.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 776904 1.01% 99.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 225300 0.29% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 61992 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54532875 71.04% 71.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7326090 9.54% 80.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3469207 4.52% 85.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2884980 3.76% 88.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6118042 7.97% 96.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1370862 1.79% 98.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 772587 1.01% 99.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 222613 0.29% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 62845 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76794959 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76760101 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29712 0.67% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 3 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4180230 94.88% 95.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 195658 4.44% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29035 0.66% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 5 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4177111 94.84% 95.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 198082 4.50% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 12649 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28971083 47.44% 47.46% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46630 0.08% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 875 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26162080 42.84% 90.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5877234 9.62% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 13548 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28887832 47.40% 47.42% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46127 0.08% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 887 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26105748 42.84% 90.34% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5888317 9.66% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 61070577 # Type of FU issued -system.cpu1.iq.rate 0.257620 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4405603 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072140 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 203466895 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57390461 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42382296 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11528 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6422 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5160 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65457468 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6063 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 311906 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60942495 # Type of FU issued +system.cpu1.iq.rate 0.257310 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4404233 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072269 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 203173539 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57307144 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42269826 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12116 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6726 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5381 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65326800 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6380 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 306796 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1999074 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3048 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15122 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 750838 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1984154 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3003 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15089 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 749009 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17042744 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 332080 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17027364 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 331342 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1493551 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14864582 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 222698 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48241525 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96453 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9772559 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6360216 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 687199 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 48610 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4313 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15122 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 168053 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 134565 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 302618 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 60042253 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25845364 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1028324 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1490012 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14823463 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 222107 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48121220 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 96425 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9729570 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6369599 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 709638 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 48371 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4239 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15089 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 167591 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133565 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 301156 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59912848 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25789830 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1029647 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 107616 # number of nop insts executed -system.cpu1.iew.exec_refs 31671376 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5872062 # Number of branches executed -system.cpu1.iew.exec_stores 5826012 # Number of stores executed -system.cpu1.iew.exec_rate 0.253282 # Inst execution rate -system.cpu1.iew.wb_sent 59578158 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42387456 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23643387 # num instructions producing a value -system.cpu1.iew.wb_consumers 43005248 # num instructions consuming a value +system.cpu1.iew.exec_nop 101616 # number of nop insts executed +system.cpu1.iew.exec_refs 31626536 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5854246 # Number of branches executed +system.cpu1.iew.exec_stores 5836706 # Number of stores executed +system.cpu1.iew.exec_rate 0.252963 # Inst execution rate +system.cpu1.iew.wb_sent 59450905 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42275207 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23556720 # num instructions producing a value +system.cpu1.iew.wb_consumers 42880647 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178807 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.549779 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178493 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.549356 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9166908 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 732652 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 262014 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 75301408 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.513681 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.486972 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9147109 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 734238 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 260548 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 75270089 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.511960 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.483838 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60995111 81.00% 81.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7470337 9.92% 90.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1928698 2.56% 93.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1074141 1.43% 94.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 820415 1.09% 96.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 494186 0.66% 96.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 699344 0.93% 97.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 371316 0.49% 98.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1447860 1.92% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60996835 81.04% 81.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7463530 9.92% 90.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1923766 2.56% 93.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1066165 1.42% 94.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 822611 1.09% 96.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 493470 0.66% 96.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 696092 0.92% 97.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 369554 0.49% 98.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1438066 1.91% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 75301408 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30565527 # Number of instructions committed -system.cpu1.commit.committedOps 38680902 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 75270089 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 30381625 # Number of instructions committed +system.cpu1.commit.committedOps 38535309 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13382863 # Number of memory references committed -system.cpu1.commit.loads 7773485 # Number of loads committed -system.cpu1.commit.membars 194338 # Number of memory barriers committed -system.cpu1.commit.branches 5145142 # Number of branches committed -system.cpu1.commit.fp_insts 5126 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34406663 # Number of committed integer instructions. -system.cpu1.commit.function_calls 483721 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1447860 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13366006 # Number of memory references committed +system.cpu1.commit.loads 7745416 # Number of loads committed +system.cpu1.commit.membars 193947 # Number of memory barriers committed +system.cpu1.commit.branches 5114433 # Number of branches committed +system.cpu1.commit.fp_insts 5338 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 34292499 # Number of committed integer instructions. +system.cpu1.commit.function_calls 482077 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 25125071 65.20% 65.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 43345 0.11% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 887 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 7745416 20.10% 85.41% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 5620590 14.59% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::total 38535309 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1438066 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120827478 # The number of ROB reads -system.cpu1.rob.rob_writes 97232532 # The number of ROB writes -system.cpu1.timesIdled 865086 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 160261950 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2316983227 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 30492768 # Number of Instructions Simulated -system.cpu1.committedOps 38608143 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 30492768 # Number of Instructions Simulated -system.cpu1.cpi 7.774201 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.774201 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.128631 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.128631 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 272500909 # number of integer regfile reads -system.cpu1.int_regfile_writes 43779735 # number of integer regfile writes -system.cpu1.fp_regfile_reads 45015 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42294 # number of floating regfile writes -system.cpu1.misc_regfile_reads 133085319 # number of misc regfile reads -system.cpu1.misc_regfile_writes 592959 # number of misc regfile writes +system.cpu1.rob.rob_reads 120626402 # The number of ROB reads +system.cpu1.rob.rob_writes 96898257 # The number of ROB writes +system.cpu1.timesIdled 866184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 160084473 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2317121408 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 30313431 # Number of Instructions Simulated +system.cpu1.committedOps 38467115 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 30313431 # Number of Instructions Simulated +system.cpu1.cpi 7.813189 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.813189 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.127989 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.127989 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 271901021 # number of integer regfile reads +system.cpu1.int_regfile_writes 43646883 # number of integer regfile writes +system.cpu1.fp_regfile_reads 45279 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42402 # number of floating regfile writes +system.cpu1.misc_regfile_reads 133121444 # number of misc regfile reads +system.cpu1.misc_regfile_writes 593543 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2082,17 +2105,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736889440801 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736889440801 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736889440801 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736889440801 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1734475259291 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1734475259291 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83061 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83062 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |