diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | 3291 |
1 files changed, 1641 insertions, 1650 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 1abf69682..c58b97d9e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,150 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.548434 # Number of seconds simulated -sim_ticks 2548433543500 # Number of ticks simulated -final_tick 2548433543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.548515 # Number of seconds simulated +sim_ticks 2548515380000 # Number of ticks simulated +final_tick 2548515380000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62524 # Simulator instruction rate (inst/s) -host_op_rate 80452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2641694597 # Simulator tick rate (ticks/s) -host_mem_usage 403600 # Number of bytes of host memory used -host_seconds 964.70 # Real time elapsed on the host -sim_insts 60316814 # Number of instructions simulated -sim_ops 77611972 # Number of ops (including micro ops) simulated +host_inst_rate 61977 # Simulator instruction rate (inst/s) +host_op_rate 79748 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2618667230 # Simulator tick rate (ticks/s) +host_mem_usage 403588 # Number of bytes of host memory used +host_seconds 973.21 # Real time elapsed on the host +sim_insts 60316341 # Number of instructions simulated +sim_ops 77611368 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1216 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 441408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4859600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 357888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4231256 # Number of bytes read from this memory -system.physmem.bytes_read::total 131003368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 441408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 357888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799296 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1678512 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1337588 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799652 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 440128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4850064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 360448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4242200 # Number of bytes read from this memory +system.physmem.bytes_read::total 131005928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 440128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 360448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785088 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1679112 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1336988 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801188 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 19 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 75965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5592 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 66119 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293431 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 419628 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 334397 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47523518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 452 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 6877 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 75816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5632 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 66290 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293471 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59142 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 419778 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 334247 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813167 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47521992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 477 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 173208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1906897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 140435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1660336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51405448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 173208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 140435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 658645 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 524867 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2668169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47523518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 172700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1903094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 141435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1664577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51404802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 172700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 141435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1485213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 658859 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 524614 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2668686 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1485213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47521992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 173208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2565541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 140435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2185203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54073617 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293431 # Total number of read requests seen -system.physmem.writeReqs 813143 # Total number of write requests seen -system.physmem.cpureqs 218375 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978779584 # Total number of bytes read from memory -system.physmem.bytesWritten 52041152 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131003368 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799652 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 955869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955530 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 955877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 955758 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955993 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 955787 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955113 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956214 # Track reads on a per bank basis +system.physmem.bw_total::cpu0.inst 172700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2561953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 141435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2189191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54073488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293471 # Total number of read requests seen +system.physmem.writeReqs 813167 # Total number of write requests seen +system.physmem.cpureqs 218464 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978782144 # Total number of bytes read from memory +system.physmem.bytesWritten 52042688 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131005928 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6801188 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4709 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 955865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955532 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 955892 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 955763 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955998 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 955786 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955940 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955511 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955116 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956216 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 955973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956070 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955978 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 48908 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51082 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51006 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51266 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51202 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51317 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51099 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50759 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50417 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50974 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51268 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51122 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 956077 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955981 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49128 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48906 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50979 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51091 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51008 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51270 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51265 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51204 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51310 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51097 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50416 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51359 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51272 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51123 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32387 # Number of times wr buffer was full causing retry -system.physmem.totGap 2548432371500 # Total gap between requests +system.physmem.numWrRetry 32396 # Number of times wr buffer was full causing retry +system.physmem.totGap 2548513467000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 42 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154573 # Categorize read packet sizes +system.physmem.readPktSize::6 154613 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754025 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59118 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1060830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 986831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 991569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3738549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2806537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2806300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2762834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 14911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 27618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 40328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 3599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 3593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59142 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1060849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 987246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 977477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3738495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2806386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2806166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2776833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 14905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,222 +156,215 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2878 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32473 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 32457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32415 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40040 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 25744.741658 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2072.132686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32880.697508 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 6923 17.29% 17.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 3475 8.68% 25.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2293 5.73% 31.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 1778 4.44% 36.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1271 3.17% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1070 2.67% 41.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 793 1.98% 43.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 869 2.17% 46.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 551 1.38% 47.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 489 1.22% 48.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 420 1.05% 49.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 393 0.98% 50.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 261 0.65% 51.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 255 0.64% 52.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 183 0.46% 52.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 282 0.70% 53.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 123 0.31% 53.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 156 0.39% 53.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 102 0.25% 54.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 126 0.31% 54.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 80 0.20% 54.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 383 0.96% 55.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 613 1.53% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 451 1.13% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 81 0.20% 58.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 160 0.40% 58.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 53 0.13% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 109 0.27% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 41 0.10% 59.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 74 0.18% 59.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 65 0.16% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 23 0.06% 59.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 42 0.10% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 15 0.04% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 29 0.07% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 18 0.04% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 27 0.07% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 12 0.03% 60.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 7 0.02% 60.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 22 0.05% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 8 0.02% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 11 0.03% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 11 0.03% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 16 0.04% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 19 0.05% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 8 0.02% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 9 0.02% 60.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 8 0.02% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 6 0.01% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 6 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 9 0.02% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 4 0.01% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 9 0.02% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 6 0.01% 60.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 4 0.01% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 3 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 10 0.02% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 40 0.10% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 3 0.01% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 5 0.01% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 4 0.01% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 4 0.01% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 3 0.01% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 2 0.00% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 3 0.01% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 3 0.01% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 2 0.00% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 5 0.01% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 1 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 2 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 4 0.01% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 3 0.01% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5087 2 0.00% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 5 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 6 0.01% 61.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 1 0.00% 61.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 2 0.00% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 5 0.01% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 7 0.02% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5791 1 0.00% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5855 1 0.00% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 2 0.00% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 1 0.00% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 6 0.01% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 1 0.00% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 2 0.00% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6367 1 0.00% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 3 0.01% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 1 0.00% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 5 0.01% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 2 0.00% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 2 0.00% 61.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 2 0.00% 61.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 20 0.05% 61.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 2 0.00% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 1 0.00% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 2 0.00% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7135 3 0.01% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 2 0.00% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 1 0.00% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 9 0.02% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7519 1 0.00% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 4 0.01% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 7 0.02% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 3 0.01% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 3 0.01% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 4 0.01% 61.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 1 0.00% 61.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 7 0.02% 61.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 2 0.00% 61.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 309 0.77% 62.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 1 0.00% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9695 1 0.00% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 17 0.04% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 1 0.00% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12831 1 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14239 1 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16927 1 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18975 1 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21343 1 0.00% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 1 0.00% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26399 1 0.00% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 1 0.00% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29983 1 0.00% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30239 1 0.00% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30623 1 0.00% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32031 1 0.00% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32287 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32799 2 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 1 0.00% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 6 0.01% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35359 1 0.00% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42944-42975 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45663 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58112-58143 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58624-58655 1 0.00% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61120-61151 1 0.00% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14762 36.87% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::123712-123743 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130048-130079 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130944-130975 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.wrQLenPdf::30 32442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32421 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40074 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 25722.964516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2062.503898 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32877.713086 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 7020 17.52% 17.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3450 8.61% 26.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2302 5.74% 31.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1762 4.40% 36.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1221 3.05% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1083 2.70% 42.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 782 1.95% 43.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 826 2.06% 46.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 552 1.38% 47.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 527 1.32% 48.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 441 1.10% 49.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 399 1.00% 50.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 278 0.69% 51.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 274 0.68% 52.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 181 0.45% 52.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 260 0.65% 53.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 121 0.30% 53.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 146 0.36% 53.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 103 0.26% 54.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 108 0.27% 54.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 77 0.19% 54.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 372 0.93% 55.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 611 1.52% 57.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 461 1.15% 58.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 86 0.21% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 174 0.43% 58.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 54 0.13% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 96 0.24% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 48 0.12% 59.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 68 0.17% 59.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 67 0.17% 59.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 19 0.05% 59.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 52 0.13% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 17 0.04% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 39 0.10% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 17 0.04% 60.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 35 0.09% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 6 0.01% 60.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 5 0.01% 60.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 15 0.04% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 12 0.03% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 19 0.05% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 10 0.02% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 19 0.05% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 14 0.03% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 5 0.01% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 6 0.01% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 5 0.01% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 3 0.01% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 12 0.03% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 10 0.02% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 3 0.01% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 8 0.02% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 7 0.02% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 6 0.01% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 1 0.00% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 7 0.02% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 35 0.09% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 5 0.01% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 2 0.00% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 3 0.01% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 7 0.02% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 4 0.01% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 5 0.01% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 1 0.00% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 7 0.02% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 1 0.00% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 7 0.02% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 3 0.01% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 3 0.01% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 5 0.01% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 4 0.01% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 2 0.00% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 2 0.00% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 5 0.01% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 4 0.01% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 5 0.01% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5983 1 0.00% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 1 0.00% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 2 0.00% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 4 0.01% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 3 0.01% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6367 2 0.00% 61.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 5 0.01% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 3 0.01% 61.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 4 0.01% 61.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 1 0.00% 61.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 21 0.05% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 2 0.00% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 4 0.01% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7135 2 0.00% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 3 0.01% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7327 5 0.01% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 2 0.00% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 3 0.01% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7647 1 0.00% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 6 0.01% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7775 1 0.00% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 7 0.02% 61.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 61.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 7 0.02% 61.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 1 0.00% 61.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 9 0.02% 61.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 3 0.01% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 305 0.76% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10143 1 0.00% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 17 0.04% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14111 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14239 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16735 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21023 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24799 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26143 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 1 0.00% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27935 2 0.00% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 1 0.00% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30239 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30431 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 5 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34847 1 0.00% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35167 1 0.00% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37663 1 0.00% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39455 1 0.00% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43167 1 0.00% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45663 1 0.00% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51487 1 0.00% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56832-56863 1 0.00% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58399 1 0.00% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60864-60895 1 0.00% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14763 36.84% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::126336-126367 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130496-130527 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131008-131039 1 0.00% 99.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::131072-131103 346 0.86% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132127 4 0.01% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::161280-161311 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::168384-168415 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::187392-187423 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::161792-161823 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::168960-168991 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::196608-196639 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40040 # Bytes accessed per row activation -system.physmem.totQLat 308881805250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 400754322750 # Sum of mem lat for all requests -system.physmem.totBusLat 76467100000 # Total cycles spent in databus access -system.physmem.totBankLat 15405417500 # Total cycles spent in bank access -system.physmem.avgQLat 20197.04 # Average queueing delay per request -system.physmem.avgBankLat 1007.32 # Average bank access latency per request +system.physmem.bytesPerActivate::total 40074 # Bytes accessed per row activation +system.physmem.totQLat 305431681500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 397314004000 # Sum of mem lat for all requests +system.physmem.totBusLat 76467280000 # Total cycles spent in databus access +system.physmem.totBankLat 15415042500 # Total cycles spent in bank access +system.physmem.avgQLat 19971.40 # Average queueing delay per request +system.physmem.avgBankLat 1007.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26204.36 # Average memory access latency -system.physmem.avgRdBW 384.07 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25979.35 # Average memory access latency +system.physmem.avgRdBW 384.06 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.41 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.40 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.16 # Data bus utilization in percentage system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 1.10 # Average write queue length over time -system.physmem.readRowHits 15267875 # Number of row buffer hits during reads -system.physmem.writeRowHits 798648 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.11 # Average write queue length over time +system.physmem.readRowHits 15267858 # Number of row buffer hits during reads +system.physmem.writeRowHits 798688 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.22 # Row buffer hit rate for writes -system.physmem.avgGap 158223.12 # Average gap between requests +system.physmem.avgGap 158227.53 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -384,289 +377,291 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55014580 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346067 # Transaction distribution -system.membus.trans_dist::ReadResp 16346070 # Transaction distribution +system.membus.throughput 55014417 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346104 # Transaction distribution +system.membus.trans_dist::ReadResp 16346107 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59118 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4682 # Transaction distribution +system.membus.trans_dist::Writeback 59142 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4707 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4684 # Transaction distribution -system.membus.trans_dist::ReadExReq 131411 # Transaction distribution -system.membus.trans_dist::ReadExResp 131411 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4709 # Transaction distribution +system.membus.trans_dist::ReadExReq 131412 # Transaction distribution +system.membus.trans_dist::ReadExResp 131412 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382954 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885920 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272668 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382954 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32163398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32163552 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550150 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550300 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390325 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16692492 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696588 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19090473 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19094561 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390325 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 137803020 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 137807116 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140201001 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140201001 # Total data (bytes) +system.membus.tot_pkt_size::total 140205089 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140205089 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1492522500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1476111500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17540815750 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 17555240750 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3583500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3581500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4705924038 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4707147287 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34177393245 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34172276993 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.replacements 64346 # number of replacements -system.l2c.tagsinuse 51424.069961 # Cycle average of tags in use -system.l2c.total_refs 1905385 # Total number of references to valid blocks. -system.l2c.sampled_refs 129735 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.686746 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2511358439500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36974.185132 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 11.366489 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000367 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4621.370879 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3355.179290 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 15.725461 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3578.652286 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2867.590058 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.564181 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000173 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.070517 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.051196 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000240 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.054606 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.043756 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784669 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 33086 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6984 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 499528 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 184262 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30366 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6676 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 472129 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 203355 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1436386 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608398 # number of Writeback hits -system.l2c.Writeback_hits::total 608398 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 21 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 15 # 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average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60817.646245 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64195.633188 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61853.395911 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.303781 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.683527 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56143.257661 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55885.895105 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56022.680137 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56090.553308 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56116.480736 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56102.719595 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -861,49 +852,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58505331 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2677704 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2677706 # Transaction distribution +system.toL2Bus.throughput 58503668 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677420 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677422 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608398 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2960 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246173 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246173 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608377 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2971 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2984 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969441 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798176 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37507 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149666 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7954790 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62986112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85598825 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253968 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 148893553 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148893553 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 203396 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4965063678 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969614 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798105 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37248 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149421 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7954388 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62990656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85594465 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54388 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253832 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 148893341 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148893341 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 204156 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4964785971 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4434793437 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4437766959 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4469014832 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4499076262 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23886909 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23705637 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86662497 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86451768 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48461480 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322135 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322135 # Transaction distribution +system.iobus.throughput 48459921 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322133 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322133 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution system.iobus.trans_dist::WriteResp 8160 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -925,11 +916,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -952,9 +943,9 @@ system.iobus.pkt_count::system.realview.aaci_fake.pio 16 system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660590 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660586 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -976,11 +967,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390325 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1003,11 +994,11 @@ system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500861 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500861 # Total data (bytes) +system.iobus.tot_pkt_size::total 123500853 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500853 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1053,684 +1044,684 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374798000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374794000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu0.branchPred.lookups 7472736 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5963732 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 379354 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4914816 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4037140 # Number of BTB hits +system.iobus.respLayer1.occupancy 41501177007 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu0.branchPred.lookups 7460849 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5960235 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 378283 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4914778 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4045811 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 82.142241 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 698266 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 38240 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 82.319303 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 696591 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 38344 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25723416 # DTB read hits -system.cpu0.dtb.read_misses 39440 # DTB read misses -system.cpu0.dtb.write_hits 6006462 # DTB write hits -system.cpu0.dtb.write_misses 9528 # DTB write misses +system.cpu0.dtb.read_hits 25704058 # DTB read hits +system.cpu0.dtb.read_misses 39030 # DTB read misses +system.cpu0.dtb.write_hits 5997479 # DTB write hits +system.cpu0.dtb.write_misses 9591 # DTB write misses system.cpu0.dtb.flush_tlb 258 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5597 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1333 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5605 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 246 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25762856 # DTB read accesses -system.cpu0.dtb.write_accesses 6015990 # DTB write accesses +system.cpu0.dtb.perms_faults 688 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25743088 # DTB read accesses +system.cpu0.dtb.write_accesses 6007070 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31729878 # DTB hits -system.cpu0.dtb.misses 48968 # DTB misses -system.cpu0.dtb.accesses 31778846 # DTB accesses -system.cpu0.itb.inst_hits 6261683 # ITB inst hits -system.cpu0.itb.inst_misses 7235 # ITB inst misses +system.cpu0.dtb.hits 31701537 # DTB hits +system.cpu0.dtb.misses 48621 # DTB misses +system.cpu0.dtb.accesses 31750158 # DTB accesses +system.cpu0.itb.inst_hits 6247488 # ITB inst hits +system.cpu0.itb.inst_misses 7199 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 258 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1762 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1719 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6268918 # ITB inst accesses -system.cpu0.itb.hits 6261683 # DTB hits -system.cpu0.itb.misses 7235 # DTB misses -system.cpu0.itb.accesses 6268918 # DTB accesses -system.cpu0.numCycles 237920120 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6254687 # ITB inst accesses +system.cpu0.itb.hits 6247488 # DTB hits +system.cpu0.itb.misses 7199 # DTB misses +system.cpu0.itb.accesses 6254687 # DTB accesses +system.cpu0.numCycles 237974378 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15748746 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 49352173 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7472736 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4735406 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10833707 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2792544 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 84623 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 47712542 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1287 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1922 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 50902 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1299242 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6259599 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 422561 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2976 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77655749 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.785029 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.152550 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15699723 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 49234228 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7460849 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4742402 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10819268 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2791638 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 83518 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 47679796 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1910 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 50382 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1297285 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 371 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6245426 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 421717 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2971 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77555768 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.784584 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.151481 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 66829888 86.06% 86.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 668416 0.86% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 858180 1.11% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1304413 1.68% 89.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1126910 1.45% 91.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 549966 0.71% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1380247 1.78% 93.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 376750 0.49% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4560979 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 66744115 86.06% 86.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 668305 0.86% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 854486 1.10% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1301033 1.68% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1140084 1.47% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 550475 0.71% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1373308 1.77% 93.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 375655 0.48% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4548307 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77655749 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031409 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.207432 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16823690 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 48684179 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9802416 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 509733 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1833567 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1006000 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91487 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 57560969 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 307020 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1833567 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17765952 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 19652864 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 25831801 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9294758 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3274685 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54590229 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7255 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 552363 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2204905 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 211 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 56896376 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 249980910 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 249932531 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48379 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39701074 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 17195302 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 410578 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 363043 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6638624 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10379903 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6907552 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1064074 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1362159 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50052762 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 969661 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62837234 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92382 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11367794 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 29332821 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 250599 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77655749 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.809177 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.518047 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77555768 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031351 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.206889 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16771569 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 48649935 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9795097 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 503008 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1834030 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1000504 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90828 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 57451762 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 304997 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1834030 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17711945 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 19691518 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 25851696 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9283653 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3180864 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54475085 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7298 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 545691 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2120831 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 197 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 56755313 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 249403500 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 249355386 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48114 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39528436 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 17226877 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 410327 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 362870 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6606046 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10343576 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6897280 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1045135 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1291149 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49940914 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 982735 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62750040 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92397 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11407526 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 29277622 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 263780 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77555768 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.809096 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.520917 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55074638 70.92% 70.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6993608 9.01% 79.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3678555 4.74% 84.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3117743 4.01% 88.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6240678 8.04% 96.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1479911 1.91% 98.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 787330 1.01% 99.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 219248 0.28% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 64038 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55086998 71.03% 71.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6938242 8.95% 79.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3598420 4.64% 84.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3124608 4.03% 88.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6233139 8.04% 96.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1485765 1.92% 98.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 804564 1.04% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 219887 0.28% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 64145 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77655749 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77555768 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 30466 0.70% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4143838 94.53% 95.23% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 209138 4.77% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 31748 0.72% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4146155 94.50% 95.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 209698 4.78% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 167413 0.27% 0.27% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29876413 47.55% 47.81% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48260 0.08% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 15 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 946 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26437550 42.07% 89.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6306621 10.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 168420 0.27% 0.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29819854 47.52% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48156 0.08% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 937 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26415371 42.10% 89.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6297270 10.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62837234 # Type of FU issued -system.cpu0.iq.rate 0.264111 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4383444 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.069759 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 207842642 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 62399132 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43895220 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12180 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6627 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5522 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67046851 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6414 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 320881 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62750040 # Type of FU issued +system.cpu0.iq.rate 0.263684 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4387604 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.069922 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 207571986 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 62340159 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43794455 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12289 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6579 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5482 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66962707 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6517 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 317894 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2431860 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3521 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16133 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 922699 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2428904 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3600 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16156 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 921017 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 16864632 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 486760 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 16878789 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 486624 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1833567 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14994749 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 240124 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 51146104 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107104 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10379903 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6907552 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 682007 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 55746 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3189 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16133 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 183360 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 147814 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 331174 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61530066 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26055329 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1307168 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1834030 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15021196 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 239984 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 51041656 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 102587 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10343576 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6897280 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 695313 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 54984 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 10683 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16156 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 184294 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 146657 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 330951 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61443864 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26034265 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1306176 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 123681 # number of nop insts executed -system.cpu0.iew.exec_refs 32305514 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5821167 # Number of branches executed -system.cpu0.iew.exec_stores 6250185 # Number of stores executed -system.cpu0.iew.exec_rate 0.258616 # Inst execution rate -system.cpu0.iew.wb_sent 60920832 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43900742 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23943541 # num instructions producing a value -system.cpu0.iew.wb_consumers 43567103 # num instructions consuming a value +system.cpu0.iew.exec_nop 118007 # number of nop insts executed +system.cpu0.iew.exec_refs 32275135 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5809455 # Number of branches executed +system.cpu0.iew.exec_stores 6240870 # Number of stores executed +system.cpu0.iew.exec_rate 0.258195 # Inst execution rate +system.cpu0.iew.wb_sent 60834498 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43799937 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23902926 # num instructions producing a value +system.cpu0.iew.wb_consumers 43468500 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184519 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.549578 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184053 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.549891 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11253313 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 719062 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 289317 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75822182 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.520093 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.499421 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11258567 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 718955 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 288860 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75721738 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.518964 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.500316 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61770131 81.47% 81.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6789372 8.95% 90.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2077521 2.74% 93.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1107875 1.46% 94.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1001712 1.32% 95.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 557795 0.74% 96.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 684831 0.90% 97.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 401810 0.53% 98.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1431135 1.89% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61785849 81.60% 81.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6716034 8.87% 90.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2031673 2.68% 93.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1100696 1.45% 94.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 996789 1.32% 95.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 567209 0.75% 96.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 697121 0.92% 97.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 401495 0.53% 98.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1424872 1.88% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75822182 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30629038 # Number of instructions committed -system.cpu0.commit.committedOps 39434598 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75721738 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30484303 # Number of instructions committed +system.cpu0.commit.committedOps 39296836 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13932896 # Number of memory references committed -system.cpu0.commit.loads 7948043 # Number of loads committed -system.cpu0.commit.membars 201908 # Number of memory barriers committed -system.cpu0.commit.branches 4992421 # Number of branches committed -system.cpu0.commit.fp_insts 5469 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34986832 # Number of committed integer instructions. -system.cpu0.commit.function_calls 490811 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1431135 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13890935 # Number of memory references committed +system.cpu0.commit.loads 7914672 # Number of loads committed +system.cpu0.commit.membars 201566 # Number of memory barriers committed +system.cpu0.commit.branches 4969836 # Number of branches committed +system.cpu0.commit.fp_insts 5449 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34871152 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489123 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1424872 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124149615 # The number of ROB reads -system.cpu0.rob.rob_writes 103265708 # The number of ROB writes -system.cpu0.timesIdled 892080 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 160264371 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2282472691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 30545540 # Number of Instructions Simulated -system.cpu0.committedOps 39351100 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 30545540 # Number of Instructions Simulated -system.cpu0.cpi 7.789030 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.789030 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.128386 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.128386 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 279175646 # number of integer regfile reads -system.cpu0.int_regfile_writes 45166448 # number of integer regfile writes -system.cpu0.fp_regfile_reads 23007 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19790 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15439802 # number of misc regfile reads -system.cpu0.misc_regfile_writes 404480 # number of misc regfile writes -system.cpu0.icache.replacements 984632 # number of replacements -system.cpu0.icache.tagsinuse 511.564307 # Cycle average of tags in use -system.cpu0.icache.total_refs 10914069 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 985144 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.078653 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6937099000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 153.323923 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 358.240384 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.299461 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.699688 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999149 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5710872 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5203197 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10914069 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5710872 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5203197 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10914069 # 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number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7029593986 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14558557970 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7528963984 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7029593986 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14558557970 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7528963984 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7029593986 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14558557970 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6259479 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5721049 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11980528 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6259479 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5721049 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11980528 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6259479 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5721049 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11980528 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.087644 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.090517 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.089016 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.087644 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.090517 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.089016 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.087644 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.090517 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.089016 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13723.784028 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13574.523196 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13651.305835 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13651.305835 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13651.305835 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 7371 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 409 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.022005 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.rob.rob_reads 123917155 # The number of ROB reads +system.cpu0.rob.rob_writes 103001078 # The number of ROB writes +system.cpu0.timesIdled 891630 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 160418610 # 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number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7505000228 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 7078718225 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14583718453 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6245307 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5737748 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11983055 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6245307 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5737748 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11983055 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6245307 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5737748 # 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mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13896.184228 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13279.234055 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13573.459198 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43991.095531 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42494.536818 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43275.068377 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12463.001758 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11481.453718 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11985.354775 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 109001574183 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 106248217570 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215249791753 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024652 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028587 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026577 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025073 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023607 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051447 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043646 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047334 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000060 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000046 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025659 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025659 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13865.405311 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13318.627137 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13577.694977 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43750.757830 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42789.411798 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43292.904137 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12465.426541 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11476.628417 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11984.657122 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14642.571429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12961.384615 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1745,330 +1736,330 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7176614 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5748558 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 346164 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4712171 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3815419 # Number of BTB hits +system.cpu1.branchPred.lookups 7195832 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5758794 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 347995 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4705708 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3816103 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 80.969451 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 703194 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35756 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 81.095193 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 703176 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35899 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25652921 # DTB read hits -system.cpu1.dtb.read_misses 36442 # DTB read misses -system.cpu1.dtb.write_hits 5708219 # DTB write hits -system.cpu1.dtb.write_misses 9483 # DTB write misses +system.cpu1.dtb.read_hits 25676963 # DTB read hits +system.cpu1.dtb.read_misses 36626 # DTB read misses +system.cpu1.dtb.write_hits 5717501 # DTB write hits +system.cpu1.dtb.write_misses 9454 # DTB write misses system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5550 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1291 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1965 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 574 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25689363 # DTB read accesses -system.cpu1.dtb.write_accesses 5717702 # DTB write accesses +system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25713589 # DTB read accesses +system.cpu1.dtb.write_accesses 5726955 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31361140 # DTB hits -system.cpu1.dtb.misses 45925 # DTB misses -system.cpu1.dtb.accesses 31407065 # DTB accesses -system.cpu1.itb.inst_hits 5722854 # ITB inst hits -system.cpu1.itb.inst_misses 6790 # ITB inst misses +system.cpu1.dtb.hits 31394464 # DTB hits +system.cpu1.dtb.misses 46080 # DTB misses +system.cpu1.dtb.accesses 31440544 # DTB accesses +system.cpu1.itb.inst_hits 5739661 # ITB inst hits +system.cpu1.itb.inst_misses 6710 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2604 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2611 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1206 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1312 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5729644 # ITB inst accesses -system.cpu1.itb.hits 5722854 # DTB hits -system.cpu1.itb.misses 6790 # DTB misses -system.cpu1.itb.accesses 5729644 # DTB accesses -system.cpu1.numCycles 238719781 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5746371 # ITB inst accesses +system.cpu1.itb.hits 5739661 # DTB hits +system.cpu1.itb.misses 6710 # DTB misses +system.cpu1.itb.accesses 5746371 # DTB accesses +system.cpu1.numCycles 238752144 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14663434 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45610232 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7176614 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4518613 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10115214 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2414166 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 79241 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 48437095 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1874 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 41135 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1402245 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 183 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5721051 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 343472 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3001 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76398004 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.741963 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.097795 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14725732 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45766952 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7195832 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4519279 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10135681 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2420409 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 79807 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 48403648 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1933 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 42395 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1408034 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5737749 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 344300 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2901 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76459821 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.743283 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.100006 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66290194 86.77% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 639384 0.84% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 858446 1.12% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1141205 1.49% 90.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1054322 1.38% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 565766 0.74% 92.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1279029 1.67% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 372986 0.49% 94.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4196672 5.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66331645 86.75% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 641052 0.84% 87.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 862069 1.13% 88.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1143637 1.50% 90.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1042629 1.36% 91.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 566145 0.74% 92.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1286339 1.68% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 374523 0.49% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4211782 5.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76398004 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030063 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.191062 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15662136 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 49485106 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9174118 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 502006 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1572389 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 964164 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86078 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53732667 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 284993 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1572389 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16517156 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19371694 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27019391 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8745759 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3169437 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51316953 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13347 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 558580 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2084092 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 533 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53384018 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 234291448 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 234248948 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42500 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38701877 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14682140 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 422621 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 375998 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6399704 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9755366 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6540913 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 899316 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1131463 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47221133 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1016692 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 61223636 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 83704 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9695690 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24360360 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 252773 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76398004 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.801377 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.509980 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76459821 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030139 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.191692 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15725454 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49459208 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9192415 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 503929 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1576672 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 971007 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86673 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53874532 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286668 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1576672 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16583861 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19404823 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27005764 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8762969 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3123666 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51462507 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13354 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 564319 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2029977 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 529 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53559967 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 234998901 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 234956394 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42507 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38873752 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14686214 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 422468 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 375757 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6418869 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9803560 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6552959 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 903342 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1157992 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47368560 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1003626 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 61323847 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 88809 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9695135 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24547753 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 239591 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76459821 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.802040 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.511450 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54279894 71.05% 71.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6964982 9.12% 80.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3572105 4.68% 84.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2997144 3.92% 88.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6191464 8.10% 96.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1336331 1.75% 98.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 781274 1.02% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 210623 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 64187 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54334795 71.06% 71.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6963817 9.11% 80.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3541064 4.63% 84.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3011943 3.94% 88.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6202034 8.11% 96.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1339759 1.75% 98.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 792493 1.04% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 211144 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 62772 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76398004 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76459821 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28625 0.64% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4232850 94.77% 95.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 204916 4.59% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 28001 0.63% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4231917 94.82% 95.44% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 203383 4.56% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 196253 0.32% 0.32% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28636645 46.77% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45275 0.07% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1166 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26314487 42.98% 90.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6029771 9.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 195246 0.32% 0.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28699765 46.80% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45365 0.07% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1174 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26341683 42.96% 90.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6040595 9.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 61223636 # Type of FU issued -system.cpu1.iq.rate 0.256467 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4466394 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072952 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 203430011 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57942058 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42278659 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11099 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5883 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4799 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65487820 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5957 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 306320 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 61323847 # Type of FU issued +system.cpu1.iq.rate 0.256852 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4463304 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072783 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 203694277 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58075857 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42386346 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11257 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5873 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65585843 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6062 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 307143 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2045827 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3210 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14938 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 792022 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2060794 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3248 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14926 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 795522 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17238980 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 391927 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17225652 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 391932 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1572389 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14646185 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 228906 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48337037 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 102627 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9755366 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6540913 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 729665 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50173 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3845 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14938 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 169845 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 132330 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 302175 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 60177661 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 26008514 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1045975 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1576672 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14666749 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 228879 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48476685 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98660 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9803560 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6552959 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 716609 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50437 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 9701 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14926 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 170356 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133051 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 303407 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 60276255 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 26034557 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1047592 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 99212 # number of nop insts executed -system.cpu1.iew.exec_refs 31985233 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5705434 # Number of branches executed -system.cpu1.iew.exec_stores 5976719 # Number of stores executed -system.cpu1.iew.exec_rate 0.252085 # Inst execution rate -system.cpu1.iew.wb_sent 59667880 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42283458 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23216135 # num instructions producing a value -system.cpu1.iew.wb_consumers 42895102 # num instructions consuming a value +system.cpu1.iew.exec_nop 104499 # number of nop insts executed +system.cpu1.iew.exec_refs 32021114 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5717498 # Number of branches executed +system.cpu1.iew.exec_stores 5986557 # Number of stores executed +system.cpu1.iew.exec_rate 0.252464 # Inst execution rate +system.cpu1.iew.wb_sent 59765334 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42391160 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23307297 # num instructions producing a value +system.cpu1.iew.wb_consumers 43055480 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.177126 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.541230 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.177553 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.541332 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9567940 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 763919 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 261423 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74825615 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.512228 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.487191 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9596314 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 764035 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 262671 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74883149 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.513666 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.490214 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 61056295 81.60% 81.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6800068 9.09% 90.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1929591 2.58% 93.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1057405 1.41% 94.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1013455 1.35% 96.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 520209 0.70% 96.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 685711 0.92% 97.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 375889 0.50% 98.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1386992 1.85% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61098286 81.59% 81.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6805438 9.09% 90.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1903916 2.54% 93.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1064936 1.42% 94.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1018174 1.36% 96.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 531111 0.71% 96.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 691593 0.92% 97.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 378534 0.51% 98.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1391161 1.86% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74825615 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29838157 # Number of instructions committed -system.cpu1.commit.committedOps 38327755 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74883149 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29982419 # Number of instructions committed +system.cpu1.commit.committedOps 38464913 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13458430 # Number of memory references committed -system.cpu1.commit.loads 7709539 # Number of loads committed -system.cpu1.commit.membars 201879 # Number of memory barriers committed -system.cpu1.commit.branches 4970440 # Number of branches committed -system.cpu1.commit.fp_insts 4743 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33879408 # Number of committed integer instructions. -system.cpu1.commit.function_calls 500692 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1386992 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13500203 # Number of memory references committed +system.cpu1.commit.loads 7742766 # Number of loads committed +system.cpu1.commit.membars 202217 # Number of memory barriers committed +system.cpu1.commit.branches 4992962 # Number of branches committed +system.cpu1.commit.fp_insts 4763 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33994528 # Number of committed integer instructions. +system.cpu1.commit.function_calls 502375 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1391161 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120414089 # The number of ROB reads -system.cpu1.rob.rob_writes 97409741 # The number of ROB writes -system.cpu1.timesIdled 885352 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 162321777 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2286481516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29771274 # Number of Instructions Simulated -system.cpu1.committedOps 38260872 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29771274 # Number of Instructions Simulated -system.cpu1.cpi 8.018460 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.018460 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124712 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124712 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 271859015 # number of integer regfile reads -system.cpu1.int_regfile_writes 43450852 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22226 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19958 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14811721 # number of misc regfile reads -system.cpu1.misc_regfile_writes 428358 # number of misc regfile writes -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.rob.rob_reads 120638730 # The number of ROB reads +system.cpu1.rob.rob_writes 97745041 # The number of ROB writes +system.cpu1.timesIdled 886317 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 162292323 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2286407630 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29911740 # Number of Instructions Simulated +system.cpu1.committedOps 38394234 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29911740 # Number of Instructions Simulated +system.cpu1.cpi 7.981888 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.981888 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.125284 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.125284 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 272364887 # number of integer regfile reads +system.cpu1.int_regfile_writes 43577017 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22187 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19914 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14848508 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429527 # number of misc regfile writes +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2077,17 +2068,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1456504103755 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1456504103755 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1453044953007 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1453044953007 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83064 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83067 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |