diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | 3417 |
1 files changed, 1726 insertions, 1691 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index b052ee538..3bffe858b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,142 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.804324 # Number of seconds simulated -sim_ticks 2804324203000 # Number of ticks simulated -final_tick 2804324203000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.814521 # Number of seconds simulated +sim_ticks 2814521286500 # Number of ticks simulated +final_tick 2814521286500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110825 # Simulator instruction rate (inst/s) -host_op_rate 134512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2657187313 # Simulator tick rate (ticks/s) -host_mem_usage 623780 # Number of bytes of host memory used -host_seconds 1055.37 # Real time elapsed on the host -sim_insts 116961789 # Number of instructions simulated -sim_ops 141959973 # Number of ops (including micro ops) simulated +host_inst_rate 106354 # Simulator instruction rate (inst/s) +host_op_rate 129085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2558515098 # Simulator tick rate (ticks/s) +host_mem_usage 570360 # Number of bytes of host memory used +host_seconds 1100.06 # Real time elapsed on the host +sim_insts 116996192 # Number of instructions simulated +sim_ops 142001364 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 4288 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 739200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5181280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 637568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4639684 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 746368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5095008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 4352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 629952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4708740 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11207460 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 739200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 637568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1376768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6111936 # Number of bytes written to this memory +system.physmem.bytes_read::total 11189732 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 746368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 629952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1376320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8426816 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 8447796 # Number of bytes written to this memory +system.physmem.bytes_written::total 8444340 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 67 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11550 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 81476 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 69 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 72496 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 80128 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 68 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9843 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 73575 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175636 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 95499 # Number of write requests responded to by this memory +system.physmem.num_reads::total 175359 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131669 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136104 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1529 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 136050 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1524 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 263593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1847604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 227352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1654475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3996492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 263593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 227352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 490945 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2179468 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 265185 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1810257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 223822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1673016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3975714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 265185 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 223822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 489007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2994049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6223 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 826700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3012418 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2179468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3000276 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2994049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1524 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 263593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1853850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 227352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1654478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 827043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7008910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175637 # Number of read requests accepted -system.physmem.writeReqs 136104 # Number of write requests accepted -system.physmem.readBursts 175637 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 136104 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11232064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue -system.physmem.bytesWritten 8461376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11207524 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8447796 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3870 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4652 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11117 # Per bank write bursts -system.physmem.perBankRdBursts::1 11147 # Per bank write bursts -system.physmem.perBankRdBursts::2 11719 # Per bank write bursts -system.physmem.perBankRdBursts::3 11225 # Per bank write bursts -system.physmem.perBankRdBursts::4 11363 # Per bank write bursts -system.physmem.perBankRdBursts::5 11390 # Per bank write bursts -system.physmem.perBankRdBursts::6 11955 # Per bank write bursts -system.physmem.perBankRdBursts::7 11820 # Per bank write bursts -system.physmem.perBankRdBursts::8 10213 # Per bank write bursts -system.physmem.perBankRdBursts::9 10442 # Per bank write bursts -system.physmem.perBankRdBursts::10 10593 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 265185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1816481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 223822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1673019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6975990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175360 # Number of read requests accepted +system.physmem.writeReqs 172246 # Number of write requests accepted +system.physmem.readBursts 175360 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 172246 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11215872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue +system.physmem.bytesWritten 10651968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11189796 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10760884 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5779 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4663 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11102 # Per bank write bursts +system.physmem.perBankRdBursts::1 11119 # Per bank write bursts +system.physmem.perBankRdBursts::2 11680 # Per bank write bursts +system.physmem.perBankRdBursts::3 11222 # Per bank write bursts +system.physmem.perBankRdBursts::4 11370 # Per bank write bursts +system.physmem.perBankRdBursts::5 11380 # Per bank write bursts +system.physmem.perBankRdBursts::6 11917 # Per bank write bursts +system.physmem.perBankRdBursts::7 11794 # Per bank write bursts +system.physmem.perBankRdBursts::8 10207 # Per bank write bursts +system.physmem.perBankRdBursts::9 10426 # Per bank write bursts +system.physmem.perBankRdBursts::10 10580 # Per bank write bursts system.physmem.perBankRdBursts::11 9765 # Per bank write bursts -system.physmem.perBankRdBursts::12 10406 # Per bank write bursts -system.physmem.perBankRdBursts::13 11413 # Per bank write bursts -system.physmem.perBankRdBursts::14 10638 # Per bank write bursts -system.physmem.perBankRdBursts::15 10295 # Per bank write bursts -system.physmem.perBankWrBursts::0 8316 # Per bank write bursts -system.physmem.perBankWrBursts::1 8444 # Per bank write bursts -system.physmem.perBankWrBursts::2 9040 # Per bank write bursts -system.physmem.perBankWrBursts::3 8545 # Per bank write bursts -system.physmem.perBankWrBursts::4 8340 # Per bank write bursts -system.physmem.perBankWrBursts::5 8537 # Per bank write bursts -system.physmem.perBankWrBursts::6 8974 # Per bank write bursts -system.physmem.perBankWrBursts::7 8818 # Per bank write bursts -system.physmem.perBankWrBursts::8 7762 # Per bank write bursts -system.physmem.perBankWrBursts::9 7809 # Per bank write bursts -system.physmem.perBankWrBursts::10 7936 # Per bank write bursts -system.physmem.perBankWrBursts::11 7396 # Per bank write bursts -system.physmem.perBankWrBursts::12 7882 # Per bank write bursts -system.physmem.perBankWrBursts::13 8742 # Per bank write bursts -system.physmem.perBankWrBursts::14 8045 # Per bank write bursts -system.physmem.perBankWrBursts::15 7623 # Per bank write bursts +system.physmem.perBankRdBursts::12 10349 # Per bank write bursts +system.physmem.perBankRdBursts::13 11405 # Per bank write bursts +system.physmem.perBankRdBursts::14 10639 # Per bank write bursts +system.physmem.perBankRdBursts::15 10293 # Per bank write bursts +system.physmem.perBankWrBursts::0 10392 # Per bank write bursts +system.physmem.perBankWrBursts::1 10480 # Per bank write bursts +system.physmem.perBankWrBursts::2 10999 # Per bank write bursts +system.physmem.perBankWrBursts::3 10520 # Per bank write bursts +system.physmem.perBankWrBursts::4 10645 # Per bank write bursts +system.physmem.perBankWrBursts::5 10713 # Per bank write bursts +system.physmem.perBankWrBursts::6 11169 # Per bank write bursts +system.physmem.perBankWrBursts::7 10762 # Per bank write bursts +system.physmem.perBankWrBursts::8 9958 # Per bank write bursts +system.physmem.perBankWrBursts::9 10000 # Per bank write bursts +system.physmem.perBankWrBursts::10 9968 # Per bank write bursts +system.physmem.perBankWrBursts::11 9745 # Per bank write bursts +system.physmem.perBankWrBursts::12 10100 # Per bank write bursts +system.physmem.perBankWrBursts::13 10962 # Per bank write bursts +system.physmem.perBankWrBursts::14 10229 # Per bank write bursts +system.physmem.perBankWrBursts::15 9795 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2804324017000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2814521100500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 175082 # Read request sizes (log2) +system.physmem.readPktSize::6 174805 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131723 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 104376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1509 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 167865 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 104183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -165,195 +162,218 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 89 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 89 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 90 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 120 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64783 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.989874 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.723316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.460023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24407 37.68% 37.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15776 24.35% 62.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6538 10.09% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3738 5.77% 77.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2814 4.34% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1507 2.33% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1107 1.71% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1104 1.70% 87.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7792 12.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64783 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6707 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.165350 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 477.307058 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6704 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 325.854595 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.388710 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 345.406571 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24509 36.52% 36.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15902 23.70% 60.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6498 9.68% 69.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3742 5.58% 75.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2828 4.21% 79.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1529 2.28% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1119 1.67% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1119 1.67% 85.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9863 14.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67109 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7131 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.571869 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 462.936248 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7128 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6707 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.712092 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.230918 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.181787 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 16 0.24% 0.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.10% 0.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 4 0.06% 0.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 9 0.13% 0.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5755 85.81% 86.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 109 1.63% 87.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 46 0.69% 88.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 238 3.55% 92.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 224 3.34% 95.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 22 0.33% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 23 0.34% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.10% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 31 0.46% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.03% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.12% 96.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 152 2.27% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.04% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.07% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 12 0.18% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 13 0.19% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.06% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.07% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6707 # Writes before turning the bus around for reads -system.physmem.totQLat 2727699250 # Total ticks spent queuing -system.physmem.totMemAccLat 6018343000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 877505000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15542.36 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7131 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7131 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.339924 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.576956 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.763951 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 15 0.21% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.10% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 3 0.04% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 7 0.10% 0.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5889 82.58% 83.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 114 1.60% 84.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 53 0.74% 85.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 224 3.14% 88.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 142 1.99% 90.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 54 0.76% 91.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 26 0.36% 91.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 40 0.56% 92.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 124 1.74% 93.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.15% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 11 0.15% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 11 0.15% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 24 0.34% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 13 0.18% 94.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 13 0.18% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 32 0.45% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 59 0.83% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 9 0.13% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 6 0.08% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 9 0.13% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 92 1.29% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.07% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 8 0.11% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 4 0.06% 98.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 17 0.24% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.04% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 14 0.20% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.04% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 38 0.53% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 9 0.13% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.13% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.04% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 7 0.10% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 3 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7131 # Writes before turning the bus around for reads +system.physmem.totQLat 2737638250 # Total ticks spent queuing +system.physmem.totMemAccLat 6023538250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 876240000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15621.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34292.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34371.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.98 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.66 # Average write queue length when enqueuing -system.physmem.readRowHits 145124 # Number of row buffer hits during reads -system.physmem.writeRowHits 97802 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.96 # Row buffer hit rate for writes -system.physmem.avgGap 8995685.58 # Average gap between requests -system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2678459999250 # Time in different power states -system.physmem.memoryStateTime::REF 93642380000 # Time in different power states +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.89 # Average write queue length when enqueuing +system.physmem.readRowHits 144870 # Number of row buffer hits during reads +system.physmem.writeRowHits 129705 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.92 # Row buffer hit rate for writes +system.physmem.avgGap 8096871.46 # Average gap between requests +system.physmem.pageHitRate 80.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2688100208500 # Time in different power states +system.physmem.memoryStateTime::REF 93982980000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 32221812750 # Time in different power states +system.physmem.memoryStateTime::ACT 32438087000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 259096320 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 230663160 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 141372000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 125857875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 715533000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 653367000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 447210720 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 409503600 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 183164495280 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 183164495280 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 77871628440 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 76866307470 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1614283197000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1615165057500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1876882532760 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1876615251885 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.282725 # Core power per rank (mW) -system.physmem.averagePower::1 669.187414 # Core power per rank (mW) +system.physmem.actEnergy::0 267820560 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 239523480 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 146132250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 130692375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 714347400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 652579200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 555206400 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 523305360 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 183830708880 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 183830708880 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 78196283910 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 77193580095 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1620118404000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1620997968750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1883828903400 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1883568358140 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.325253 # Core power per rank (mW) +system.physmem.averagePower::1 669.232681 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 640 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 640 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 640 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 640 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 10 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 10 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 228 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 228 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 228 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 228 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 228 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 228 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 227 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 227 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 227 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 227 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 227 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 227 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 27347795 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14227638 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 549324 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 17049849 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 12874628 # Number of BTB hits +system.cpu0.branchPred.lookups 27454524 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14302225 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 560028 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 17144432 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12924274 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 75.511683 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6769747 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 30174 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 75.384673 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6779174 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 30579 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -378,25 +398,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14276180 # DTB read hits -system.cpu0.dtb.read_misses 49315 # DTB read misses -system.cpu0.dtb.write_hits 10339289 # DTB write hits -system.cpu0.dtb.write_misses 7532 # DTB write misses -system.cpu0.dtb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 14369333 # DTB read hits +system.cpu0.dtb.read_misses 50679 # DTB read misses +system.cpu0.dtb.write_hits 10383293 # DTB write hits +system.cpu0.dtb.write_misses 7631 # DTB write misses +system.cpu0.dtb.flush_tlb 181 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3434 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1022 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1284 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3537 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1074 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1312 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14325495 # DTB read accesses -system.cpu0.dtb.write_accesses 10346821 # DTB write accesses +system.cpu0.dtb.perms_faults 596 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14420012 # DTB read accesses +system.cpu0.dtb.write_accesses 10390924 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24615469 # DTB hits -system.cpu0.dtb.misses 56847 # DTB misses -system.cpu0.dtb.accesses 24672316 # DTB accesses +system.cpu0.dtb.hits 24752626 # DTB hits +system.cpu0.dtb.misses 58310 # DTB misses +system.cpu0.dtb.accesses 24810936 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -418,158 +438,158 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 20541420 # ITB inst hits -system.cpu0.itb.inst_misses 9178 # ITB inst misses +system.cpu0.itb.inst_hits 20633477 # ITB inst hits +system.cpu0.itb.inst_misses 8891 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 181 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2315 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2375 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1446 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1486 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 20550598 # ITB inst accesses -system.cpu0.itb.hits 20541420 # DTB hits -system.cpu0.itb.misses 9178 # DTB misses -system.cpu0.itb.accesses 20550598 # DTB accesses -system.cpu0.numCycles 107861472 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20642368 # ITB inst accesses +system.cpu0.itb.hits 20633477 # DTB hits +system.cpu0.itb.misses 8891 # DTB misses +system.cpu0.itb.accesses 20642368 # DTB accesses +system.cpu0.numCycles 108176623 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 40570754 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 105629295 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 27347795 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19644375 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 61853082 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3245677 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 138610 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 7043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 456 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 740654 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 142990 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 184 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 20540168 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 376427 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3608 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 105076575 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.207830 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.305137 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 40839610 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 106163283 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 27454524 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19703448 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 62043143 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3268003 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 133218 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 6760 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 444 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 566983 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 143911 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 303 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20632158 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 383201 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3475 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 105368337 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.210422 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.308267 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 75967097 72.30% 72.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3896975 3.71% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2393426 2.28% 78.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 8192788 7.80% 86.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1656267 1.58% 87.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 1057275 1.01% 88.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6246218 5.94% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1068490 1.02% 95.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4598039 4.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 76140836 72.26% 72.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3909718 3.71% 75.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2409828 2.29% 78.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 8201309 7.78% 86.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1666024 1.58% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1066995 1.01% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6252269 5.93% 94.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1076692 1.02% 95.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4644666 4.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 105076575 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.253546 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.979305 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27994294 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58319975 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15794569 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1493949 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1473513 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1905038 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 151409 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 87407414 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 488746 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1473513 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28854924 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 7818064 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 44554229 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 16415102 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 5960455 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 83576128 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2157 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1234281 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 240945 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3763501 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 86207701 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 384903383 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 93172990 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5580 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 72433922 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13773763 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1548068 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1453832 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8905153 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 15025647 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11465948 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1963626 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2709003 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 80419048 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1054429 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 77104069 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 91403 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10038631 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24749704 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 115176 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 105076575 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.733789 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.427784 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 105368337 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.253794 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.981388 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 28207041 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58279935 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15901267 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1497528 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1482288 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1929977 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 153844 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 87989191 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 497994 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1482288 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 29073693 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 7845343 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 44593101 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16518954 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 5854664 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 84134111 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 3122 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1216605 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 229511 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3673419 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 86811691 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 387318144 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 93734921 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 6132 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 72788537 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14023138 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1551068 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1456111 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8913232 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 15130036 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11520954 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1958410 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2751427 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 80936298 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1061855 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 77564111 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 93737 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10215309 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 25112322 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 116543 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 105368337 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.736124 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.430465 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 74341292 70.75% 70.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10185363 9.69% 80.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7872852 7.49% 87.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6575632 6.26% 94.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2323435 2.21% 96.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1484934 1.41% 97.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1562160 1.49% 99.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 492520 0.47% 99.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 238387 0.23% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 74478008 70.68% 70.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10230371 9.71% 80.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7904463 7.50% 87.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6602787 6.27% 94.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2340926 2.22% 96.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1499410 1.42% 97.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1574332 1.49% 99.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 494613 0.47% 99.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 243427 0.23% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 105076575 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 105368337 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 112989 9.93% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 4 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 531745 46.73% 56.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 493078 43.34% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 114999 10.01% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 537121 46.77% 56.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 496300 43.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2199 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 51434902 66.71% 66.71% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57707 0.07% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2212 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 51748002 66.72% 66.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57664 0.07% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.79% # Type of FU issued @@ -579,7 +599,7 @@ system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.79% # Ty system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 2 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMisc 1 0.00% 66.79% # Type of FU issued @@ -593,410 +613,410 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.79% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4464 0.01% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14679264 19.04% 85.83% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10925524 14.17% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4488 0.01% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14779498 19.05% 85.85% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10972237 14.15% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 77104069 # Type of FU issued -system.cpu0.iq.rate 0.714843 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1137816 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014757 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 260501553 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 91556805 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 74656153 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12379 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6497 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5408 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 78233021 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6665 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 345101 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 77564111 # Type of FU issued +system.cpu0.iq.rate 0.717014 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1148423 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014806 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 261725178 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 92258450 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 75089604 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 13541 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 7156 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5898 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 78703023 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7299 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 349741 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2206473 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2440 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 52158 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1126677 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2246191 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2538 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 53151 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1141086 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 207379 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 207346 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 210404 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 206292 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1473513 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5378839 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 2159961 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 81600157 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 131532 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 15025647 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11465948 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 550941 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44144 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2103435 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 52158 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 253796 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 219690 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 473486 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 76500063 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 14443562 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 547275 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1482288 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5387849 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 2181647 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 82121235 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 133747 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 15130036 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11520954 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 554131 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 44613 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2124772 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 53151 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 259624 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 223920 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 483544 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 76945762 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14537604 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 560147 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 126680 # number of nop insts executed -system.cpu0.iew.exec_refs 25263883 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14430618 # Number of branches executed -system.cpu0.iew.exec_stores 10820321 # Number of stores executed -system.cpu0.iew.exec_rate 0.709244 # Inst execution rate -system.cpu0.iew.wb_sent 75840899 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 74661561 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 38996929 # num instructions producing a value -system.cpu0.iew.wb_consumers 67640251 # num instructions consuming a value +system.cpu0.iew.exec_nop 123082 # number of nop insts executed +system.cpu0.iew.exec_refs 25403316 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14507602 # Number of branches executed +system.cpu0.iew.exec_stores 10865712 # Number of stores executed +system.cpu0.iew.exec_rate 0.711298 # Inst execution rate +system.cpu0.iew.wb_sent 76276982 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 75095502 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 39231378 # num instructions producing a value +system.cpu0.iew.wb_consumers 67987446 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.692199 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.576534 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.694193 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.577039 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11313930 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 939253 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 399962 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 102521377 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.684763 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.574745 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11493235 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 945312 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 408278 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 102784889 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.686324 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.576953 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 75202228 73.35% 73.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12236708 11.94% 85.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6265954 6.11% 91.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2644751 2.58% 93.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1294412 1.26% 95.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 834681 0.81% 96.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1890114 1.84% 97.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 411979 0.40% 98.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1740550 1.70% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 75343720 73.30% 73.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12296354 11.96% 85.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6287520 6.12% 91.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2655547 2.58% 93.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1297923 1.26% 95.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 837088 0.81% 96.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1893538 1.84% 97.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 418210 0.41% 98.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1754989 1.71% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 102521377 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 57875239 # Number of instructions committed -system.cpu0.commit.committedOps 70202859 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 102784889 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 58163617 # Number of instructions committed +system.cpu0.commit.committedOps 70543777 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 23158445 # Number of memory references committed -system.cpu0.commit.loads 12819174 # Number of loads committed -system.cpu0.commit.membars 372518 # Number of memory barriers committed -system.cpu0.commit.branches 13646130 # Number of branches committed -system.cpu0.commit.fp_insts 5383 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 61467682 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2657552 # Number of function calls committed. +system.cpu0.commit.refs 23263713 # Number of memory references committed +system.cpu0.commit.loads 12883845 # Number of loads committed +system.cpu0.commit.membars 375648 # Number of memory barriers committed +system.cpu0.commit.branches 13703294 # Number of branches committed +system.cpu0.commit.fp_insts 5822 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 61764808 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2662565 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 46983958 66.93% 66.93% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55992 0.08% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4464 0.01% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12819174 18.26% 85.27% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10339271 14.73% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 47219648 66.94% 66.94% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55928 0.08% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4488 0.01% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12883845 18.26% 85.29% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10379868 14.71% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 70202859 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1740550 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 70543777 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1754989 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 169629703 # The number of ROB reads -system.cpu0.rob.rob_writes 165592947 # The number of ROB writes -system.cpu0.timesIdled 399199 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2784897 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2442098527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 57803575 # Number of Instructions Simulated -system.cpu0.committedOps 70131195 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.866000 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.866000 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.535906 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.535906 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 83223669 # number of integer regfile reads -system.cpu0.int_regfile_writes 47570918 # number of integer regfile writes -system.cpu0.fp_regfile_reads 16180 # number of floating regfile reads -system.cpu0.fp_regfile_writes 12936 # number of floating regfile writes -system.cpu0.cc_regfile_reads 270428616 # number of cc regfile reads -system.cpu0.cc_regfile_writes 28197078 # number of cc regfile writes -system.cpu0.misc_regfile_reads 191501099 # number of misc regfile reads -system.cpu0.misc_regfile_writes 720417 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 852560 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.984422 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42511963 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 853072 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.833968 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 170407355 # The number of ROB reads +system.cpu0.rob.rob_writes 166661887 # The number of ROB writes +system.cpu0.timesIdled 403384 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2808286 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2462180041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 58092959 # Number of Instructions Simulated +system.cpu0.committedOps 70473119 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.862130 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.862130 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.537020 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.537020 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 83669019 # number of integer regfile reads +system.cpu0.int_regfile_writes 47858513 # number of integer regfile writes +system.cpu0.fp_regfile_reads 16561 # number of floating regfile reads +system.cpu0.fp_regfile_writes 13070 # number of floating regfile writes +system.cpu0.cc_regfile_reads 272007090 # number of cc regfile reads +system.cpu0.cc_regfile_writes 28371958 # number of cc regfile writes +system.cpu0.misc_regfile_reads 192053211 # number of misc regfile reads +system.cpu0.misc_regfile_writes 725022 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 853093 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.984491 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42526051 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 853605 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.819356 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 91705250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 328.271130 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 183.713292 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.641155 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.358815 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 331.074612 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 180.909879 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.646630 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.353340 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189853089 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189853089 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 12598830 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12738851 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25337681 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7730207 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 8172441 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15902648 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180909 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 181454 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 362363 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 207827 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 238877 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 446704 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 213772 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 245645 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459417 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20329037 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20911292 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41240329 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20509946 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21092746 # number of overall hits -system.cpu0.dcache.overall_hits::total 41602692 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 422442 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 405866 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 828308 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1913785 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1789558 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3703343 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 96940 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 84905 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 181845 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13431 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14182 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27613 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 189920314 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189920314 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 12675400 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 12670649 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25346049 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7759190 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 8148697 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15907887 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 181607 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 180873 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 362480 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 209218 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 237638 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 446856 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 215214 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 244406 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459620 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20434590 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 20819346 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41253936 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20616197 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21000219 # number of overall hits +system.cpu0.dcache.overall_hits::total 41616416 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 429328 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 400663 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 829991 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1922864 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1781286 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 3704150 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 97758 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 84121 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 181879 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13488 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14194 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 27682 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 28 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 49 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 77 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2336227 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2195424 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4531651 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2433167 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2280329 # number of overall misses -system.cpu0.dcache.overall_misses::total 4713496 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7006933211 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6629197868 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13636131079 # 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number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 899145507 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1879055012 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 46870501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79520003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 126390504 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 411492 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 768982 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1180474 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9648547200 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9090744839 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 18739292039 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10628456705 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9989890346 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 20618347051 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3173952500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2610543001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784495501 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2430739877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2005307000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4436046877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5604692377 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4615850001 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220542378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016260 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016264 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016262 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015948 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014643 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228304 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.218521 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223516 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017780 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020470 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019215 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000131 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000199 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000168 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016127 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015565 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015843 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018697 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017878 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018284 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13513.315086 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13667.806116 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13590.935473 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44130.918058 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42289.243196 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43234.457208 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15447.701627 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15447.908376 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15447.800557 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11914.209710 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15351.351931 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13867.731402 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14696.142857 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15693.510204 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15330.831169 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26396.336239 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25276.081274 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25840.741162 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24777.267589 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23907.094780 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24347.882676 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 50 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 78 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 368071 # 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number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 978421259 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 894015008 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1872436267 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 46952751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79934003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 126886754 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 536492 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 753484 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1289976 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9599504714 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9164100290 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 18763605004 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10577925973 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10058115298 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 20636041271 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3170222000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2614349000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784571000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2418015877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2018079000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4436094877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5588237877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4632428000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220665877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016308 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016242 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016275 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015943 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014630 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015279 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.229359 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.217205 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223443 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017732 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020772 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019345 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000130 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000205 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000170 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016153 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015546 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015848 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018735 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017843 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018287 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13478.219605 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13806.770002 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13641.954947 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43527.537428 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42902.554244 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43224.521409 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15269.937714 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15532.419612 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15394.146876 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11889.782477 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15280.826419 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13822.086492 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19160.428571 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15069.680000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16538.153846 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26080.578785 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25627.753653 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25857.437965 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24477.667207 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24228.073936 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24355.374932 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1007,150 +1027,150 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1944459 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.580154 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 39104715 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1944971 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 20.105552 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1945413 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.581807 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 39117111 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1945925 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 20.102065 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 9481344250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 279.534125 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 232.046029 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.545965 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.453215 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999180 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 277.889096 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 233.692710 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.542752 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.456431 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999183 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 158 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43134734 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43134734 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 19500172 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19604543 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 39104715 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19500172 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19604543 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 39104715 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19500172 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19604543 # 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average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 9173 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 502 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 525 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.414343 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.472381 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 69295 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 70585 # 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number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 49455500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 49455500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047228 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047217 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047222 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047228 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.047217 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047222 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047228 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.047217 # 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average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047500 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046959 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047229 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047500 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046959 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047229 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047500 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046959 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047229 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11965.099923 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11897.356672 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11931.471227 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11965.099923 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11897.356672 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11931.471227 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11965.099923 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11897.356672 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11931.471227 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 27351704 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14236490 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 554287 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17308437 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 12845549 # Number of BTB hits +system.cpu1.branchPred.lookups 27255758 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14164958 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 545624 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17245755 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 12796801 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 74.215534 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6761805 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 29778 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 74.202614 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6756979 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 29539 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1174,25 +1194,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14383095 # DTB read hits -system.cpu1.dtb.read_misses 49639 # DTB read misses -system.cpu1.dtb.write_hits 10688826 # DTB write hits -system.cpu1.dtb.write_misses 9570 # DTB write misses -system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 14301761 # DTB read hits +system.cpu1.dtb.read_misses 48555 # DTB read misses +system.cpu1.dtb.write_hits 10652785 # DTB write hits +system.cpu1.dtb.write_misses 10002 # DTB write misses +system.cpu1.dtb.flush_tlb 175 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3468 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 807 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1316 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3340 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 749 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1278 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14432734 # DTB read accesses -system.cpu1.dtb.write_accesses 10698396 # DTB write accesses +system.cpu1.dtb.perms_faults 539 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14350316 # DTB read accesses +system.cpu1.dtb.write_accesses 10662787 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25071921 # DTB hits -system.cpu1.dtb.misses 59209 # DTB misses -system.cpu1.dtb.accesses 25131130 # DTB accesses +system.cpu1.dtb.hits 24954546 # DTB hits +system.cpu1.dtb.misses 58557 # DTB misses +system.cpu1.dtb.accesses 25013103 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1214,333 +1234,334 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 20651947 # ITB inst hits -system.cpu1.itb.inst_misses 7444 # ITB inst misses +system.cpu1.itb.inst_hits 20573712 # ITB inst hits +system.cpu1.itb.inst_misses 7567 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 175 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2253 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2209 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1346 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1224 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20659391 # ITB inst accesses -system.cpu1.itb.hits 20651947 # DTB hits -system.cpu1.itb.misses 7444 # DTB misses -system.cpu1.itb.accesses 20659391 # DTB accesses -system.cpu1.numCycles 107242437 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20581279 # ITB inst accesses +system.cpu1.itb.hits 20573712 # DTB hits +system.cpu1.itb.misses 7567 # DTB misses +system.cpu1.itb.accesses 20581279 # DTB accesses +system.cpu1.numCycles 106992745 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40725111 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 106781914 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27351704 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19607354 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 61789362 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3232365 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 107163 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 4234 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 436 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 251985 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 137059 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 228 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20650163 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 382444 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3144 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 104631724 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.228100 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.325979 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40476291 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 106336791 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27255758 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19553780 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 61749013 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3214085 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 109935 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 4125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 398 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 310457 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 137038 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20572028 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 377209 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3305 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 104394378 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.225923 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.323476 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 75276621 71.94% 71.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3919456 3.75% 75.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2502030 2.39% 78.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8106690 7.75% 85.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1591855 1.52% 87.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1179587 1.13% 88.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6153020 5.88% 94.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1148569 1.10% 95.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4753896 4.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 75141351 71.98% 71.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3905835 3.74% 75.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2486724 2.38% 78.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8099869 7.76% 85.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1581267 1.51% 87.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1170303 1.12% 88.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6153110 5.89% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1141979 1.09% 95.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4713940 4.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 104631724 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.255046 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.995706 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27872686 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 57819434 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15751164 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1722324 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1465861 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1979467 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 152392 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 89250616 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 494405 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1465861 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28821025 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 6714609 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 45327507 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16516394 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 5786062 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 85371989 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2599 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1571177 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 234219 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 3175787 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 88221695 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 393591898 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 95352384 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6204 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 74304877 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13916818 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1590220 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1488950 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10060689 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15200897 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11860337 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2181365 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2795831 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 82084086 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1161665 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 78697860 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94798 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10134538 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 25514104 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 106722 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 104631724 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.752141 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.431263 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 104394378 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.254744 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.993869 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27669699 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 57891094 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15657559 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1717451 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1458318 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1956668 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 150768 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 88739686 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 487490 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1458318 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28613011 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 6694397 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 45325373 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16423590 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 5879419 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 84880856 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2064 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1581177 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 275105 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 3240122 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 87684483 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 391488803 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 94864107 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5764 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 73992323 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13692160 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1588753 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1487965 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10049323 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15109971 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11816534 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2163704 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2733219 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 81632312 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1156422 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 78295274 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93656 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9981310 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 25207475 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 106198 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 104394378 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.749995 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.429509 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 72948361 69.72% 69.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10716718 10.24% 79.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8047314 7.69% 87.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6681191 6.39% 94.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2496863 2.39% 96.42% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1548306 1.48% 97.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1467102 1.40% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 495605 0.47% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 230264 0.22% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 72878860 69.81% 69.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10639333 10.19% 80.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8017923 7.68% 87.68% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6659758 6.38% 94.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2479715 2.38% 96.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1538380 1.47% 97.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1459445 1.40% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 494321 0.47% 99.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 226643 0.22% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 104631724 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 104394378 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 103418 8.95% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 4 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 534479 46.25% 55.20% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 517677 44.80% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 101103 8.77% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 4 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 535174 46.44% 55.22% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 516045 44.78% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 138 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 52546114 66.77% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 58878 0.07% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 1 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4118 0.01% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14788040 18.79% 85.64% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11300566 14.36% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 125 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 52268288 66.76% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59024 0.08% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 1 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4106 0.01% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14700600 18.78% 85.61% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11263124 14.39% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 78697860 # Type of FU issued -system.cpu1.iq.rate 0.733831 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1155578 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014684 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 263263981 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 93425233 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 76303202 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 13839 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7410 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6119 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 79845879 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7421 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 368633 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 78295274 # Type of FU issued +system.cpu1.iq.rate 0.731781 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1152326 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014718 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 262217922 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 92814464 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 75924804 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12986 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6859 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5648 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 79440457 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7018 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 366358 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2206977 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2711 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 53558 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1154048 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2171723 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2780 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 52487 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1144439 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 194646 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 154093 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 191401 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 154292 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1465861 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4319089 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2154851 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 83386940 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 137036 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15200897 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11860337 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 585271 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 47319 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2094987 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 53558 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 256552 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 222245 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 478797 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 78084459 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14546039 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 554355 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1458318 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4304329 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2156600 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 82933418 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 134740 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15109971 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11816534 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 582996 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 47778 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2096463 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 52487 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 251579 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 218702 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 470281 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 77694436 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14463933 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 542445 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 141189 # number of nop insts executed -system.cpu1.iew.exec_refs 25737628 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14524352 # Number of branches executed -system.cpu1.iew.exec_stores 11191589 # Number of stores executed -system.cpu1.iew.exec_rate 0.728112 # Inst execution rate -system.cpu1.iew.wb_sent 77455792 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 76309321 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 39942887 # num instructions producing a value -system.cpu1.iew.wb_consumers 70003346 # num instructions consuming a value +system.cpu1.iew.exec_nop 144684 # number of nop insts executed +system.cpu1.iew.exec_refs 25618626 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14454326 # Number of branches executed +system.cpu1.iew.exec_stores 11154693 # Number of stores executed +system.cpu1.iew.exec_rate 0.726165 # Inst execution rate +system.cpu1.iew.wb_sent 77075073 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 75930452 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 39739983 # num instructions producing a value +system.cpu1.iew.wb_consumers 69711076 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.711559 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.570585 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.709679 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.570067 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 11462178 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1054943 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 403929 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 102065282 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.704569 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.588134 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 11308333 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1050224 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 396863 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 101852612 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.703099 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.586744 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 73979562 72.48% 72.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12596710 12.34% 84.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6446210 6.32% 91.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2677597 2.62% 93.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1413220 1.38% 95.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 933927 0.92% 96.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1825426 1.79% 97.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 426013 0.42% 98.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1766617 1.73% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 73894552 72.55% 72.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12525380 12.30% 84.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6426003 6.31% 91.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2662589 2.61% 93.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1410437 1.38% 95.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 930996 0.91% 96.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1822810 1.79% 97.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 425009 0.42% 98.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1754836 1.72% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 102065282 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 59241455 # Number of instructions committed -system.cpu1.commit.committedOps 71912019 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 101852612 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 58987480 # Number of instructions committed +system.cpu1.commit.committedOps 71612492 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 23700209 # Number of memory references committed -system.cpu1.commit.loads 12993920 # Number of loads committed -system.cpu1.commit.membars 441872 # Number of memory barriers committed -system.cpu1.commit.branches 13745651 # Number of branches committed -system.cpu1.commit.fp_insts 6045 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 63021281 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2683532 # Number of function calls committed. +system.cpu1.commit.refs 23610343 # Number of memory references committed +system.cpu1.commit.loads 12938248 # Number of loads committed +system.cpu1.commit.membars 439261 # Number of memory barriers committed +system.cpu1.commit.branches 13694369 # Number of branches committed +system.cpu1.commit.fp_insts 5606 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 62760739 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2679383 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 48150599 66.96% 66.96% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57094 0.08% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4117 0.01% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 12993920 18.07% 85.11% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10706289 14.89% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 47940825 66.94% 66.94% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57221 0.08% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4103 0.01% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 12938248 18.07% 85.10% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10672095 14.90% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 71912019 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1766617 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 71612492 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1754836 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 171199210 # The number of ROB reads -system.cpu1.rob.rob_writes 169319306 # The number of ROB writes -system.cpu1.timesIdled 392561 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2610713 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2951410695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 59158214 # Number of Instructions Simulated -system.cpu1.committedOps 71828778 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.812807 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.812807 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.551631 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.551631 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 84962024 # number of integer regfile reads -system.cpu1.int_regfile_writes 48578648 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16598 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13166 # number of floating regfile writes -system.cpu1.cc_regfile_reads 275767015 # number of cc regfile reads -system.cpu1.cc_regfile_writes 29005141 # number of cc regfile writes -system.cpu1.misc_regfile_reads 192510337 # number of misc regfile reads -system.cpu1.misc_regfile_writes 799392 # number of misc regfile writes +system.cpu1.rob.rob_reads 170535238 # The number of ROB reads +system.cpu1.rob.rob_writes 168387616 # The number of ROB writes +system.cpu1.timesIdled 388789 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2598367 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2951659136 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 58903233 # Number of Instructions Simulated +system.cpu1.committedOps 71528245 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.816415 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.816415 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.550535 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.550535 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 84575323 # number of integer regfile reads +system.cpu1.int_regfile_writes 48329446 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16299 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13042 # number of floating regfile writes +system.cpu1.cc_regfile_reads 274393748 # number of cc regfile reads +system.cpu1.cc_regfile_writes 28845956 # number of cc regfile writes +system.cpu1.misc_regfile_reads 191595742 # number of misc regfile reads +system.cpu1.misc_regfile_writes 795775 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30210 # Transaction distribution system.iobus.trans_dist::ReadResp 30210 # Transaction distribution system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1631,42 +1652,46 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326614949 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347069959 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36834534 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36834574 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36423 # number of replacements -system.iocache.tags.tagsinuse 0.982055 # Cycle average of tags in use -system.iocache.tags.total_refs 16 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 234012764000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.982055 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.061378 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.061378 # Average percentage of cache occupancy +system.iocache.tags.replacements 36411 # number of replacements +system.iocache.tags.tagsinuse 1.036467 # Cycle average of tags in use +system.iocache.tags.total_refs 28 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36427 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000769 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 234012835000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.036467 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064779 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064779 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328241 # Number of tag accesses -system.iocache.tags.data_accesses 328241 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 328229 # Number of tag accesses +system.iocache.tags.data_accesses 328229 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 27 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 27 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses system.iocache.ReadReq_misses::total 249 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36197 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36197 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses system.iocache.demand_misses::total 249 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 249 # number of overall misses system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29659377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29659377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29659377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29659377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29659377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29659377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29650777 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29650777 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9620896608 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9620896608 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29650777 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29650777 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29650777 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29650777 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1677,296 +1702,306 @@ system.iocache.overall_accesses::realview.ide 249 system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.999255 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.999255 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119113.963855 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119113.963855 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119113.963855 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119113.963855 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119113.963855 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119113.963855 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 119079.425703 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119079.425703 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265792.651546 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265792.651546 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119079.425703 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119079.425703 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119079.425703 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119079.425703 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56505 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7228 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.817515 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36162 # number of writebacks +system.iocache.writebacks::total 36162 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36197 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36197 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.028353 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.013880 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.969357 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.961487 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.965190 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.367347 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.337662 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.490251 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.454192 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.472713 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001816 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000108 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.024472 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001869 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010193 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.029425 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.013878 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.967953 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.966667 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.967288 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.357143 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.320000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.482325 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.462572 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.472753 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001796 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000112 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.011238 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.189690 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001875 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010219 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.174210 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.061041 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001816 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000108 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.185622 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001869 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010193 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.178151 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.061018 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001796 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000112 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.011238 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.189690 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001875 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010219 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.174210 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.061041 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67026.119403 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu0.data 0.185622 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001869 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010193 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.178151 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.061018 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62939.311927 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68249.154993 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62482.734391 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 69566.014635 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 65322.906692 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.781804 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10044.162983 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.500546 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62789.275336 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68457.461561 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62958.583037 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71153.569434 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 65815.992635 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.127916 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10161.450387 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10084.454182 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20050.800000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64274.914919 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65547.461649 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 64869.592247 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67026.119403 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 13866.307692 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64141.581463 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65701.749106 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64881.275293 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62939.311927 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64620.091520 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62482.734391 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65977.465861 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 64962.074596 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67026.119403 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62789.275336 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64510.303765 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62958.583037 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66293.042370 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 65072.025171 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62939.311927 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64620.091520 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62482.734391 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65977.465861 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 64962.074596 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62789.275336 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64510.303765 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62958.583037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66293.042370 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 65072.025171 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -2147,57 +2182,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 68015 # Transaction distribution -system.membus.trans_dist::ReadResp 68014 # Transaction distribution -system.membus.trans_dist::WriteReq 27608 # Transaction distribution -system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 95499 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4626 # Transaction distribution +system.membus.trans_dist::ReadReq 68031 # Transaction distribution +system.membus.trans_dist::ReadResp 68030 # Transaction distribution +system.membus.trans_dist::WriteReq 27609 # Transaction distribution +system.membus.trans_dist::WriteResp 27609 # Transaction distribution +system.membus.trans_dist::Writeback 131669 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36196 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36196 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4639 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 26 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4652 # Transaction distribution -system.membus.trans_dist::ReadExReq 138449 # Transaction distribution -system.membus.trans_dist::ReadExResp 138449 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4665 # Transaction distribution +system.membus.trans_dist::ReadExReq 138446 # Transaction distribution +system.membus.trans_dist::ReadExResp 138446 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464808 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 572448 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 572218 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 681038 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17335960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17499937 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19819233 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 234 # Total snoops (count) -system.membus.snoop_fanout::samples 311043 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17318744 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17482733 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4631872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4631872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22114605 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 524 # Total snoops (count) +system.membus.snoop_fanout::samples 347207 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 311043 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 347207 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 311043 # Request fanout histogram -system.membus.reqLayer0.occupancy 81528999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 347207 # Request fanout histogram +system.membus.reqLayer0.occupancy 81506999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 15812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1699500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1714000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1433996498 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1759264748 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1730108850 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1730266590 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38499466 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38512426 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2230,57 +2265,57 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2655847 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2655761 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 703475 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2657108 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2657013 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27609 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27609 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 704003 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36196 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2844 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 77 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 78 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2921 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296861 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296861 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891199 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2533159 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43047 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169738 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6637143 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124509952 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99813985 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 66376 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 294776 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224685089 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 69111 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3663534 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.009957 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.099284 # Request fanout histogram +system.toL2Bus.trans_dist::ReadExReq 296844 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296844 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3893099 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2534750 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42773 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169663 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6640285 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124570688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99881325 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 65944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 294780 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224812737 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 68939 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3665274 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.009944 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.099221 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3627058 99.00% 99.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36476 1.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3628828 99.01% 99.01% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36446 0.99% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3663534 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4671361722 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3665274 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4674358232 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 697500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 8762587438 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 8766890883 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3909721674 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3912089949 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26515368 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 26359345 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 96849116 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 96778607 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 3042 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |