diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | 2788 |
1 files changed, 1388 insertions, 1400 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 56b72ce02..da9e176fe 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,163 +1,151 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.541275 # Number of seconds simulated -sim_ticks 2541275479000 # Number of ticks simulated -final_tick 2541275479000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.543226 # Number of seconds simulated +sim_ticks 2543226083000 # Number of ticks simulated +final_tick 2543226083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58368 # Simulator instruction rate (inst/s) -host_op_rate 75104 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2459458086 # Simulator tick rate (ticks/s) -host_mem_usage 437960 # Number of bytes of host memory used -host_seconds 1033.27 # Real time elapsed on the host -sim_insts 60310144 # Number of instructions simulated -sim_ops 77602537 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 24298 # Simulator instruction rate (inst/s) +host_op_rate 31265 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1024641665 # Simulator tick rate (ticks/s) +host_mem_usage 442376 # Number of bytes of host memory used +host_seconds 2482.06 # Real time elapsed on the host +sim_insts 60309820 # Number of instructions simulated +sim_ops 77602107 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 2112 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 503040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4153104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 296576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4940508 # Number of bytes read from this memory -system.physmem.bytes_read::total 131006444 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 503040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 296576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785600 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1346056 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1670056 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801712 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 511168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4147472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 290304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4947228 # Number of bytes read from this memory +system.physmem.bytes_read::total 131010156 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 511168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 290304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 801472 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3787712 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1346148 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1669964 # Number of bytes written to this memory +system.physmem.bytes_written::total 6803824 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 33 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7860 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 64926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4634 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77202 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293480 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59150 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336514 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417514 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813178 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47657379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 730 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 64838 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4536 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77307 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293538 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59183 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 336537 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 417491 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813211 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47620826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 830 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 197948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1634260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 116704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1944106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51551453 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 197948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 116704 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314651 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 529677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 657172 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2676495 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47657379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 200992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1630792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 114148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1945257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51513374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 200992 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 114148 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315140 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489334 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529307 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 656632 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2675273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47620826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 830 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 197948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2163937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 116704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2601278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54227949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293480 # Total number of read requests seen -system.physmem.writeReqs 813178 # Total number of write requests seen -system.physmem.cpureqs 218453 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978782720 # Total number of bytes read from memory -system.physmem.bytesWritten 52043392 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131006444 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6801712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4682 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956482 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955442 # Track reads on a per bank basis +system.physmem.bw_total::cpu0.inst 200992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2160099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 114148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2601889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54188647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293538 # Total number of read requests seen +system.physmem.writeReqs 813211 # Total number of write requests seen +system.physmem.cpureqs 218552 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978786432 # Total number of bytes read from memory +system.physmem.bytesWritten 52045504 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131010156 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6803824 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955738 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956493 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956273 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955443 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 955569 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956164 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956098 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955607 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955922 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956025 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955322 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955985 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50834 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50190 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50859 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51371 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50904 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50808 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51186 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50728 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51236 # Track writes on a per bank basis +system.physmem.perBankRdReqs::7 956157 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956101 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955527 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955934 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956035 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955435 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955983 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50828 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50414 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50915 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50189 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50286 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50807 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51194 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51255 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50732 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51231 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32469 # Number of times wr buffer was full causing retry -system.physmem.totGap 2541274319500 # Total gap between requests +system.physmem.numWrRetry 32473 # Number of times wr buffer was full causing retry +system.physmem.totGap 2543224928500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154621 # Categorize read packet sizes +system.physmem.readPktSize::6 154679 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754028 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59150 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1054746 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3604884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2723048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2699101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 9166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59183 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1054814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 991597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3605153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2700441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 59924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 109988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10663 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 9196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -168,282 +156,290 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2942 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 2939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2931 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 2921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35378 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35313 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35250 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35236 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32599 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 32527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32504 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 32495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32475 # What write queue length does an incoming req see -system.physmem.totQLat 346695398500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 439867444750 # Sum of mem lat for all requests -system.physmem.totBusLat 76467350000 # Total cycles spent in databus access -system.physmem.totBankLat 16704696250 # Total cycles spent in bank access -system.physmem.avgQLat 22669.51 # Average queueing delay per request -system.physmem.avgBankLat 1092.28 # Average bank access latency per request +system.physmem.wrQLenPdf::30 32489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32479 # What write queue length does an incoming req see +system.physmem.totQLat 346835420750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 440002912000 # Sum of mem lat for all requests +system.physmem.totBusLat 76467635000 # Total cycles spent in databus access +system.physmem.totBankLat 16699856250 # Total cycles spent in bank access +system.physmem.avgQLat 22678.58 # Average queueing delay per request +system.physmem.avgBankLat 1091.96 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28761.78 # Average memory access latency -system.physmem.avgRdBW 385.15 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.55 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 28770.53 # Average memory access latency +system.physmem.avgRdBW 384.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.46 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.51 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time system.physmem.avgWrQLen 1.12 # Average write queue length over time -system.physmem.readRowHits 15218335 # Number of row buffer hits during reads -system.physmem.writeRowHits 794661 # Number of row buffer hits during writes +system.physmem.readRowHits 15218407 # Number of row buffer hits during reads +system.physmem.writeRowHits 794595 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes -system.physmem.avgGap 157777.88 # Average gap between requests -system.l2c.replacements 64389 # number of replacements -system.l2c.tagsinuse 51396.917216 # Cycle average of tags in use -system.l2c.total_refs 1903765 # Total number of references to valid blocks. -system.l2c.sampled_refs 129779 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.669284 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2505294633000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36944.332930 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 18.025643 # Average occupied blocks per requestor +system.physmem.writeRowHitRate 97.71 # Row buffer hit rate for writes +system.physmem.avgGap 157898.09 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 64447 # number of replacements +system.l2c.tagsinuse 51415.469971 # Cycle average of tags in use +system.l2c.total_refs 1904213 # Total number of references to valid blocks. +system.l2c.sampled_refs 129841 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.665730 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2506268100000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36946.421058 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 20.318328 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5127.291089 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3277.380324 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 9.553076 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3076.231813 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2944.101992 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563726 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000275 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 5214.605130 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3261.076745 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 16.327658 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2998.760808 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2957.959894 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563758 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000310 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078236 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.050009 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000146 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.046940 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044923 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784255 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 32015 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7355 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 491964 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 214249 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30395 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6870 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 478610 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 173362 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1434820 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608422 # number of Writeback hits -system.l2c.Writeback_hits::total 608422 # number of Writeback hits +system.l2c.occ_percent::cpu0.inst 0.079569 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.049760 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000249 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.045757 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.045135 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784538 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 33050 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7442 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 494450 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 217567 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 29984 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6613 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 477029 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 169593 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435728 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 607829 # number of Writeback hits +system.l2c.Writeback_hits::total 607829 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 11 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57870 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55015 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112885 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32015 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7355 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 491964 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 272119 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30395 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6870 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 478610 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 228377 # number of demand (read+write) hits -system.l2c.demand_hits::total 1547705 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32015 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7355 # number of overall hits -system.l2c.overall_hits::cpu0.inst 491964 # number of overall hits -system.l2c.overall_hits::cpu0.data 272119 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30395 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6870 # number of overall hits -system.l2c.overall_hits::cpu1.inst 478610 # number of overall hits -system.l2c.overall_hits::cpu1.data 228377 # number of overall hits -system.l2c.overall_hits::total 1547705 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 29 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 57675 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 55157 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112832 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 33050 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7442 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 494450 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 275242 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 29984 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6613 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 477029 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 224750 # number of demand (read+write) hits +system.l2c.demand_hits::total 1548560 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 33050 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7442 # number of overall hits +system.l2c.overall_hits::cpu0.inst 494450 # number of overall hits +system.l2c.overall_hits::cpu0.data 275242 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 29984 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6613 # number of overall hits +system.l2c.overall_hits::cpu1.inst 477029 # number of overall hits +system.l2c.overall_hits::cpu1.data 224750 # number of overall hits +system.l2c.overall_hits::total 1548560 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 33 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7751 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6089 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4640 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4614 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23136 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1537 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1371 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2908 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 59818 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 73396 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133214 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 7877 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6086 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 19 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4540 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4624 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23181 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1632 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1283 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2915 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 59765 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 73463 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133228 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 33 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7751 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 65907 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4640 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 78010 # number of demand (read+write) misses -system.l2c.demand_misses::total 156350 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses +system.l2c.demand_misses::cpu0.inst 7877 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 65851 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4540 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 78087 # number of demand (read+write) misses +system.l2c.demand_misses::total 156409 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 33 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7751 # number of overall misses -system.l2c.overall_misses::cpu0.data 65907 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4640 # number of overall misses -system.l2c.overall_misses::cpu1.data 78010 # number of overall misses -system.l2c.overall_misses::total 156350 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1945000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 7877 # number of overall misses +system.l2c.overall_misses::cpu0.data 65851 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4540 # number of overall misses +system.l2c.overall_misses::cpu1.data 78087 # number of overall misses +system.l2c.overall_misses::total 156409 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2765500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 430985000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 344391500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 737500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 265908000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 270917500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1315002500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 204500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 227500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 432000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3114638500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3663340000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6777978500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1945000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 434812500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 348876500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1306000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 265734500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 270200000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1323813000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 205500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 182500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 388000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3099799500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3655844500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6755644000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2765500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 430985000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3459030000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 737500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 265908000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3934257500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8092981000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1945000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 434812500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3448676000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1306000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 265734500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3926044500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8079457000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2765500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 430985000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3459030000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 737500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 265908000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3934257500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8092981000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 32044 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 7357 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 499715 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 220338 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30406 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6870 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 483250 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 177976 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1457956 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 608422 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 608422 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1555 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1384 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2939 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 6 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu0.inst 434812500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3448676000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1306000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 265734500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3926044500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8079457000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 33083 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 7444 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 502327 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 223653 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30003 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6613 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 481569 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 174217 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1458909 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 607829 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 607829 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1650 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1294 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 3 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 5 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 117688 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 128411 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246099 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 32044 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7357 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 499715 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 338026 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30406 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6870 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 483250 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 306387 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1704055 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 32044 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7357 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 499715 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 338026 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30406 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6870 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 483250 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 306387 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1704055 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000905 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000272 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015511 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.027635 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000362 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009602 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.025925 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015869 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988424 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990607 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989452 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.166667 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.090909 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.508276 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.571571 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541302 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000905 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000272 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015511 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.194976 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000362 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009602 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.254613 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091752 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000905 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000272 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015511 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.194976 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000362 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009602 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.254613 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091752 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 67068.965517 # average ReadReq miss latency +system.l2c.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 117440 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 128620 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246060 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 33083 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7444 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 502327 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 341093 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30003 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6613 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 481569 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 302837 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1704969 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 33083 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7444 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 502327 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 341093 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30003 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6613 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 481569 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 302837 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1704969 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000997 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000269 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015681 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.027212 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000633 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009428 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.026542 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015889 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989091 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991499 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.990149 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.508898 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.571163 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541445 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000997 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000269 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015681 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.193059 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000633 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009428 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.257852 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091737 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000997 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000269 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015681 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.193059 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000633 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009428 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.257852 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091737 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83803.030303 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55603.793059 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 56559.615700 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 67045.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 57307.758621 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 58716.406589 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 56837.936549 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 133.051399 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 165.937272 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 148.555708 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52068.583035 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49911.984304 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 50880.376687 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 67068.965517 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55200.266599 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 57324.433125 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68736.842105 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 58531.828194 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 58434.256055 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 57107.674389 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 125.919118 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 142.244739 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 133.104631 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 51866.468669 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49764.432435 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 50707.388837 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83803.030303 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 55603.793059 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52483.499477 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 67045.454545 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 57307.758621 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 50432.732983 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51761.950752 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 67068.965517 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 55200.266599 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52370.897936 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68736.842105 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 58531.828194 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 50277.824734 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51655.959695 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83803.030303 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 55603.793059 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52483.499477 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 67045.454545 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 57307.758621 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 50432.732983 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51761.950752 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 55200.266599 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52370.897936 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68736.842105 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 58531.828194 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 50277.824734 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51655.959695 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -452,166 +448,158 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59150 # number of writebacks -system.l2c.writebacks::total 59150 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 21 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 59183 # number of writebacks +system.l2c.writebacks::total 59183 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 19 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 42 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 42 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 33 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7741 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6051 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4634 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4593 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23061 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1537 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1371 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2908 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 59818 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 73396 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133214 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 29 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7868 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6044 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 19 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4536 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4605 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23107 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1632 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1283 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 59765 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 73463 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133228 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 33 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7741 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 65869 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4634 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 77989 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156275 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7868 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 65809 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 19 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4536 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 78068 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156335 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 33 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7741 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 65869 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4634 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 77989 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156275 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1583028 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 7868 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 65809 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 19 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4536 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 78068 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156335 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2354282 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 334226230 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 267591443 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 598510 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 207854839 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 212784313 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1024731614 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15371537 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13786326 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29157863 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2368364997 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2749328891 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5117693888 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1583028 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 336517819 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 271517668 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1068769 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 209058491 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 211521322 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1032131602 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 16321632 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 12832782 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29154414 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2354223480 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2740919006 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5095142486 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2354282 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 334226230 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2635956440 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 598510 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 207854839 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2962113204 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6142425502 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1583028 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 336517819 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2625741148 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1068769 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 209058491 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2952440328 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6127274088 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2354282 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 334226230 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2635956440 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 598510 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 207854839 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2962113204 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6142425502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 336517819 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2625741148 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1068769 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 209058491 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2952440328 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6127274088 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5052330 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84119678267 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82847227004 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166971957601 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10487963006 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13201284574 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 23689247580 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83994636767 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82967803004 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166967492101 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10493457778 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13230278140 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 23723735918 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5052330 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94607641273 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 96048511578 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 190661205181 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027462 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025807 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015817 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988424 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990607 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.989452 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.090909 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508276 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571571 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541302 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.194864 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.254544 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091708 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.194864 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.254544 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091708 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94488094545 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 96198081144 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 190691228019 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000997 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000269 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015663 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027024 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000633 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009419 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026433 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015839 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989091 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991499 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.990149 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508898 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571163 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541445 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000997 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000269 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015663 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.192936 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000633 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009419 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.257789 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000997 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000269 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015663 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.192936 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000633 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.257789 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71341.878788 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44222.681044 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46327.958415 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44435.697238 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42770.439629 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44923.505625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46088.732584 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45932.968947 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44667.486130 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10055.671772 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.775447 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39592.848256 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37458.838234 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38417.087453 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.168355 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.514237 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39391.340751 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37310.197052 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38243.781232 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71341.878788 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40018.163931 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37981.166626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39305.234375 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42770.439629 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 39899.423301 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46088.732584 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37818.828816 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39193.233044 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71341.878788 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40018.163931 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37981.166626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39305.234375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42770.439629 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 39899.423301 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46088.732584 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37818.828816 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39193.233044 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -634,680 +622,680 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7621777 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6075515 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 381764 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4964344 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4051622 # Number of BTB hits +system.cpu0.branchPred.lookups 7719049 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6144205 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 388400 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 5016002 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4082948 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.614449 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 732539 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39625 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.398452 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 737953 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39729 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26065013 # DTB read hits -system.cpu0.dtb.read_misses 39990 # DTB read misses -system.cpu0.dtb.write_hits 5895229 # DTB write hits -system.cpu0.dtb.write_misses 9395 # DTB write misses +system.cpu0.dtb.read_hits 26145640 # DTB read hits +system.cpu0.dtb.read_misses 41213 # DTB read misses +system.cpu0.dtb.write_hits 5906110 # DTB write hits +system.cpu0.dtb.write_misses 9202 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 770 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5652 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1415 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 280 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5753 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1471 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 281 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 669 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26105003 # DTB read accesses -system.cpu0.dtb.write_accesses 5904624 # DTB write accesses +system.cpu0.dtb.perms_faults 691 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26186853 # DTB read accesses +system.cpu0.dtb.write_accesses 5915312 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31960242 # DTB hits -system.cpu0.dtb.misses 49385 # DTB misses -system.cpu0.dtb.accesses 32009627 # DTB accesses -system.cpu0.itb.inst_hits 6121620 # ITB inst hits -system.cpu0.itb.inst_misses 7590 # ITB inst misses +system.cpu0.dtb.hits 32051750 # DTB hits +system.cpu0.dtb.misses 50415 # DTB misses +system.cpu0.dtb.accesses 32102165 # DTB accesses +system.cpu0.itb.inst_hits 6183534 # ITB inst hits +system.cpu0.itb.inst_misses 7751 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 770 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2650 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2745 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1597 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1565 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6129210 # ITB inst accesses -system.cpu0.itb.hits 6121620 # DTB hits -system.cpu0.itb.misses 7590 # DTB misses -system.cpu0.itb.accesses 6129210 # DTB accesses -system.cpu0.numCycles 238950356 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6191285 # ITB inst accesses +system.cpu0.itb.hits 6183534 # DTB hits +system.cpu0.itb.misses 7751 # DTB misses +system.cpu0.itb.accesses 6191285 # DTB accesses +system.cpu0.numCycles 239079415 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15511561 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47861098 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7621777 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4784161 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10616760 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2562446 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 93609 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49488171 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1985 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 51736 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 101083 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6119617 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 397619 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3186 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77638963 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.762623 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.119947 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15644570 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 48338125 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7719049 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4820901 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10703205 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2596540 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 94746 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49591987 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1783 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1964 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 53331 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101492 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6181495 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 400642 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3259 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77992242 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.765373 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.123716 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67029800 86.34% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 691008 0.89% 87.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 886701 1.14% 88.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1229558 1.58% 89.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1143059 1.47% 91.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 577576 0.74% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1327799 1.71% 93.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 398469 0.51% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4354993 5.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67296980 86.29% 86.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 702662 0.90% 87.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 892389 1.14% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1243235 1.59% 89.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1139067 1.46% 91.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 581520 0.75% 92.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1338462 1.72% 93.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 402047 0.52% 94.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4395880 5.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77638963 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031897 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.200297 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16561693 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49223207 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9616319 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 551624 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1684026 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1027423 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90511 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56351612 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 302709 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1684026 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17495833 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18963913 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27008828 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9162852 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3321475 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53533397 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13490 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 620965 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2156088 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 544 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55691405 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 243710313 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243662711 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 47602 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40470990 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15220415 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 429980 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 381705 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6754845 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10370790 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6781090 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1064335 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1313359 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49665444 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1039347 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63215993 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 96269 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10485149 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26517521 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 261916 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77638963 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.814230 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.519509 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77992242 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.032287 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.202184 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16701716 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49328258 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9693840 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 556609 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1709696 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1049154 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91765 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56812427 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 306906 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1709696 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17642458 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18978880 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27077809 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9239108 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3342271 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53967560 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13437 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 629408 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2165949 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 513 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 56184131 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 245540949 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 245492809 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48140 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40778039 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15406092 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 434005 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 385260 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6805574 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10494917 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6795022 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1080492 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1313371 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50078322 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1031134 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63522685 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 99823 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10628436 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26923896 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 250828 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77992242 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.814474 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519995 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54786055 70.57% 70.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7213649 9.29% 79.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3700645 4.77% 84.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3137751 4.04% 88.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6288496 8.10% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1404757 1.81% 98.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 809185 1.04% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 232478 0.30% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 65947 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55011307 70.53% 70.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7277871 9.33% 79.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3728534 4.78% 84.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3132981 4.02% 88.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6315907 8.10% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1400012 1.80% 98.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 822343 1.05% 99.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 235239 0.30% 99.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 68048 0.09% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77638963 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77992242 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29964 0.67% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 4 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4227609 94.71% 95.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 206392 4.62% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 33040 0.74% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4225834 94.61% 95.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207543 4.65% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195815 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29964622 47.40% 47.71% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46968 0.07% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1209 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26783752 42.37% 90.16% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6223613 9.84% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 193689 0.30% 0.30% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 30176884 47.51% 47.81% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47977 0.08% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1219 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26869653 42.30% 90.19% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6233244 9.81% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63215993 # Type of FU issued -system.cpu0.iq.rate 0.264557 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4463969 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070615 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208668164 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61198847 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44188793 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12222 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6485 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5502 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67477689 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6458 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 323157 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63522685 # Type of FU issued +system.cpu0.iq.rate 0.265697 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4466420 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070312 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 209641938 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61746831 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44505201 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12130 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6615 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5501 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67789033 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6383 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 329345 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2276582 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3606 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15957 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 887836 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2321629 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3668 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16120 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 899548 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17155494 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367481 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17127140 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367757 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1684026 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14200734 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 233893 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50821833 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107458 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10370790 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6781090 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 738100 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 56554 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3388 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15957 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 188011 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 147687 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 335698 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62040059 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26425172 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1175934 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1709696 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14213295 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 236264 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 51235944 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105063 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10494917 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6795022 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 726682 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 58301 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3691 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16120 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 190260 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 151203 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 341463 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62339008 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26506413 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1183677 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117042 # number of nop insts executed -system.cpu0.iew.exec_refs 32592128 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6029174 # Number of branches executed -system.cpu0.iew.exec_stores 6166956 # Number of stores executed -system.cpu0.iew.exec_rate 0.259636 # Inst execution rate -system.cpu0.iew.wb_sent 61509785 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44194295 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24341972 # num instructions producing a value -system.cpu0.iew.wb_consumers 44715542 # num instructions consuming a value +system.cpu0.iew.exec_nop 126488 # number of nop insts executed +system.cpu0.iew.exec_refs 32682490 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6088882 # Number of branches executed +system.cpu0.iew.exec_stores 6176077 # Number of stores executed +system.cpu0.iew.exec_rate 0.260746 # Inst execution rate +system.cpu0.iew.wb_sent 61801058 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44510702 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24520944 # num instructions producing a value +system.cpu0.iew.wb_consumers 44899908 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184952 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544374 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.186175 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.546125 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10343604 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 777431 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 292475 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75954937 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.526454 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.509299 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10516243 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 780306 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 297973 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 76282546 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.527732 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.509463 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61716542 81.25% 81.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6915967 9.11% 90.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2042261 2.69% 93.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1137231 1.50% 94.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1037452 1.37% 95.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 547322 0.72% 96.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 703732 0.93% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 369670 0.49% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1484760 1.95% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61930092 81.19% 81.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6958991 9.12% 90.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2075873 2.72% 93.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1156776 1.52% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1044437 1.37% 95.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 552027 0.72% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 702446 0.92% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 372143 0.49% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1489761 1.95% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75954937 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31329293 # Number of instructions committed -system.cpu0.commit.committedOps 39986762 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 76282546 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31604949 # Number of instructions committed +system.cpu0.commit.committedOps 40256713 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13987462 # Number of memory references committed -system.cpu0.commit.loads 8094208 # Number of loads committed -system.cpu0.commit.membars 212609 # Number of memory barriers committed -system.cpu0.commit.branches 5213704 # Number of branches committed -system.cpu0.commit.fp_insts 5481 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35328328 # Number of committed integer instructions. -system.cpu0.commit.function_calls 514863 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1484760 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14068762 # Number of memory references committed +system.cpu0.commit.loads 8173288 # Number of loads committed +system.cpu0.commit.membars 214624 # Number of memory barriers committed +system.cpu0.commit.branches 5267155 # Number of branches committed +system.cpu0.commit.fp_insts 5449 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35547917 # Number of committed integer instructions. +system.cpu0.commit.function_calls 518151 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1489761 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123824951 # The number of ROB reads -system.cpu0.rob.rob_writes 102387078 # The number of ROB writes -system.cpu0.timesIdled 884056 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161311393 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289794473 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31249850 # Number of Instructions Simulated -system.cpu0.committedOps 39907319 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31249850 # Number of Instructions Simulated -system.cpu0.cpi 7.646448 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.646448 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130780 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130780 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 280856495 # number of integer regfile reads -system.cpu0.int_regfile_writes 45466199 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22714 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19802 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15537514 # number of misc regfile reads -system.cpu0.misc_regfile_writes 430329 # number of misc regfile writes -system.cpu0.icache.replacements 983581 # number of replacements -system.cpu0.icache.tagsinuse 511.609112 # Cycle average of tags in use -system.cpu0.icache.total_refs 11036717 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984093 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.215116 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 356.975852 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 154.633260 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.697218 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.302018 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999237 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5578101 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5458616 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11036717 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5578101 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5458616 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11036717 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5578101 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5458616 # number of overall hits -system.cpu0.icache.overall_hits::total 11036717 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 541391 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 523221 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1064612 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 541391 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 523221 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1064612 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 541391 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 523221 # number of overall misses -system.cpu0.icache.overall_misses::total 1064612 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7337521992 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6947086995 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14284608987 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7337521992 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6947086995 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14284608987 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7337521992 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6947086995 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14284608987 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6119492 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5981837 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12101329 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6119492 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5981837 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12101329 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6119492 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5981837 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12101329 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088470 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087468 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.087975 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088470 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087468 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.087975 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088470 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087468 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.087975 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13553.091928 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13277.538545 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13417.666706 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13553.091928 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13277.538545 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13417.666706 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13553.091928 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13277.538545 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13417.666706 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4893 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 347 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.100865 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.rob.rob_reads 124585414 # The number of ROB reads +system.cpu0.rob.rob_writes 103297804 # The number of ROB writes +system.cpu0.timesIdled 884994 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161087173 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289793652 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31519096 # Number of Instructions Simulated +system.cpu0.committedOps 40170860 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31519096 # Number of Instructions Simulated +system.cpu0.cpi 7.585224 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.585224 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.131835 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.131835 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 282333154 # number of integer regfile reads +system.cpu0.int_regfile_writes 45811922 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22666 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19880 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15681131 # number of misc regfile reads +system.cpu0.misc_regfile_writes 434463 # number of misc regfile writes +system.cpu0.icache.replacements 984470 # number of replacements +system.cpu0.icache.tagsinuse 511.608417 # Cycle average of tags in use +system.cpu0.icache.total_refs 11039436 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984982 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.207754 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6537508000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 358.593548 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 153.014869 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.700378 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.298857 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999235 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5636954 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5402482 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11039436 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5636954 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5402482 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11039436 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5636954 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5402482 # number of overall hits +system.cpu0.icache.overall_hits::total 11039436 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 544416 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 521534 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1065950 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 544416 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 521534 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1065950 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 544416 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 521534 # number of overall misses +system.cpu0.icache.overall_misses::total 1065950 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7382097491 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6930257996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14312355487 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7382097491 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6930257996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14312355487 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7382097491 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6930257996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14312355487 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6181370 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5924016 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12105386 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6181370 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5924016 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12105386 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6181370 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5924016 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12105386 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088074 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.088037 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.088056 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088074 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.088037 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.088056 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088074 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.088037 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.088056 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13559.662999 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13288.218977 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13426.854437 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13559.662999 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13288.218977 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13426.854437 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13559.662999 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13288.218977 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13426.854437 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5254 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 847 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 386 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.611399 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 847 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41083 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39415 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80498 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 41083 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39415 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 80498 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 41083 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39415 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80498 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 500308 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 483806 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984114 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 500308 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 483806 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984114 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 500308 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 483806 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984114 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5984214993 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5663833496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11648048489 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5984214993 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5663833496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11648048489 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5984214993 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5663833496 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11648048489 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41493 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39456 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 80949 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 41493 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39456 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 80949 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 41493 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39456 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 80949 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 502923 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 482078 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 985001 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 502923 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 482078 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 985001 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 502923 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 482078 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 985001 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6018484991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5644614996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11663099987 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6018484991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5644614996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11663099987 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6018484991 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5644614996 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11663099987 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7527500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7527500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7527500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7527500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081756 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080879 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081323 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081756 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080879 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.081323 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081756 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080879 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.081323 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11961.061972 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11706.827728 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11836.076399 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11961.061972 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11706.827728 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11836.076399 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11961.061972 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11706.827728 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11836.076399 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081361 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081377 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081369 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081361 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081377 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.081369 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081361 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081377 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.081369 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.010837 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11708.924689 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11840.698626 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.010837 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11708.924689 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11840.698626 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.010837 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11708.924689 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11840.698626 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643901 # number of replacements -system.cpu0.dcache.tagsinuse 511.992715 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21533518 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 644413 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.415710 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 643418 # number of replacements +system.cpu0.dcache.tagsinuse 511.992721 # Cycle average of tags in use +system.cpu0.dcache.total_refs 21533730 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 643930 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.441104 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 318.189291 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 193.803424 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.621463 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.378522 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 319.254285 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 192.738436 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.623544 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.376442 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7127084 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6650362 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13777446 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3774490 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3487348 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261838 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125952 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117576 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243528 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127946 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119673 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247619 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10901574 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10137710 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21039284 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10901574 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10137710 # number of overall hits -system.cpu0.dcache.overall_hits::total 21039284 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 437179 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 313532 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 750711 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1386171 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1574804 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2960975 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6802 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6759 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13561 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7222864 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6555051 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13777915 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3783291 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3477957 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261248 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 126614 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117265 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243879 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 128750 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 118867 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247617 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11006155 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10033008 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21039163 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11006155 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10033008 # number of overall hits +system.cpu0.dcache.overall_hits::total 21039163 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 443968 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 305583 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 749551 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1380597 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1580939 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2961536 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6950 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6643 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13593 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1823350 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1888336 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3711686 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1823350 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1888336 # number of overall misses -system.cpu0.dcache.overall_misses::total 3711686 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6487702500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4845715000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11333417500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52314948357 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 62070901782 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114385850139 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91825500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94465000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 186290500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1824565 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1886522 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3711087 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1824565 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1886522 # number of overall misses +system.cpu0.dcache.overall_misses::total 3711087 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6592316000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4802887000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11395203000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52073406352 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 62127905305 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 114201311657 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94083500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 92681000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 186764500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 39000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 65000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 155000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 58802650857 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 66916616782 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125719267639 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 58802650857 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 66916616782 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125719267639 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7564263 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6963894 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14528157 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5160661 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5062152 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10222813 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132754 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124335 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257089 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127952 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119678 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247630 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12724924 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12026046 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24750970 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12724924 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12026046 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24750970 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057795 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045023 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051673 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.268603 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.311094 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289644 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051238 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054361 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052748 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000047 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_latency::total 104000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 58665722352 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 66930792305 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 125596514657 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 58665722352 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 66930792305 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 125596514657 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7666832 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6860634 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14527466 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5163888 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5058896 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10222784 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 133564 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123908 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 257472 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 128753 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 118872 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247625 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12830720 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11919530 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24750250 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12830720 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11919530 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24750250 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057908 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.044542 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051595 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.267356 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.312507 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289700 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052035 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.053612 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052794 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000023 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000042 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143290 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.157021 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149961 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143290 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.157021 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149961 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14839.922549 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15455.248587 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15096.911461 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37740.616675 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39415.001347 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38631.143505 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13499.779477 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13976.179908 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13737.224393 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000032 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.142203 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.158272 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.149941 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.142203 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.158272 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.149941 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14848.628730 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15717.127589 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15202.705353 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37718.035279 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39298.104041 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38561.513909 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13537.194245 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13951.678459 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13739.755757 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14090.909091 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32249.787949 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35436.816743 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33871.202370 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32249.787949 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35436.816743 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33871.202370 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 36391 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 16051 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3543 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 264 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.271239 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 60.799242 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32153.265218 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35478.405396 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33843.592095 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32153.265218 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35478.405396 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33843.592095 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 34838 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 14844 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3534 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 260 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.857951 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 57.092308 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608422 # number of writebacks -system.cpu0.dcache.writebacks::total 608422 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 222914 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 141593 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 364507 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1266986 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1445051 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2712037 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 671 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 680 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1351 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1489900 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1586644 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3076544 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1489900 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1586644 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3076544 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 214265 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 171939 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386204 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119185 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129753 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248938 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6131 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6079 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12210 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 607829 # number of writebacks +system.cpu0.dcache.writebacks::total 607829 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 226509 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 137269 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 363778 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1261567 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1451066 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2712633 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 696 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 699 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1395 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1488076 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1588335 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3076411 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1488076 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1588335 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3076411 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 217459 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 168314 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 385773 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119030 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129873 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248903 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6254 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5944 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12198 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 333450 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 301692 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 635142 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 333450 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 301692 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 635142 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2906449500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2315533500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5221983000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3953585991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4507381433 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8460967424 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71518000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74200000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145718000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 336489 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 298187 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 634676 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 336489 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 298187 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 634676 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2948842500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2284266500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5233109000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3938983490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4499310442 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8438293932 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73127000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72549000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145676000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 33000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 133000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6860035491 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6822914933 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13682950424 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6860035491 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6822914933 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13682950424 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91872733500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90487640000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182360373500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14914514407 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18644008670 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33558523077 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 88000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6887825990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6783576942 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13671402932 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6887825990 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6783576942 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13671402932 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91735466000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90620432500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182355898500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14921149436 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18671847220 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33592996656 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106787247907 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109131648670 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215918896577 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028326 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024690 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026583 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023095 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025632 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024351 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046183 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048892 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047493 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000047 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106656615436 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109292279720 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215948895156 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028364 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024533 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026555 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023050 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025672 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024348 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046824 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047971 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047376 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000023 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025087 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025661 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025087 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025661 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13564.742258 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13467.180221 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13521.307392 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33171.842019 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34738.167387 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33988.251790 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.981243 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12205.954927 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11934.316134 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026225 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025017 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025643 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026225 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025017 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025643 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13560.452775 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13571.458702 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13565.254696 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33092.358985 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34643.924773 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33901.937429 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11692.836585 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12205.417227 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11942.613543 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12090.909091 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20572.905956 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22615.498366 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21543.135903 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20572.905956 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22615.498366 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21543.135903 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20469.691402 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22749.405380 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21540.759272 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20469.691402 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22749.405380 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21540.759272 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1322,324 +1310,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7016100 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5626613 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 342958 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4632911 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3801004 # Number of BTB hits +system.cpu1.branchPred.lookups 6924581 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5562771 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 336228 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4476731 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3769892 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 82.043536 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 670740 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35021 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.210823 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 665809 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34604 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25297638 # DTB read hits -system.cpu1.dtb.read_misses 36209 # DTB read misses -system.cpu1.dtb.write_hits 5817747 # DTB write hits -system.cpu1.dtb.write_misses 9250 # DTB write misses +system.cpu1.dtb.read_hits 25217799 # DTB read hits +system.cpu1.dtb.read_misses 35648 # DTB read misses +system.cpu1.dtb.write_hits 5810779 # DTB write hits +system.cpu1.dtb.write_misses 9529 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 669 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5517 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1319 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5398 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1388 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 230 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 648 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25333847 # DTB read accesses -system.cpu1.dtb.write_accesses 5826997 # DTB write accesses +system.cpu1.dtb.perms_faults 634 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25253447 # DTB read accesses +system.cpu1.dtb.write_accesses 5820308 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31115385 # DTB hits -system.cpu1.dtb.misses 45459 # DTB misses -system.cpu1.dtb.accesses 31160844 # DTB accesses -system.cpu1.itb.inst_hits 5983825 # ITB inst hits -system.cpu1.itb.inst_misses 6876 # ITB inst misses +system.cpu1.dtb.hits 31028578 # DTB hits +system.cpu1.dtb.misses 45177 # DTB misses +system.cpu1.dtb.accesses 31073755 # DTB accesses +system.cpu1.itb.inst_hits 5925943 # ITB inst hits +system.cpu1.itb.inst_misses 6573 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 669 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2607 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2476 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1422 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1382 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5990701 # ITB inst accesses -system.cpu1.itb.hits 5983825 # DTB hits -system.cpu1.itb.misses 6876 # DTB misses -system.cpu1.itb.accesses 5990701 # DTB accesses -system.cpu1.numCycles 234271094 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5932516 # ITB inst accesses +system.cpu1.itb.hits 5925943 # DTB hits +system.cpu1.itb.misses 6573 # DTB misses +system.cpu1.itb.accesses 5932516 # DTB accesses +system.cpu1.numCycles 234244847 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15106075 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46495215 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7016100 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4471744 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10263244 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2607774 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 83065 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47539930 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 913 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2033 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 42850 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 94637 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 151 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5981839 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 442153 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2974 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74917861 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.771750 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.136158 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15045426 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46051404 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 6924581 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4435701 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10180178 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2576164 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 79323 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47488838 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 962 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2036 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 40665 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94257 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 230 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5924019 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 441347 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2911 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74691954 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.768024 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.131487 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64662198 86.31% 86.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 618220 0.83% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 830780 1.11% 88.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1202992 1.61% 89.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1054171 1.41% 91.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 533923 0.71% 91.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1365534 1.82% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 350745 0.47% 94.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4299298 5.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64519001 86.38% 86.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 606919 0.81% 87.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 824654 1.10% 88.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1190723 1.59% 89.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1057088 1.42% 91.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 528345 0.71% 92.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1354186 1.81% 93.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 346670 0.46% 94.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4264368 5.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74917861 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.029949 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.198468 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16114785 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47334136 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9307437 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 457642 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1701687 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 943149 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85752 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54765911 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286536 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1701687 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17049791 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18574833 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25739106 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8750674 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3099680 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51604165 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7083 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 481938 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2120083 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 47 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53629483 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 236928405 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 236886159 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42246 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 37922365 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15707117 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 402858 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 356707 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6241200 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9820106 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6689053 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 876297 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1123238 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47543883 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 946480 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60738625 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 81609 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10509389 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 27830287 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 241377 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74917861 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.810736 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521004 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74691954 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.029561 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.196595 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16048040 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47278235 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9237318 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 448383 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1677844 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 921418 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 84751 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54328734 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 282420 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1677844 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16980429 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18581446 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25685933 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8674589 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3089642 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51185611 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7172 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 483859 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2112197 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 97 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53156547 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 235159359 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 235117285 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42074 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 37614805 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15541741 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 399062 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 353498 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6213195 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9696990 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6683769 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 865241 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1058674 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47161259 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 954916 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60450494 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 77232 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10409443 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27466585 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 252722 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74691954 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.809331 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.520957 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53210773 71.03% 71.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6641164 8.86% 79.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3529295 4.71% 84.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2876551 3.84% 88.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6221124 8.30% 96.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1436861 1.92% 98.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 733077 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 210173 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 58843 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53120438 71.12% 71.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6581682 8.81% 79.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3495899 4.68% 84.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2849080 3.81% 88.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6224305 8.33% 96.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1417719 1.90% 98.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 735156 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 208377 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59298 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74917861 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74691954 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24144 0.55% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4145479 94.86% 95.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 200357 4.58% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 25658 0.59% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4148051 94.78% 95.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 202723 4.63% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 167851 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28384328 46.73% 47.01% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46613 0.08% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 903 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26029174 42.85% 89.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6109728 10.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 169977 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28184247 46.62% 46.90% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45636 0.08% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 4 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 892 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.98% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 25945360 42.92% 89.90% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6104366 10.10% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60738625 # Type of FU issued -system.cpu1.iq.rate 0.259266 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4369980 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071947 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 200881299 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59008077 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41690782 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10661 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5857 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4774 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 64935130 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5624 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 302237 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60450494 # Type of FU issued +system.cpu1.iq.rate 0.258065 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4376432 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072397 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 200080953 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58533998 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41393677 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10638 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5781 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4780 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 64651317 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5632 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 296486 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2258994 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3096 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14702 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 849711 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2215043 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3144 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14677 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 846684 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16948413 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 457547 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16976661 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 457892 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1701687 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13992381 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229468 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48596033 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98735 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9820106 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6689053 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 673721 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49557 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3683 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14702 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 165794 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 132525 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 298319 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59364884 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25624684 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1373741 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1677844 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14002380 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 233104 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48212114 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 96608 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9696990 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6683769 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 685390 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50588 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3685 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14677 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 163070 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 129112 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 292182 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59083319 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25544592 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1367175 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105670 # number of nop insts executed -system.cpu1.iew.exec_refs 31682928 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5509079 # Number of branches executed -system.cpu1.iew.exec_stores 6058244 # Number of stores executed -system.cpu1.iew.exec_rate 0.253403 # Inst execution rate -system.cpu1.iew.wb_sent 58786539 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41695556 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22722145 # num instructions producing a value -system.cpu1.iew.wb_consumers 41696703 # num instructions consuming a value +system.cpu1.iew.exec_nop 95939 # number of nop insts executed +system.cpu1.iew.exec_refs 31597721 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5452623 # Number of branches executed +system.cpu1.iew.exec_stores 6053129 # Number of stores executed +system.cpu1.iew.exec_rate 0.252229 # Inst execution rate +system.cpu1.iew.wb_sent 58512296 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41398457 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22553116 # num instructions producing a value +system.cpu1.iew.wb_consumers 41520902 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.177980 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.544939 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.176732 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.543175 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10421777 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 705103 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 258416 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73216174 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.515817 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.496135 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10281991 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 702194 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 252752 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73014110 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.513541 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.493879 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59718106 81.56% 81.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6653283 9.09% 90.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1904372 2.60% 93.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1008936 1.38% 94.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 956792 1.31% 95.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 521917 0.71% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 703785 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 374006 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1374977 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59627220 81.67% 81.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6596697 9.03% 90.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1882997 2.58% 93.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 995941 1.36% 94.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 953813 1.31% 95.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 518436 0.71% 96.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 701051 0.96% 97.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 372117 0.51% 98.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1365838 1.87% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73216174 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29131232 # Number of instructions committed -system.cpu1.commit.committedOps 37766156 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73014110 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 28855252 # Number of instructions committed +system.cpu1.commit.committedOps 37495775 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13400454 # Number of memory references committed -system.cpu1.commit.loads 7561112 # Number of loads committed -system.cpu1.commit.membars 191037 # Number of memory barriers committed -system.cpu1.commit.branches 4747981 # Number of branches committed -system.cpu1.commit.fp_insts 4731 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33529515 # Number of committed integer instructions. -system.cpu1.commit.function_calls 476457 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1374977 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13319032 # Number of memory references committed +system.cpu1.commit.loads 7481947 # Number of loads committed +system.cpu1.commit.membars 189014 # Number of memory barriers committed +system.cpu1.commit.branches 4694468 # Number of branches committed +system.cpu1.commit.fp_insts 4763 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33309565 # Number of committed integer instructions. +system.cpu1.commit.function_calls 473164 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1365838 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119155388 # The number of ROB reads -system.cpu1.rob.rob_writes 98129561 # The number of ROB writes -system.cpu1.timesIdled 872896 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159353233 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285655752 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29060294 # Number of Instructions Simulated -system.cpu1.committedOps 37695218 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29060294 # Number of Instructions Simulated -system.cpu1.cpi 8.061553 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.061553 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124046 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124046 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 268946784 # number of integer regfile reads -system.cpu1.int_regfile_writes 42787312 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22150 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19734 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14724221 # number of misc regfile reads -system.cpu1.misc_regfile_writes 402169 # number of misc regfile writes +system.cpu1.rob.rob_reads 118557028 # The number of ROB reads +system.cpu1.rob.rob_writes 97285221 # The number of ROB writes +system.cpu1.timesIdled 872406 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159552893 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285658129 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 28790724 # Number of Instructions Simulated +system.cpu1.committedOps 37431247 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 28790724 # Number of Instructions Simulated +system.cpu1.cpi 8.136122 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.136122 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.122909 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.122909 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 267548470 # number of integer regfile reads +system.cpu1.int_regfile_writes 42457075 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22098 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19630 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14600078 # number of misc regfile reads +system.cpu1.misc_regfile_writes 398004 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1654,10 +1642,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192686110607 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192686110607 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192686110607 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192686110607 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192831582801 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192831582801 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192831582801 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192831582801 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |