diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | 3622 |
1 files changed, 1787 insertions, 1835 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 7a8eccd80..1944dbbec 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,156 +1,164 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.550461 # Number of seconds simulated -sim_ticks 2550460850000 # Number of ticks simulated -final_tick 2550460850000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.550456 # Number of seconds simulated +sim_ticks 2550455693500 # Number of ticks simulated +final_tick 2550455693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71467 # Simulator instruction rate (inst/s) -host_op_rate 91959 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3022122690 # Simulator tick rate (ticks/s) -host_mem_usage 427404 # Number of bytes of host memory used -host_seconds 843.93 # Real time elapsed on the host -sim_insts 60313440 # Number of instructions simulated -sim_ops 77607116 # Number of ops (including micro ops) simulated +host_inst_rate 59744 # Simulator instruction rate (inst/s) +host_op_rate 76873 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2526372396 # Simulator tick rate (ticks/s) +host_mem_usage 427472 # Number of bytes of host memory used +host_seconds 1009.53 # Real time elapsed on the host +sim_insts 60313472 # Number of instructions simulated +sim_ops 77606209 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 504512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5067800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 293824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4027288 # Number of bytes read from this memory -system.physmem.bytes_read::total 131006896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 504512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 293824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786560 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521444 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494656 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802660 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 504320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5079000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 295488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4015064 # Number of bytes read from this memory +system.physmem.bytes_read::total 131007536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 504320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 295488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786368 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1520720 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1495380 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802468 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7883 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 79220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4591 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 62932 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293488 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59165 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380361 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373664 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813190 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47485743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7880 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 79395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 62741 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293498 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59162 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380180 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373845 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813187 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47485839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 853 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 197812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1987013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 115204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1579043 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51365970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 197812 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 115204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313016 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596537 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586034 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2667228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47485743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 197737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1991409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 115857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1574254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51366325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 197737 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 115857 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484585 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596254 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586319 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2667158 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47485839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 853 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 197812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2583550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 115204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2165077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54033198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293488 # Number of read requests accepted -system.physmem.writeReqs 813190 # Number of write requests accepted -system.physmem.readBursts 15293488 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813190 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978237376 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 545856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6910336 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131006896 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6802660 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8529 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705216 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4690 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955874 # Per bank write bursts -system.physmem.perBankRdBursts::1 955460 # Per bank write bursts -system.physmem.perBankRdBursts::2 954683 # Per bank write bursts -system.physmem.perBankRdBursts::3 954757 # Per bank write bursts -system.physmem.perBankRdBursts::4 955767 # Per bank write bursts -system.physmem.perBankRdBursts::5 955952 # Per bank write bursts -system.physmem.perBankRdBursts::6 954810 # Per bank write bursts -system.physmem.perBankRdBursts::7 954709 # Per bank write bursts -system.physmem.perBankRdBursts::8 956270 # Per bank write bursts -system.physmem.perBankRdBursts::9 955934 # Per bank write bursts -system.physmem.perBankRdBursts::10 954560 # Per bank write bursts -system.physmem.perBankRdBursts::11 953973 # Per bank write bursts -system.physmem.perBankRdBursts::12 956221 # Per bank write bursts -system.physmem.perBankRdBursts::13 955978 # Per bank write bursts -system.physmem.perBankRdBursts::14 955151 # Per bank write bursts -system.physmem.perBankRdBursts::15 954860 # Per bank write bursts -system.physmem.perBankWrBursts::0 6693 # Per bank write bursts -system.physmem.perBankWrBursts::1 6460 # Per bank write bursts -system.physmem.perBankWrBursts::2 6602 # Per bank write bursts -system.physmem.perBankWrBursts::3 6635 # Per bank write bursts -system.physmem.perBankWrBursts::4 6566 # Per bank write bursts -system.physmem.perBankWrBursts::5 6824 # Per bank write bursts -system.physmem.perBankWrBursts::6 6825 # Per bank write bursts -system.physmem.perBankWrBursts::7 6757 # Per bank write bursts -system.physmem.perBankWrBursts::8 7131 # Per bank write bursts -system.physmem.perBankWrBursts::9 6880 # Per bank write bursts -system.physmem.perBankWrBursts::10 6546 # Per bank write bursts -system.physmem.perBankWrBursts::11 6195 # Per bank write bursts -system.physmem.perBankWrBursts::12 7145 # Per bank write bursts -system.physmem.perBankWrBursts::13 6763 # Per bank write bursts -system.physmem.perBankWrBursts::14 7046 # Per bank write bursts -system.physmem.perBankWrBursts::15 6906 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 197737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2587663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 115857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2160572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54033483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293498 # Number of read requests accepted +system.physmem.writeReqs 813187 # Number of write requests accepted +system.physmem.readBursts 15293498 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813187 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978241024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 542848 # Total number of bytes read from write queue +system.physmem.bytesWritten 6911808 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131007536 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6802468 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8482 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705190 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955869 # Per bank write bursts +system.physmem.perBankRdBursts::1 955539 # Per bank write bursts +system.physmem.perBankRdBursts::2 954667 # Per bank write bursts +system.physmem.perBankRdBursts::3 954789 # Per bank write bursts +system.physmem.perBankRdBursts::4 955759 # Per bank write bursts +system.physmem.perBankRdBursts::5 955951 # Per bank write bursts +system.physmem.perBankRdBursts::6 954859 # Per bank write bursts +system.physmem.perBankRdBursts::7 954668 # Per bank write bursts +system.physmem.perBankRdBursts::8 956272 # Per bank write bursts +system.physmem.perBankRdBursts::9 955769 # Per bank write bursts +system.physmem.perBankRdBursts::10 954516 # Per bank write bursts +system.physmem.perBankRdBursts::11 954114 # Per bank write bursts +system.physmem.perBankRdBursts::12 956222 # Per bank write bursts +system.physmem.perBankRdBursts::13 955973 # Per bank write bursts +system.physmem.perBankRdBursts::14 955087 # Per bank write bursts +system.physmem.perBankRdBursts::15 954962 # Per bank write bursts +system.physmem.perBankWrBursts::0 6687 # Per bank write bursts +system.physmem.perBankWrBursts::1 6466 # Per bank write bursts +system.physmem.perBankWrBursts::2 6605 # Per bank write bursts +system.physmem.perBankWrBursts::3 6628 # Per bank write bursts +system.physmem.perBankWrBursts::4 6579 # Per bank write bursts +system.physmem.perBankWrBursts::5 6834 # Per bank write bursts +system.physmem.perBankWrBursts::6 6823 # Per bank write bursts +system.physmem.perBankWrBursts::7 6763 # Per bank write bursts +system.physmem.perBankWrBursts::8 7134 # Per bank write bursts +system.physmem.perBankWrBursts::9 6882 # Per bank write bursts +system.physmem.perBankWrBursts::10 6543 # Per bank write bursts +system.physmem.perBankWrBursts::11 6191 # Per bank write bursts +system.physmem.perBankWrBursts::12 7147 # Per bank write bursts +system.physmem.perBankWrBursts::13 6760 # Per bank write bursts +system.physmem.perBankWrBursts::14 7044 # Per bank write bursts +system.physmem.perBankWrBursts::15 6911 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2550459728500 # Total gap between requests +system.physmem.totGap 2550454486000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 44 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154628 # Read request sizes (log2) +system.physmem.readPktSize::6 154638 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754025 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59165 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1189211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1129031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1083368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3689725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2647408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2642045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2653706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 51340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59162 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1173632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1113468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1067801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3688063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2661485 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2656312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2669345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 52900 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see @@ -165,31 +173,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5216 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 5378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4744 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 4738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -197,394 +205,389 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86806 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11348.833952 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1015.155739 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16835.722240 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23589 27.17% 27.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14167 16.32% 43.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2667 3.07% 46.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2091 2.41% 48.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1355 1.56% 50.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1138 1.31% 51.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 864 1.00% 52.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1120 1.29% 54.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 549 0.63% 54.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 610 0.70% 55.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 512 0.59% 56.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 456 0.53% 56.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 243 0.28% 56.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 296 0.34% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 156 0.18% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 592 0.68% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 118 0.14% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 142 0.16% 58.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 67 0.08% 58.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 249 0.29% 58.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 52 0.06% 58.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 529 0.61% 59.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 292 0.34% 59.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 23 0.03% 59.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 99 0.11% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 19 0.02% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 187 0.22% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 47 0.05% 60.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 18 0.02% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 308 0.35% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 8 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 37 0.04% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 15 0.02% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 167 0.19% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 7 0.01% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 23 0.03% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 12 0.01% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 29 0.03% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 15 0.02% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 19 0.02% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 10 0.01% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 208 0.24% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 13 0.01% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 29 0.03% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 6 0.01% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 407 0.47% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 12 0.01% 61.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 20 0.02% 61.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 80 0.09% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 11 0.01% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 13 0.01% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 7 0.01% 61.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 84 0.10% 62.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 10 0.01% 62.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 19 0.02% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 9 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 152 0.18% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 9 0.01% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 349 0.40% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 12 0.01% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 10 0.01% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 13 0.01% 62.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 21 0.02% 62.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 11 0.01% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11341.188281 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1014.168764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16824.493217 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23628 27.20% 27.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14156 16.30% 43.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2700 3.11% 46.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2166 2.49% 49.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1318 1.52% 50.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1170 1.35% 51.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 896 1.03% 52.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 913 1.05% 54.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 566 0.65% 54.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 606 0.70% 55.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 521 0.60% 55.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 631 0.73% 56.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 271 0.31% 57.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 267 0.31% 57.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 154 0.18% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 590 0.68% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 110 0.13% 58.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 147 0.17% 58.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 73 0.08% 58.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 151 0.17% 58.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 55 0.06% 58.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 532 0.61% 59.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 32 0.04% 59.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 226 0.26% 59.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 18 0.02% 59.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 114 0.13% 59.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 25 0.03% 59.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 112 0.13% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 26 0.03% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 51 0.06% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 19 0.02% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 424 0.49% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 10 0.01% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 29 0.03% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 12 0.01% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 47 0.05% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 15 0.02% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 23 0.03% 60.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 12 0.01% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 153 0.18% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 13 0.01% 60.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 8 0.01% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 30 0.03% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 14 0.02% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 22 0.03% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 8 0.01% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 344 0.40% 61.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 8 0.01% 61.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 12 0.01% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 150 0.17% 61.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 12 0.01% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 8 0.01% 61.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 14 0.02% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 136 0.16% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 11 0.01% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 13 0.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 10 0.01% 61.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 83 0.10% 62.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 12 0.01% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 470 0.54% 62.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 7 0.01% 62.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 13 0.01% 62.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 83 0.10% 62.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 13 0.01% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 10 0.01% 62.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::4544-4551 11 0.01% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 184 0.21% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 10 0.01% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 12 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 8 0.01% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 5 0.01% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 12 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 6 0.01% 63.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 273 0.31% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 7 0.01% 63.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 11 0.01% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 14 0.02% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 208 0.24% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 14 0.02% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 7 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 73 0.08% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 5 0.01% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 17 0.02% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 9 0.01% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 138 0.16% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 3 0.00% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 13 0.01% 64.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 5 0.01% 64.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 459 0.53% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 4 0.00% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 6 0.01% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 9 0.01% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 3 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 10 0.01% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 6 0.01% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 12 0.01% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 10 0.01% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 19 0.02% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 4 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 133 0.15% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 6 0.01% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 4 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 263 0.30% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 10 0.01% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 11 0.01% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 14 0.02% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 26 0.03% 65.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 7 0.01% 65.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 188 0.22% 65.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 3 0.00% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 68 0.08% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 5 0.01% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 6 0.01% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8135 2 0.00% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 602 0.69% 66.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 64 0.07% 66.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 184 0.21% 66.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 4 0.00% 66.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9159 1 0.00% 66.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 261 0.30% 66.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 128 0.15% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 2 0.00% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 3 0.00% 66.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 4 0.00% 66.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 451 0.52% 67.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 68 0.08% 67.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 63 0.07% 67.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 194 0.22% 67.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 1 0.00% 67.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 259 0.30% 68.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 167 0.19% 68.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 5 0.01% 68.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 322 0.37% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 68.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 68.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 135 0.16% 68.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 67 0.08% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 55 0.06% 69.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 384 0.44% 69.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 185 0.21% 69.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13767 1 0.00% 69.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 6 0.01% 69.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 1 0.00% 69.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 126 0.15% 69.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14151 1 0.00% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 1 0.00% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 259 0.30% 70.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 129 0.15% 70.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 129 0.15% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15047 1 0.00% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 124 0.14% 70.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 385 0.44% 71.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 3 0.00% 71.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 129 0.15% 71.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 67 0.08% 71.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 642 0.74% 71.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16455 1 0.00% 71.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 65 0.07% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 128 0.15% 72.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 2 0.00% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 1 0.00% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 384 0.44% 72.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17600-17607 1 0.00% 72.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 123 0.14% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 129 0.15% 72.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 129 0.15% 73.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18375 1 0.00% 73.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 261 0.30% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 126 0.15% 73.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 6 0.01% 73.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 183 0.21% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19264-19271 2 0.00% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 1 0.00% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 384 0.44% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 55 0.06% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 67 0.08% 74.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 132 0.15% 74.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 322 0.37% 74.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 6 0.01% 74.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 169 0.19% 75.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 3 0.00% 75.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 256 0.29% 75.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 195 0.22% 75.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 63 0.07% 75.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 64 0.07% 75.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 449 0.52% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 5 0.01% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 3 0.00% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 129 0.15% 76.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 259 0.30% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23616-23623 1 0.00% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 4 0.00% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23936-23943 1 0.00% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 1 0.00% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 184 0.21% 76.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 65 0.07% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 1 0.00% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 497 0.57% 77.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 65 0.07% 77.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 186 0.21% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 4 0.00% 77.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 259 0.30% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 130 0.15% 78.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 2 0.00% 78.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 6 0.01% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 449 0.52% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 64 0.07% 78.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 61 0.07% 79.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 194 0.22% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 258 0.30% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27719 1 0.00% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 167 0.19% 79.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 2 0.00% 79.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 5 0.01% 79.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 321 0.37% 80.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 130 0.15% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 66 0.08% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29383 1 0.00% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 54 0.06% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 384 0.44% 80.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 186 0.21% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 7 0.01% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 127 0.15% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 260 0.30% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 130 0.15% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 128 0.15% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 1 0.00% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31424-31431 1 0.00% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 123 0.14% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 385 0.44% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 3 0.00% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 128 0.15% 82.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 65 0.07% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 640 0.74% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 65 0.07% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 128 0.15% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 3 0.00% 83.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 386 0.44% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 123 0.14% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 128 0.15% 84.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 130 0.15% 84.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 260 0.30% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 20 0.02% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 11 0.01% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 7 0.01% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 8 0.01% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 151 0.17% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 7 0.01% 63.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 10 0.01% 63.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 397 0.46% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 3 0.00% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 13 0.01% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 7 0.01% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 18 0.02% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 13 0.01% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 9 0.01% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 10 0.01% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 76 0.09% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 6 0.01% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 11 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 5 0.01% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 208 0.24% 63.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 5 0.01% 63.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 13 0.01% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 7 0.01% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 368 0.42% 64.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 3 0.00% 64.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 4 0.00% 64.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 73 0.08% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 2 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 7 0.01% 64.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 137 0.16% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 10 0.01% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 24 0.03% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 2 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 60 0.07% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 5 0.01% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 5 0.01% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 7 0.01% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 270 0.31% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 5 0.01% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 10 0.01% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 9 0.01% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 215 0.25% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 8 0.01% 65.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 21 0.02% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 7 0.01% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 8 0.01% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 2 0.00% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 69 0.08% 65.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 4 0.00% 65.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 6 0.01% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 602 0.69% 66.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8391 1 0.00% 66.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 67 0.08% 66.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 2 0.00% 66.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 203 0.23% 66.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 262 0.30% 66.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9287 1 0.00% 66.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 56 0.06% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 129 0.15% 67.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 65 0.07% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 354 0.41% 67.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 1 0.00% 67.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 132 0.15% 67.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 66 0.08% 67.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 2 0.00% 67.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 377 0.43% 68.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 143 0.16% 68.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 1 0.00% 68.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 65 0.07% 68.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 444 0.51% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 65 0.07% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 1 0.00% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 120 0.14% 69.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 129 0.15% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 321 0.37% 69.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 4 0.00% 69.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 137 0.16% 69.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 1 0.00% 69.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 5 0.01% 69.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14151 1 0.00% 69.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 1 0.00% 69.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 386 0.44% 70.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 64 0.07% 70.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 71 0.08% 70.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 56 0.06% 70.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 70.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 386 0.44% 70.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 121 0.14% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 5 0.01% 71.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 125 0.14% 71.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 641 0.74% 72.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16455 1 0.00% 72.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 72.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 125 0.14% 72.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.15% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 4 0.00% 81.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 385 0.44% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 66 0.08% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 71 0.08% 81.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31296-31303 2 0.00% 81.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 54 0.06% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 385 0.44% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 120 0.14% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 4 0.00% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 124 0.14% 82.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 640 0.74% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 124 0.14% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 4 0.00% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 121 0.14% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 386 0.44% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 54 0.06% 84.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 71 0.08% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 66 0.08% 84.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 384 0.44% 84.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::35008-35015 1 0.00% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 126 0.15% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 8 0.01% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35520-35527 1 0.00% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 185 0.21% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 384 0.44% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 55 0.06% 85.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 67 0.08% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 130 0.15% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 321 0.37% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 5 0.01% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 165 0.19% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 1 0.00% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 258 0.30% 86.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 194 0.22% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 60 0.07% 87.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 64 0.07% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38784-38791 1 0.00% 87.11% # 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Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 65 0.07% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 183 0.21% 89.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 1 0.00% 89.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41664-41671 1 0.00% 89.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 4 0.00% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 258 0.30% 89.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 128 0.15% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 2 0.00% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 4 0.00% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42944-42951 1 0.00% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 450 0.52% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 65 0.07% 90.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43456-43463 1 0.00% 90.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 59 0.07% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 195 0.22% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 257 0.30% 90.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 2 0.00% 90.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 1 0.00% 90.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44352-44359 2 0.00% 90.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 168 0.19% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 1 0.00% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 6 0.01% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 2 0.00% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44992-44999 1 0.00% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 327 0.38% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 131 0.15% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 67 0.08% 91.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 55 0.06% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 386 0.44% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 185 0.21% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 6 0.01% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 126 0.15% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 260 0.30% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 129 0.15% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 130 0.15% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 122 0.14% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 386 0.44% 93.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 1 0.00% 93.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 129 0.15% 93.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 65 0.07% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 2 0.00% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 4 0.00% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 134 0.15% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 5 0.01% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35776-35783 1 0.00% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 321 0.37% 85.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 128 0.15% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 120 0.14% 85.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 65 0.07% 85.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 441 0.51% 86.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 64 0.07% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 1 0.00% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 143 0.16% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37760-37767 1 0.00% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37824-37831 1 0.00% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 377 0.43% 86.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 1 0.00% 86.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38208-38215 1 0.00% 86.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 64 0.07% 86.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38464-38471 1 0.00% 86.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 130 0.15% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 355 0.41% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 66 0.08% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 128 0.15% 87.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 55 0.06% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 261 0.30% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40000-40007 1 0.00% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 203 0.23% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 1 0.00% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 66 0.08% 88.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 496 0.57% 88.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 67 0.08% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41280-41287 1 0.00% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 2 0.00% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 203 0.23% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41920-41927 1 0.00% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 260 0.30% 89.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 55 0.06% 89.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42304-42311 1 0.00% 89.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 128 0.15% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 67 0.08% 89.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42880-42887 1 0.00% 89.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 353 0.41% 90.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 131 0.15% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 65 0.07% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 379 0.44% 90.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 143 0.16% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 2 0.00% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 67 0.08% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 443 0.51% 91.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 67 0.08% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 122 0.14% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 1 0.00% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 130 0.15% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46016-46023 1 0.00% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 322 0.37% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 4 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 131 0.15% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 5 0.01% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 384 0.44% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 64 0.07% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 72 0.08% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 54 0.06% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 385 0.44% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 121 0.14% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48576-48583 1 0.00% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 5 0.01% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48832-48839 1 0.00% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 123 0.14% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 2 0.00% 93.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::49088-49095 1 0.00% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5210 6.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49671 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5211 6.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49536-49543 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50112-50119 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52416-52423 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86806 # Bytes accessed per row activation -system.physmem.totQLat 369546937250 # Total ticks spent queuing -system.physmem.totMemAccLat 463545387250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76424795000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17573655000 # Total ticks spent accessing banks -system.physmem.avgQLat 24177.16 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1149.74 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::51648-51655 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51719 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86865 # Bytes accessed per row activation +system.physmem.totQLat 369784547000 # Total ticks spent queuing +system.physmem.totMemAccLat 463560559500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76425080000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17350932500 # Total ticks spent accessing banks +system.physmem.avgQLat 24192.62 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1135.16 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30326.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30327.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s @@ -594,324 +597,293 @@ system.physmem.busUtilRead 3.00 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing -system.physmem.readRowHits 15213019 # Number of row buffer hits during reads -system.physmem.writeRowHits 93108 # Number of row buffer hits during writes +system.physmem.readRowHits 15213014 # Number of row buffer hits during reads +system.physmem.writeRowHits 93134 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.23 # Row buffer hit rate for writes -system.physmem.avgGap 158347.97 # Average gap between requests +system.physmem.writeRowHitRate 86.24 # Row buffer hit rate for writes +system.physmem.avgGap 158347.57 # Average gap between requests system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 2.65 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54973413 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346095 # Transaction distribution -system.membus.trans_dist::ReadResp 16346098 # Transaction distribution -system.membus.trans_dist::WriteReq 763348 # Transaction distribution -system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59165 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4689 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4690 # Transaction distribution -system.membus.trans_dist::ReadExReq 131440 # Transaction distribution -system.membus.trans_dist::ReadExResp 131440 # Transaction distribution +system.membus.throughput 54973753 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346163 # Transaction distribution +system.membus.trans_dist::ReadResp 16346166 # Transaction distribution +system.membus.trans_dist::WriteReq 763365 # Transaction distribution +system.membus.trans_dist::WriteResp 763365 # Transaction distribution +system.membus.trans_dist::Writeback 59162 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4696 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution +system.membus.trans_dist::ReadExReq 131412 # Transaction distribution +system.membus.trans_dist::ReadExResp 131412 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383052 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272691 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885968 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272814 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550323 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550446 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390470 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16699028 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19097009 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16699476 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19097594 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140207537 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140207537 # Total data (bytes) +system.membus.tot_pkt_size::total 140208122 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140208122 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487746500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487391000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3584500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17566438500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17566049500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4736460824 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4736056592 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34185683234 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34187486731 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64398 # number of replacements -system.l2c.tags.tagsinuse 51440.737713 # Cycle average of tags in use -system.l2c.tags.total_refs 1904463 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129791 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.673306 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2513095359500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36974.659237 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.382027 # Average occupied blocks per requestor +system.l2c.tags.replacements 64408 # number of replacements +system.l2c.tags.tagsinuse 51449.796153 # Cycle average of tags in use +system.l2c.tags.total_refs 1905827 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129798 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.683023 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2540137710500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36969.006628 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 22.725284 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4864.361052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3325.264959 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.733963 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.979227 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3333.561172 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2910.795705 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564189 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000280 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4879.693838 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3326.753767 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.863300 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3332.963946 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2906.789020 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564102 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000347 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074224 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050740 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000194 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.050866 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044415 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784923 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65370 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.074458 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050762 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000181 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.050857 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044354 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.785062 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65368 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 341 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3070 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6833 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55085 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997467 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18926387 # Number of tag accesses -system.l2c.tags.data_accesses 18926387 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 32717 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6688 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65404.248069 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61895.307716 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60132.375676 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61881.625160 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62489.278752 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65121.037138 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62041.944348 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.871418 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.715168 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62155.866596 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61603.993250 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61909.751342 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70741.379310 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.537692 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.686706 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62421.351588 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61492.320361 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62008.251199 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64985.294118 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59796.587250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62176.018321 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 86464.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61866.153720 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61907.619247 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70741.379310 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60132.375676 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62379.214261 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62489.278752 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61744.106312 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62013.232366 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64985.294118 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59796.587250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62176.018321 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 86464.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61866.153720 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61907.619247 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60132.375676 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62379.214261 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62489.278752 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61744.106312 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62013.232366 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1114,49 +1066,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58420424 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676760 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676762 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 607936 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2958 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246118 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246118 # Transaction distribution +system.toL2Bus.throughput 58427801 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677013 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677015 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 607832 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2952 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2962 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246108 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246108 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968062 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796874 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37580 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149966 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7952482 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62939648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85542385 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 54872 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254948 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148791853 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148791853 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 207152 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4962468234 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968942 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796822 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 150646 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7954400 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62968576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85534266 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 56288 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 258652 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148817782 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148817782 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 199736 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4962135725 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4433875230 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4435783766 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4484319469 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4484209498 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23911393 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23967895 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86679578 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86426354 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48422959 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322135 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322135 # Transaction distribution -system.iobus.trans_dist::WriteReq 8160 # Transaction distribution -system.iobus.trans_dist::WriteResp 8160 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48423111 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322165 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322165 # Transaction distribution +system.iobus.trans_dist::WriteReq 8177 # Transaction distribution +system.iobus.trans_dist::WriteResp 8177 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7932 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1178,12 +1130,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383052 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660590 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 32660684 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15864 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1205,14 +1157,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390470 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500861 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500861 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 123500998 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500998 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3971000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1258,19 +1210,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374798000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374875000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41495326766 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41493951269 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7528776 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6012881 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 377531 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4829761 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3930404 # Number of BTB hits +system.cpu0.branchPred.lookups 7524637 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6008547 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 377377 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4829480 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3929632 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.378851 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 724348 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39225 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.367601 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 723615 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39097 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1294,25 +1246,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25731693 # DTB read hits -system.cpu0.dtb.read_misses 40178 # DTB read misses -system.cpu0.dtb.write_hits 6168711 # DTB write hits -system.cpu0.dtb.write_misses 10337 # DTB write misses +system.cpu0.dtb.read_hits 25732063 # DTB read hits +system.cpu0.dtb.read_misses 40060 # DTB read misses +system.cpu0.dtb.write_hits 6173955 # DTB write hits +system.cpu0.dtb.write_misses 10391 # DTB write misses system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 776 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5677 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1369 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 257 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5654 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1384 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 265 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 641 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25771871 # DTB read accesses -system.cpu0.dtb.write_accesses 6179048 # DTB write accesses +system.cpu0.dtb.perms_faults 665 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25772123 # DTB read accesses +system.cpu0.dtb.write_accesses 6184346 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31900404 # DTB hits -system.cpu0.dtb.misses 50515 # DTB misses -system.cpu0.dtb.accesses 31950919 # DTB accesses +system.cpu0.dtb.hits 31906018 # DTB hits +system.cpu0.dtb.misses 50451 # DTB misses +system.cpu0.dtb.accesses 31956469 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1334,664 +1286,664 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5899860 # ITB inst hits -system.cpu0.itb.inst_misses 7207 # ITB inst misses +system.cpu0.itb.inst_hits 5897367 # ITB inst hits +system.cpu0.itb.inst_misses 7084 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 776 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2688 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2660 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1562 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1482 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5907067 # ITB inst accesses -system.cpu0.itb.hits 5899860 # DTB hits -system.cpu0.itb.misses 7207 # DTB misses -system.cpu0.itb.accesses 5907067 # DTB accesses -system.cpu0.numCycles 242297109 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5904451 # ITB inst accesses +system.cpu0.itb.hits 5897367 # DTB hits +system.cpu0.itb.misses 7084 # DTB misses +system.cpu0.itb.accesses 5904451 # DTB accesses +system.cpu0.numCycles 242280954 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15555542 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45617593 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7528776 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4654752 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10311247 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2439507 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 83051 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 50330649 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1691 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2002 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 48587 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1491133 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 722 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5897866 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 368478 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3041 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 79507031 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.722707 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.070799 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15560897 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45618983 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7524637 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4653247 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10311307 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2438027 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 82681 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 50295736 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2004 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 47904 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1479659 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 328 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5895435 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 368728 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2960 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 79463748 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.723138 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.071375 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 69202528 87.04% 87.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 678265 0.85% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 875305 1.10% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1177307 1.48% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1118218 1.41% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 557082 0.70% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1282023 1.61% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 381348 0.48% 94.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4234955 5.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 69159455 87.03% 87.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 678650 0.85% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 874708 1.10% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1176149 1.48% 90.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1117399 1.41% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 558232 0.70% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1283192 1.61% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 380865 0.48% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4235098 5.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79507031 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031072 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.188271 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16656471 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 51363244 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9231902 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 659908 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1593273 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1005882 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91811 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 54700033 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 305616 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1593273 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17552192 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20324540 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27741870 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8932000 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3360998 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 52127379 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 375 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 510306 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2174045 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 221 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 53799249 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 241745694 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 220537236 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5112 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39397526 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14401722 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 594296 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 542687 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6992906 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10039494 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6994522 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1049493 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1384753 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 48432856 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1029992 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62172633 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 89012 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9963233 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24631985 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 276940 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 79507031 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.781977 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.500620 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 79463748 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031057 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.188290 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16659746 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 51317609 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9233971 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 657554 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1592691 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1005769 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91409 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 54704033 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 304298 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1592691 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17554490 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20340792 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27693159 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8932278 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3348216 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 52126479 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 377 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 497478 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2175969 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 155 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 53794326 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 241736924 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 220533984 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5031 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39400219 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14394106 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 593139 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 541531 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6973197 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10037020 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 7000202 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1050357 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1288163 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 48430994 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1028168 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62176930 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 89712 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9957065 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24599714 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 276838 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 79463748 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.782457 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.501316 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 56951176 71.63% 71.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7375765 9.28% 80.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3517120 4.42% 85.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2922983 3.68% 89.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6158188 7.75% 96.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1492282 1.88% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 793715 1.00% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 229189 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 66613 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 56925517 71.64% 71.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7350450 9.25% 80.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3522799 4.43% 85.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2913274 3.67% 88.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6168473 7.76% 96.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1495817 1.88% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 789992 0.99% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 231277 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 66149 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 79507031 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 79463748 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 30271 0.68% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4195541 94.33% 95.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 221720 4.99% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 30568 0.69% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4194749 94.30% 94.98% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 223174 5.02% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 15963 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29223949 47.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47621 0.08% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1246 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26409062 42.48% 89.59% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6474770 10.41% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 15922 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29222200 47.00% 47.02% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47810 0.08% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1242 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26409099 42.47% 89.58% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6480639 10.42% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62172633 # Type of FU issued -system.cpu0.iq.rate 0.256597 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4447534 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.071535 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208427694 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59435167 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43384407 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11467 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6219 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5237 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66598153 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6051 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 313701 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62176930 # Type of FU issued +system.cpu0.iq.rate 0.256632 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4448493 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.071546 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208394864 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59425365 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43388237 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11204 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6101 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5139 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66603600 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5901 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 313863 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2134408 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3835 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15882 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 849708 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2132926 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3897 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15826 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 851086 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17067409 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348218 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17067174 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 347980 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1593273 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15683016 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 239861 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 49569735 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107283 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10039494 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6994522 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 730989 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 55378 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4828 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15882 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 184147 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 145491 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 329638 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61106002 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26080146 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1066631 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1592691 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15703960 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 239689 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 49567887 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 107700 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10037020 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 7000202 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 730031 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 54998 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4795 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15826 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 184371 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 145167 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 329538 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61108768 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26079506 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1068162 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 106887 # number of nop insts executed -system.cpu0.iew.exec_refs 32497006 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5987699 # Number of branches executed -system.cpu0.iew.exec_stores 6416860 # Number of stores executed -system.cpu0.iew.exec_rate 0.252195 # Inst execution rate -system.cpu0.iew.wb_sent 60612995 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43389644 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23417175 # num instructions producing a value -system.cpu0.iew.wb_consumers 43060015 # num instructions consuming a value +system.cpu0.iew.exec_nop 108725 # number of nop insts executed +system.cpu0.iew.exec_refs 32501673 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5985971 # Number of branches executed +system.cpu0.iew.exec_stores 6422167 # Number of stores executed +system.cpu0.iew.exec_rate 0.252223 # Inst execution rate +system.cpu0.iew.wb_sent 60615706 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43393376 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23422073 # num instructions producing a value +system.cpu0.iew.wb_consumers 43067972 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.179076 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.543826 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.179104 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.543840 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9791777 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 753052 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 287149 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 77913758 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.504003 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.469415 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9785974 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 751330 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 287324 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 77871057 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.504327 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.472133 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 63454715 81.44% 81.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7423327 9.53% 90.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1988141 2.55% 93.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1098394 1.41% 94.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 861624 1.11% 96.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 581195 0.75% 96.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 738806 0.95% 97.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 351756 0.45% 98.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1415800 1.82% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 63445664 81.48% 81.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7408180 9.51% 90.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1965702 2.52% 93.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1101219 1.41% 94.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 850042 1.09% 96.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 579839 0.74% 96.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 741280 0.95% 97.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 350840 0.45% 98.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1428291 1.83% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 77913758 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30063645 # Number of instructions committed -system.cpu0.commit.committedOps 39268790 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 77871057 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30068673 # Number of instructions committed +system.cpu0.commit.committedOps 39272492 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14049900 # Number of memory references committed -system.cpu0.commit.loads 7905086 # Number of loads committed -system.cpu0.commit.membars 209983 # Number of memory barriers committed -system.cpu0.commit.branches 5182251 # Number of branches committed -system.cpu0.commit.fp_insts 5199 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34974968 # Number of committed integer instructions. -system.cpu0.commit.function_calls 508855 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1415800 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14053210 # Number of memory references committed +system.cpu0.commit.loads 7904094 # Number of loads committed +system.cpu0.commit.membars 209520 # Number of memory barriers committed +system.cpu0.commit.branches 5180571 # Number of branches committed +system.cpu0.commit.fp_insts 5103 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34976585 # Number of committed integer instructions. +system.cpu0.commit.function_calls 508087 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1428291 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124579792 # The number of ROB reads -system.cpu0.rob.rob_writes 99757537 # The number of ROB writes -system.cpu0.timesIdled 906870 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 162790078 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2250741366 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29991762 # Number of Instructions Simulated -system.cpu0.committedOps 39196907 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29991762 # Number of Instructions Simulated -system.cpu0.cpi 8.078789 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.078789 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.123781 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.123781 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 277582728 # number of integer regfile reads -system.cpu0.int_regfile_writes 44079568 # number of integer regfile writes -system.cpu0.fp_regfile_reads 44948 # number of floating regfile reads -system.cpu0.fp_regfile_writes 42562 # number of floating regfile writes -system.cpu0.misc_regfile_reads 138472263 # number of misc regfile reads -system.cpu0.misc_regfile_writes 583698 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983976 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.534971 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10503842 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984488 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.669345 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7011386250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 317.535325 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 193.999646 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.620186 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.378906 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999092 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 124525442 # The number of ROB reads +system.cpu0.rob.rob_writes 99752707 # The number of ROB writes +system.cpu0.timesIdled 907289 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 162817206 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2250738250 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 29995072 # Number of Instructions Simulated +system.cpu0.committedOps 39198891 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 29995072 # Number of Instructions Simulated +system.cpu0.cpi 8.077359 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.077359 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.123803 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.123803 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 277602258 # number of integer regfile reads +system.cpu0.int_regfile_writes 44085175 # number of integer regfile writes +system.cpu0.fp_regfile_reads 44877 # number of floating regfile reads +system.cpu0.fp_regfile_writes 42488 # number of floating regfile writes +system.cpu0.misc_regfile_reads 138395505 # number of misc regfile reads +system.cpu0.misc_regfile_writes 582325 # number of misc regfile writes +system.cpu0.icache.tags.replacements 984398 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.534546 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10515921 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 984910 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.677037 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7008829000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 316.868268 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 194.666278 # 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number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 557837 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 507875 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065712 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 557837 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 507875 # number of overall misses -system.cpu0.icache.overall_misses::total 1065712 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7709624467 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6833167274 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14542791741 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7709624467 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6833167274 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14542791741 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7709624467 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6833167274 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14542791741 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5897743 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5671811 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11569554 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5897743 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5671811 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11569554 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5897743 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5671811 # 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mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12155.517382 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11850.110095 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12010.000889 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12155.517382 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11850.110095 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12010.000889 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12155.517382 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11850.110095 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12010.000889 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087491 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082504 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085042 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087491 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.082504 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085042 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087491 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.082504 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085042 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12159.612576 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11864.045674 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12018.825492 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12159.612576 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11864.045674 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12018.825492 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12159.612576 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11864.045674 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12018.825492 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643555 # number of replacements +system.cpu0.dcache.tags.replacements 643530 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.993287 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21527522 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644067 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.424352 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 21531295 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644042 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.431508 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 43200250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 256.501132 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 255.492155 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.500979 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.499008 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 257.568714 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 254.424573 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.503064 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.496923 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 101636995 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 101636995 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7028225 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6743962 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13772187 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3755786 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3505627 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261413 # 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number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 339066 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 409132 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 748198 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1643950 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1318126 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2962076 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7538 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6009 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13547 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 101651746 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 101651746 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7028815 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6747590 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13776405 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3755876 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3505333 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261209 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116971 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 125973 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 242944 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 119744 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 127881 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247625 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10784691 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10252923 # 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number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84542718469 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 64782602600 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 149325321069 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 108200746 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 80635496 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 188836242 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 64501 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1987963 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1722242 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3710205 # 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number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 188050993 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 78000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 52000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 116501 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 89990745047 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 70766386337 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 160757131384 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 89990745047 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 70766386337 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 160757131384 # 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number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 127597 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247653 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12767027 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11976847 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24743874 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12767027 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11976847 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24743874 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.046023 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057197 # miss rate for ReadReq accesses +system.cpu0.dcache.StoreCondReq_miss_latency::total 130000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 90474408086 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 70443282805 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 160917690891 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 90474408086 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 70443282805 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 160917690891 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7368208 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 7156618 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14524826 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5404446 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4818547 # 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mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023406 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024351 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054282 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040929 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047428 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000033 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105218986779 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103892921217 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209111907996 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025563 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027602 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026568 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025221 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023377 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054402 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040743 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047374 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000050 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000031 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025396 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025934 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025657 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025396 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025934 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025657 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13954.086330 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13285.710326 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13611.653829 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47027.142187 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45575.250598 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46368.672796 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12619.397523 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11614.686445 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12174.353840 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025419 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025902 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025653 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025419 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025902 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025653 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13933.898543 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13286.722972 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.612056 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47179.018143 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45492.118665 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46415.738360 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12622.287317 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11506.045192 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12128.292757 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12562.375000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27831.405146 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25022.844020 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26457.252239 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27831.405146 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25022.844020 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26457.252239 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27891.681728 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24982.400005 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26470.223994 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27891.681728 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24982.400005 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26470.223994 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2006,15 +1958,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7298811 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5882879 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 344498 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4442454 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3749763 # Number of BTB hits +system.cpu1.branchPred.lookups 7303181 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5881126 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 346154 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4653929 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3750959 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.407469 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 676814 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34330 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 80.597684 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 679679 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34597 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2038,25 +1990,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25485052 # DTB read hits -system.cpu1.dtb.read_misses 36401 # DTB read misses -system.cpu1.dtb.write_hits 5542090 # DTB write hits -system.cpu1.dtb.write_misses 8345 # DTB write misses +system.cpu1.dtb.read_hits 25488049 # DTB read hits +system.cpu1.dtb.read_misses 36227 # DTB read misses +system.cpu1.dtb.write_hits 5538132 # DTB write hits +system.cpu1.dtb.write_misses 8320 # DTB write misses system.cpu1.dtb.flush_tlb 512 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 663 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5452 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1278 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 241 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5495 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1338 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 228 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 674 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25521453 # DTB read accesses -system.cpu1.dtb.write_accesses 5550435 # DTB write accesses +system.cpu1.dtb.perms_faults 677 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25524276 # DTB read accesses +system.cpu1.dtb.write_accesses 5546452 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31027142 # DTB hits -system.cpu1.dtb.misses 44746 # DTB misses -system.cpu1.dtb.accesses 31071888 # DTB accesses +system.cpu1.dtb.hits 31026181 # DTB hits +system.cpu1.dtb.misses 44547 # DTB misses +system.cpu1.dtb.accesses 31070728 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2078,124 +2030,124 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5673835 # ITB inst hits -system.cpu1.itb.inst_misses 6882 # ITB inst misses +system.cpu1.itb.inst_hits 5688452 # ITB inst hits +system.cpu1.itb.inst_misses 7006 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 512 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 663 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2658 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2704 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1447 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1448 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5680717 # ITB inst accesses -system.cpu1.itb.hits 5673835 # DTB hits -system.cpu1.itb.misses 6882 # DTB misses -system.cpu1.itb.accesses 5680717 # DTB accesses -system.cpu1.numCycles 236975623 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5695458 # ITB inst accesses +system.cpu1.itb.hits 5688452 # DTB hits +system.cpu1.itb.misses 7006 # DTB misses +system.cpu1.itb.accesses 5695458 # DTB accesses +system.cpu1.numCycles 236990378 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14429172 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45037398 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7298811 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4426577 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9907364 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2282600 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82705 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 49394158 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1073 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1935 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 44118 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1230431 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 170 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5671812 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 352198 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3013 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76664255 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.724522 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.076690 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14445279 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45031495 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7303181 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4430638 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9912685 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2288075 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 85272 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 49385810 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1038 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1883 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 43903 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1235955 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5686448 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 352687 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3068 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76688585 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.724367 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.076407 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66765211 87.09% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 630389 0.82% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 841220 1.10% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1125492 1.47% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 998152 1.30% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 547084 0.71% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1279264 1.67% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 367549 0.48% 94.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4109894 5.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66784675 87.09% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 633491 0.83% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 843387 1.10% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1127901 1.47% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 993338 1.30% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 549443 0.72% 92.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1277588 1.67% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 369483 0.48% 94.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4109279 5.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76664255 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030800 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.190051 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15533095 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 50132740 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8857878 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 647971 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1490380 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 961231 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85259 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 52933701 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 285543 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1490380 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16375879 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19322833 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27622785 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8617835 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3232383 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 50467558 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 173 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 596710 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2000524 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 626 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 52901652 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 233465152 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 213426027 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5240 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39335356 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13566296 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 577962 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 535418 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6495060 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9746539 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6334911 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 894923 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1137674 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 46958643 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 959615 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60863950 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 85447 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9232783 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23424311 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 229955 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76664255 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.793903 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.504568 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76688585 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030816 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.190014 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15549027 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50133952 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8864377 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 645129 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1493916 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 964413 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85194 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 52934695 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 283965 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1493916 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16391230 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19303163 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27652687 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8622958 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3222506 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 50466149 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 174 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 593171 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 1994496 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 690 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 52886950 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 233487672 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 213429055 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5328 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39332432 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13554518 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 579559 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 536966 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6477487 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9753455 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6333018 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 895982 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1122035 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 46958561 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 957421 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60864798 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 86364 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9232524 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23424717 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 226140 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76688585 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.793662 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.504660 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54480181 71.06% 71.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7304682 9.53% 80.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3460273 4.51% 85.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2866704 3.74% 88.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6125054 7.99% 96.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1372858 1.79% 98.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 769548 1.00% 99.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 222824 0.29% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 62131 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54509370 71.08% 71.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7300848 9.52% 80.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3460717 4.51% 85.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2863086 3.73% 88.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6124123 7.99% 96.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1373475 1.79% 98.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 772006 1.01% 99.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 222325 0.29% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 62635 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76664255 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76688585 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29010 0.66% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 28981 0.66% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available @@ -2224,13 +2176,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4179738 94.96% 95.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 192807 4.38% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4176523 94.96% 95.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 192832 4.38% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 12555 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28808011 47.33% 47.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45980 0.08% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 12596 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28808168 47.33% 47.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45770 0.08% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued @@ -2247,7 +2199,7 @@ system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.43% # Ty system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued @@ -2256,116 +2208,116 @@ system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Ty system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 867 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26140692 42.95% 90.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5855817 9.62% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26145062 42.96% 90.38% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5852305 9.62% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60863950 # Type of FU issued -system.cpu1.iq.rate 0.256836 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4401559 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072318 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 202912608 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57159577 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42178137 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11121 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6181 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5062 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65247126 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5828 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 310626 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60864798 # Type of FU issued +system.cpu1.iq.rate 0.256824 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4398340 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072264 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 202935847 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57156855 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42177968 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11410 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6319 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5146 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65244557 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5985 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 312441 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1995012 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2960 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15279 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 746422 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2001655 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2943 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15220 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 749307 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17045290 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 332871 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17042804 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 332523 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1490380 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14881654 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 224199 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48035025 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 95776 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9746539 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6334911 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 685011 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49572 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 5137 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15279 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 166909 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 134382 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 301291 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59839107 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25823960 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1024843 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1493916 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14868856 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 223350 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48029034 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 96518 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9753455 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6333018 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 681732 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49156 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 5134 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15220 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 168778 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 134493 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 303271 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59837987 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25827716 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1026811 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 116767 # number of nop insts executed -system.cpu1.iew.exec_refs 31629946 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5849908 # Number of branches executed -system.cpu1.iew.exec_stores 5805986 # Number of stores executed -system.cpu1.iew.exec_rate 0.252512 # Inst execution rate -system.cpu1.iew.wb_sent 59372558 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42183199 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23508004 # num instructions producing a value -system.cpu1.iew.wb_consumers 42759548 # num instructions consuming a value +system.cpu1.iew.exec_nop 113052 # number of nop insts executed +system.cpu1.iew.exec_refs 31629861 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5852394 # Number of branches executed +system.cpu1.iew.exec_stores 5802145 # Number of stores executed +system.cpu1.iew.exec_rate 0.252491 # Inst execution rate +system.cpu1.iew.wb_sent 59370669 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42183114 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23501476 # num instructions producing a value +system.cpu1.iew.wb_consumers 42733790 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178006 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.549772 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.177995 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.549951 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9155270 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 729660 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260542 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 75173875 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.511996 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.483358 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9169088 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 731281 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 262316 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 75194669 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.511793 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.483255 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60919870 81.04% 81.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7446257 9.91% 90.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1922213 2.56% 93.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1068282 1.42% 94.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 820469 1.09% 96.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 498258 0.66% 96.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 699309 0.93% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 369578 0.49% 98.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1429639 1.90% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60941986 81.05% 81.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7448338 9.91% 90.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1921902 2.56% 93.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1064941 1.42% 94.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 820613 1.09% 96.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 497482 0.66% 96.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 699016 0.93% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 369953 0.49% 98.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1430438 1.90% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 75173875 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30400176 # Number of instructions committed -system.cpu1.commit.committedOps 38488707 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 75194669 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 30395180 # Number of instructions committed +system.cpu1.commit.committedOps 38484098 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13340016 # Number of memory references committed -system.cpu1.commit.loads 7751527 # Number of loads committed -system.cpu1.commit.membars 193715 # Number of memory barriers committed -system.cpu1.commit.branches 5124652 # Number of branches committed -system.cpu1.commit.fp_insts 5013 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34222153 # Number of committed integer instructions. -system.cpu1.commit.function_calls 482564 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1429639 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13335511 # Number of memory references committed +system.cpu1.commit.loads 7751800 # Number of loads committed +system.cpu1.commit.membars 194141 # Number of memory barriers committed +system.cpu1.commit.branches 5126394 # Number of branches committed +system.cpu1.commit.fp_insts 5109 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 34219487 # Number of committed integer instructions. +system.cpu1.commit.function_calls 483277 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1430438 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120517356 # The number of ROB reads -system.cpu1.rob.rob_writes 96821590 # The number of ROB writes -system.cpu1.timesIdled 866519 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 160311368 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2319089759 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 30321678 # Number of Instructions Simulated -system.cpu1.committedOps 38410209 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 30321678 # Number of Instructions Simulated -system.cpu1.cpi 7.815386 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.815386 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.127953 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.127953 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 271574951 # number of integer regfile reads -system.cpu1.int_regfile_writes 43566618 # number of integer regfile writes -system.cpu1.fp_regfile_reads 45165 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42266 # number of floating regfile writes -system.cpu1.misc_regfile_reads 132802747 # number of misc regfile reads -system.cpu1.misc_regfile_writes 590318 # number of misc regfile writes +system.cpu1.rob.rob_reads 120543738 # The number of ROB reads +system.cpu1.rob.rob_writes 96843723 # The number of ROB writes +system.cpu1.timesIdled 866392 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 160301793 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2319061347 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 30318400 # Number of Instructions Simulated +system.cpu1.committedOps 38407318 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 30318400 # Number of Instructions Simulated +system.cpu1.cpi 7.816718 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.816718 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.127931 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.127931 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 271568545 # number of integer regfile reads +system.cpu1.int_regfile_writes 43555908 # number of integer regfile writes +system.cpu1.fp_regfile_reads 45194 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42320 # number of floating regfile writes +system.cpu1.misc_regfile_reads 132647791 # number of misc regfile reads +system.cpu1.misc_regfile_writes 591619 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2382,17 +2334,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518508564766 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1518508564766 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518508564766 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1518508564766 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518507680269 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1518507680269 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518507680269 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1518507680269 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83065 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83057 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |