diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | 3315 |
1 files changed, 1869 insertions, 1446 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 8bb759cd2..1abf69682 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,163 +1,151 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.543311 # Number of seconds simulated -sim_ticks 2543310963000 # Number of ticks simulated -final_tick 2543310963000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.548434 # Number of seconds simulated +sim_ticks 2548433543500 # Number of ticks simulated +final_tick 2548433543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64896 # Simulator instruction rate (inst/s) -host_op_rate 83503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2736674491 # Simulator tick rate (ticks/s) -host_mem_usage 401948 # Number of bytes of host memory used -host_seconds 929.34 # Real time elapsed on the host -sim_insts 60310426 # Number of instructions simulated -sim_ops 77602848 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 62524 # Simulator instruction rate (inst/s) +host_op_rate 80452 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2641694597 # Simulator tick rate (ticks/s) +host_mem_usage 403600 # Number of bytes of host memory used +host_seconds 964.70 # Real time elapsed on the host +sim_insts 60316814 # Number of instructions simulated +sim_ops 77611972 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1152 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 505600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4226512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 293504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4868124 # Number of bytes read from this memory -system.physmem.bytes_read::total 131007148 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 505600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 293504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786304 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1344512 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1671600 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802416 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 441408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4859600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 357888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4231256 # Number of bytes read from this memory +system.physmem.bytes_read::total 131003368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 441408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 357888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799296 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1678512 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1337588 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799652 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 33 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 18 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7900 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 66073 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4586 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 76071 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293491 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59161 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336128 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417900 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813189 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47619237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 830 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 6897 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 75965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5592 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 66119 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293431 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 419628 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 334397 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47523518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 452 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 198796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1661815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 115402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1914089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51510472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 198796 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 115402 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314198 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1488730 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 528646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 657253 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2674630 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1488730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47619237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 173208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1906897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 140435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1660336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51405448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 173208 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 140435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 658645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 524867 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2668169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47523518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 452 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 198796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2190461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 115402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2571343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54185102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293491 # Total number of read requests seen -system.physmem.writeReqs 813189 # Total number of write requests seen -system.physmem.cpureqs 218466 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978783424 # Total number of bytes read from memory -system.physmem.bytesWritten 52044096 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131007148 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6802416 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4673 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955732 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956165 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956089 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956033 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955432 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955985 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50834 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51163 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50191 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50901 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50804 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51194 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50730 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 173208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2565541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 140435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2185203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54073617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293431 # Total number of read requests seen +system.physmem.writeReqs 813143 # Total number of write requests seen +system.physmem.cpureqs 218375 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978779584 # Total number of bytes read from memory +system.physmem.bytesWritten 52041152 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131003368 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799652 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 955869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955530 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 955877 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 955758 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955993 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 955787 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955507 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955113 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956214 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956070 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955978 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48908 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51082 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51006 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51266 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51202 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51317 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51099 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50759 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50417 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50974 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51268 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51122 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32475 # Number of times wr buffer was full causing retry -system.physmem.totGap 2543309787500 # Total gap between requests +system.physmem.numWrRetry 32387 # Number of times wr buffer was full causing retry +system.physmem.totGap 2548432371500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 43 # Categorize read packet sizes +system.physmem.readPktSize::2 42 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154632 # Categorize read packet sizes +system.physmem.readPktSize::6 154573 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754028 # Categorize write packet sizes +system.physmem.writePktSize::2 754025 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59161 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1054822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991773 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3605165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2700301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 59966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160547 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 9111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59118 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1060830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 986831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 991569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3738549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2806537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2806300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2762834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 14911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 27618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 40328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 3599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 3593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2835 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -168,282 +156,517 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35292 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32480 # What write queue length does an incoming req see -system.physmem.totQLat 346644691750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 439813624250 # Sum of mem lat for all requests -system.physmem.totBusLat 76467385000 # Total cycles spent in databus access -system.physmem.totBankLat 16701547500 # Total cycles spent in bank access -system.physmem.avgQLat 22666.18 # Average queueing delay per request -system.physmem.avgBankLat 1092.07 # Average bank access latency per request +system.physmem.wrQLenPdf::17 35276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32415 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40040 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 25744.741658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2072.132686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32880.697508 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 6923 17.29% 17.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3475 8.68% 25.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2293 5.73% 31.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1778 4.44% 36.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1271 3.17% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1070 2.67% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 793 1.98% 43.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 869 2.17% 46.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 551 1.38% 47.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 489 1.22% 48.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 420 1.05% 49.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 393 0.98% 50.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 261 0.65% 51.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 255 0.64% 52.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 183 0.46% 52.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 282 0.70% 53.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 123 0.31% 53.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 156 0.39% 53.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 102 0.25% 54.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 126 0.31% 54.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 80 0.20% 54.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 383 0.96% 55.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 613 1.53% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 451 1.13% 58.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 81 0.20% 58.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 160 0.40% 58.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 53 0.13% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 109 0.27% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 41 0.10% 59.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 74 0.18% 59.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 65 0.16% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 23 0.06% 59.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 42 0.10% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 15 0.04% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 29 0.07% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 18 0.04% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 27 0.07% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 12 0.03% 60.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 7 0.02% 60.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 22 0.05% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 8 0.02% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 11 0.03% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 11 0.03% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 16 0.04% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 19 0.05% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 8 0.02% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 9 0.02% 60.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 8 0.02% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 6 0.01% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 6 0.01% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 9 0.02% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 4 0.01% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 9 0.02% 60.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 6 0.01% 60.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 4 0.01% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 3 0.01% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 10 0.02% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 40 0.10% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 3 0.01% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 5 0.01% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 4 0.01% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 4 0.01% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 3 0.01% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 2 0.00% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 3 0.01% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 3 0.01% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 2 0.00% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 5 0.01% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 1 0.00% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 2 0.00% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 4 0.01% 60.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 3 0.01% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5087 2 0.00% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 5 0.01% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 6 0.01% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 2 0.00% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 5 0.01% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 7 0.02% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5791 1 0.00% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5855 1 0.00% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 2 0.00% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 1 0.00% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 6 0.01% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 1 0.00% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 2 0.00% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6367 1 0.00% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6431 3 0.01% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 1 0.00% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 5 0.01% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 2 0.00% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 2 0.00% 61.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 2 0.00% 61.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 20 0.05% 61.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 2 0.00% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 1 0.00% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 2 0.00% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7135 3 0.01% 61.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 2 0.00% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 1 0.00% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 9 0.02% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7519 1 0.00% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 4 0.01% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 7 0.02% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 3 0.01% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 4 0.01% 61.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 1 0.00% 61.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 7 0.02% 61.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 2 0.00% 61.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 309 0.77% 62.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9247 1 0.00% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9695 1 0.00% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 17 0.04% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 1 0.00% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12831 1 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14239 1 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16927 1 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18975 1 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21343 1 0.00% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 1 0.00% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26399 1 0.00% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 1 0.00% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29983 1 0.00% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30239 1 0.00% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30623 1 0.00% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32031 1 0.00% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32287 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32799 2 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33311 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 6 0.01% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35359 1 0.00% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42944-42975 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45663 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53279 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58112-58143 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58624-58655 1 0.00% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61120-61151 1 0.00% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14762 36.87% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::123712-123743 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130048-130079 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130944-130975 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 346 0.86% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132127 4 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::161280-161311 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::168384-168415 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::187392-187423 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 4 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40040 # Bytes accessed per row activation +system.physmem.totQLat 308881805250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 400754322750 # Sum of mem lat for all requests +system.physmem.totBusLat 76467100000 # Total cycles spent in databus access +system.physmem.totBankLat 15405417500 # Total cycles spent in bank access +system.physmem.avgQLat 20197.04 # Average queueing delay per request +system.physmem.avgBankLat 1007.32 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28758.25 # Average memory access latency -system.physmem.avgRdBW 384.85 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.46 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.51 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 26204.36 # Average memory access latency +system.physmem.avgRdBW 384.07 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.41 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.17 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.13 # Average write queue length over time -system.physmem.readRowHits 15218324 # Number of row buffer hits during reads -system.physmem.writeRowHits 794497 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.70 # Row buffer hit rate for writes -system.physmem.avgGap 157904.04 # Average gap between requests -system.l2c.replacements 64400 # number of replacements -system.l2c.tagsinuse 51409.834545 # Cycle average of tags in use -system.l2c.total_refs 1903586 # Total number of references to valid blocks. -system.l2c.sampled_refs 129789 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.666775 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2531435998500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36958.443874 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 20.878124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5181.005742 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3269.589268 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 7.697989 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3013.641151 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2958.578047 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563941 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000319 # Average percentage of cache occupancy +system.physmem.busUtil 3.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.16 # Average read queue length over time +system.physmem.avgWrQLen 1.10 # Average write queue length over time +system.physmem.readRowHits 15267875 # Number of row buffer hits during reads +system.physmem.writeRowHits 798648 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.22 # Row buffer hit rate for writes +system.physmem.avgGap 158223.12 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55014580 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346067 # Transaction distribution +system.membus.trans_dist::ReadResp 16346070 # Transaction distribution +system.membus.trans_dist::WriteReq 763348 # Transaction distribution +system.membus.trans_dist::WriteResp 763348 # Transaction distribution +system.membus.trans_dist::Writeback 59118 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4682 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4684 # Transaction distribution +system.membus.trans_dist::ReadExReq 131411 # Transaction distribution +system.membus.trans_dist::ReadExResp 131411 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution +system.membus.trans_dist::StoreCondReq 3 # Transaction distribution +system.membus.trans_dist::StoreCondResp 3 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32163398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34550150 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16692492 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19090473 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 137803020 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 140201001 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140201001 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1492522500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 17540815750 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3583500 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4705924038 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 34177393245 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.l2c.replacements 64346 # number of replacements +system.l2c.tagsinuse 51424.069961 # Cycle average of tags in use +system.l2c.total_refs 1905385 # Total number of references to valid blocks. +system.l2c.sampled_refs 129735 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.686746 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2511358439500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36974.185132 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 11.366489 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000367 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4621.370879 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3355.179290 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 15.725461 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3578.652286 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2867.590058 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.564181 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000173 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.079056 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.049890 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000117 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.045985 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.045144 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784452 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015791 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.986607 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989146 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.987797 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.090909 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.512929 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567979 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541390 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001012 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000278 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015638 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.198407 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000326 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009442 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.250831 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091686 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001012 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000278 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015638 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.198407 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000326 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009442 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.250831 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091686 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45381.291618 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46521.165293 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44712.359629 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.551471 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.529588 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.540998 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.241204 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011705 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.205460 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091591 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.241204 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011705 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.205460 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091591 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61674.135507 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62787.378534 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61810.745390 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10005.201034 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.731529 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.573439 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39988.226573 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37119.935476 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38432.465895 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40475.095470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37683.798886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39359.547770 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40475.095470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37683.798886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39359.547770 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56143.257661 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55885.895105 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56022.680137 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -634,680 +861,876 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7600384 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6061207 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 379102 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4941026 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4041960 # Number of BTB hits +system.toL2Bus.throughput 58505331 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677704 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677706 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608398 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2960 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246173 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246173 # Transaction distribution +system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution +system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution +system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969441 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798176 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37507 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149666 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7954790 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62986112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85598825 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54648 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253968 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 148893553 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148893553 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 203396 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4965063678 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 4434793437 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 4469014832 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 23886909 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 86662497 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 48461480 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322135 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322135 # Transaction distribution +system.iobus.trans_dist::WriteReq 8160 # Transaction distribution +system.iobus.trans_dist::WriteResp 8160 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660590 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 123500861 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500861 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374798000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu0.branchPred.lookups 7472736 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5963732 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 379354 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4914816 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4037140 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.804063 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 728879 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39033 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 82.142241 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 698266 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 38240 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26040938 # DTB read hits -system.cpu0.dtb.read_misses 40555 # DTB read misses -system.cpu0.dtb.write_hits 5901951 # DTB write hits -system.cpu0.dtb.write_misses 9434 # DTB write misses -system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 25723416 # DTB read hits +system.cpu0.dtb.read_misses 39440 # DTB read misses +system.cpu0.dtb.write_hits 6006462 # DTB write hits +system.cpu0.dtb.write_misses 9528 # DTB write misses +system.cpu0.dtb.flush_tlb 258 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5623 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 276 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5597 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1333 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 633 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26081493 # DTB read accesses -system.cpu0.dtb.write_accesses 5911385 # DTB write accesses +system.cpu0.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25762856 # DTB read accesses +system.cpu0.dtb.write_accesses 6015990 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31942889 # DTB hits -system.cpu0.dtb.misses 49989 # DTB misses -system.cpu0.dtb.accesses 31992878 # DTB accesses -system.cpu0.itb.inst_hits 6096045 # ITB inst hits -system.cpu0.itb.inst_misses 7428 # ITB inst misses +system.cpu0.dtb.hits 31729878 # DTB hits +system.cpu0.dtb.misses 48968 # DTB misses +system.cpu0.dtb.accesses 31778846 # DTB accesses +system.cpu0.itb.inst_hits 6261683 # ITB inst hits +system.cpu0.itb.inst_misses 7235 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 258 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1569 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1762 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6103473 # ITB inst accesses -system.cpu0.itb.hits 6096045 # DTB hits -system.cpu0.itb.misses 7428 # DTB misses -system.cpu0.itb.accesses 6103473 # DTB accesses -system.cpu0.numCycles 239139269 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6268918 # ITB inst accesses +system.cpu0.itb.hits 6261683 # DTB hits +system.cpu0.itb.misses 7235 # DTB misses +system.cpu0.itb.accesses 6268918 # DTB accesses +system.cpu0.numCycles 237920120 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15469651 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47735703 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7600384 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4770839 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10588915 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2554228 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 92050 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 48266741 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1619 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2012 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 51922 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1409369 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6094028 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 397204 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3100 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77649364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.760813 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.117939 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15748746 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 49352173 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7472736 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4735406 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10833707 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2792544 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 84623 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 47712542 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1287 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1922 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 50902 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1299242 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6259599 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 422561 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2976 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77655749 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.785029 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.152550 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67068023 86.37% 86.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 685973 0.88% 87.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 883508 1.14% 88.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1225779 1.58% 89.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1145464 1.48% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 573659 0.74% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1320882 1.70% 93.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 397746 0.51% 94.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4348330 5.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 66829888 86.06% 86.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 668416 0.86% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 858180 1.11% 88.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1304413 1.68% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1126910 1.45% 91.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 549966 0.71% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1380247 1.78% 93.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 376750 0.49% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4560979 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77649364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031782 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.199615 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16523555 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49304070 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9588345 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 552618 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1678659 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1021998 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90748 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56218321 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 303479 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1678659 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17458336 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 19025484 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27018348 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9133613 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3332888 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53403158 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13481 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 625557 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2163090 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 470 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55533202 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 243132036 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243084049 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 47987 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40330710 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15202492 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 427890 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 379964 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6776397 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10330089 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6786263 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1056196 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1308824 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49548242 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1040790 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63116713 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 95333 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10484602 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26435485 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 265976 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77649364 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.812843 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.518782 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77655749 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031409 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.207432 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16823690 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 48684179 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9802416 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 509733 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1833567 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1006000 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91487 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 57560969 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 307020 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1833567 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17765952 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 19652864 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 25831801 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9294758 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3274685 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54590229 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7255 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 552363 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2204905 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 211 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 56896376 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 249980910 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 249932531 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48379 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39701074 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 17195302 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 410578 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 363043 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6638624 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10379903 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6907552 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1064074 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1362159 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50052762 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 969661 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62837234 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92382 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11367794 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 29332821 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 250599 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77655749 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.809177 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.518047 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54835526 70.62% 70.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7206411 9.28% 79.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3684013 4.74% 84.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3126457 4.03% 88.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6296301 8.11% 96.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1390393 1.79% 98.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 812577 1.05% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 231214 0.30% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 66472 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55074638 70.92% 70.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6993608 9.01% 79.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3678555 4.74% 84.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3117743 4.01% 88.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6240678 8.04% 96.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1479911 1.91% 98.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 787330 1.01% 99.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 219248 0.28% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 64038 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77649364 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77655749 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 32527 0.73% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 4 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4227565 94.61% 95.34% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 208097 4.66% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 30466 0.70% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4143838 94.53% 95.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 209138 4.77% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195790 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29888266 47.35% 47.66% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47148 0.07% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1209 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26756071 42.39% 90.13% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6228206 9.87% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 167413 0.27% 0.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29876413 47.55% 47.81% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48260 0.08% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 15 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 946 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26437550 42.07% 89.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6306621 10.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63116713 # Type of FU issued -system.cpu0.iq.rate 0.263933 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4468193 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070793 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208483702 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61082486 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44086612 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12401 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6581 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5541 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67382548 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6568 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 320496 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62837234 # Type of FU issued +system.cpu0.iq.rate 0.264111 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4383444 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.069759 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 207842642 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 62399132 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43895220 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12180 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6627 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5522 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67046851 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6414 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 320881 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2269255 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3561 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15997 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 887357 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2431860 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3521 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16133 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 922699 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17163539 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367436 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 16864632 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 486760 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1678659 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14252559 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 235358 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50705856 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 106082 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10330089 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6786263 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 740769 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 57048 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3493 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15997 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 185463 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 146727 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 332190 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61942896 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26397875 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1173817 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1833567 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14994749 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 240124 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 51146104 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 107104 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10379903 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6907552 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 682007 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 55746 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3189 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16133 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 183360 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 147814 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 331174 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61530066 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26055329 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1307168 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 116824 # number of nop insts executed -system.cpu0.iew.exec_refs 32569629 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6012851 # Number of branches executed -system.cpu0.iew.exec_stores 6171754 # Number of stores executed -system.cpu0.iew.exec_rate 0.259024 # Inst execution rate -system.cpu0.iew.wb_sent 61414090 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44092153 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24268667 # num instructions producing a value -system.cpu0.iew.wb_consumers 44593954 # num instructions consuming a value +system.cpu0.iew.exec_nop 123681 # number of nop insts executed +system.cpu0.iew.exec_refs 32305514 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5821167 # Number of branches executed +system.cpu0.iew.exec_stores 6250185 # Number of stores executed +system.cpu0.iew.exec_rate 0.258616 # Inst execution rate +system.cpu0.iew.wb_sent 60920832 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43900742 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23943541 # num instructions producing a value +system.cpu0.iew.wb_consumers 43567103 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184379 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544214 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184519 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.549578 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10328850 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 774814 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 289634 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75970705 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.524893 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.506232 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11253313 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 719062 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 289317 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75822182 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.520093 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.499421 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61754720 81.29% 81.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6906334 9.09% 90.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2042059 2.69% 93.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1137631 1.50% 94.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1039888 1.37% 95.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 547173 0.72% 96.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 697067 0.92% 97.57% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 371357 0.49% 98.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1474476 1.94% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61770131 81.47% 81.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6789372 8.95% 90.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2077521 2.74% 93.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1107875 1.46% 94.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1001712 1.32% 95.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 557795 0.74% 96.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 684831 0.90% 97.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 401810 0.53% 98.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1431135 1.89% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75970705 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31216883 # Number of instructions committed -system.cpu0.commit.committedOps 39876471 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75822182 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30629038 # Number of instructions committed +system.cpu0.commit.committedOps 39434598 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13959740 # Number of memory references committed -system.cpu0.commit.loads 8060834 # Number of loads committed -system.cpu0.commit.membars 211745 # Number of memory barriers committed -system.cpu0.commit.branches 5194005 # Number of branches committed -system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35234084 # Number of committed integer instructions. -system.cpu0.commit.function_calls 512673 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1474476 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13932896 # Number of memory references committed +system.cpu0.commit.loads 7948043 # Number of loads committed +system.cpu0.commit.membars 201908 # Number of memory barriers committed +system.cpu0.commit.branches 4992421 # Number of branches committed +system.cpu0.commit.fp_insts 5469 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34986832 # Number of committed integer instructions. +system.cpu0.commit.function_calls 490811 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1431135 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123727475 # The number of ROB reads -system.cpu0.rob.rob_writes 102131366 # The number of ROB writes -system.cpu0.timesIdled 883402 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161489905 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289692501 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31137553 # Number of Instructions Simulated -system.cpu0.committedOps 39797141 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31137553 # Number of Instructions Simulated -system.cpu0.cpi 7.680092 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.680092 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130207 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130207 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 280388173 # number of integer regfile reads -system.cpu0.int_regfile_writes 45343219 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22835 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19826 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15490012 # number of misc regfile reads -system.cpu0.misc_regfile_writes 428542 # number of misc regfile writes -system.cpu0.icache.replacements 983837 # number of replacements -system.cpu0.icache.tagsinuse 511.608434 # Cycle average of tags in use -system.cpu0.icache.total_refs 11044105 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984349 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.219705 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6537508000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 356.557711 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 155.050723 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.696402 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.302833 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999235 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5554519 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5489586 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11044105 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5554519 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5489586 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11044105 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5554519 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5489586 # number of overall hits -system.cpu0.icache.overall_hits::total 11044105 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 539384 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 525964 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065348 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 539384 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 525964 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065348 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 539384 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 525964 # number of overall misses -system.cpu0.icache.overall_misses::total 1065348 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7306834994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6986624997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14293459991 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7306834994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6986624997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14293459991 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7306834994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6986624997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14293459991 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6093903 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 6015550 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12109453 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6093903 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 6015550 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12109453 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6093903 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 6015550 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12109453 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088512 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087434 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.087977 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088512 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087434 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.087977 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088512 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087434 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.087977 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13546.629107 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13283.466163 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13416.705143 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13546.629107 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13283.466163 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13416.705143 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13546.629107 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13283.466163 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13416.705143 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5066 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 940 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 333 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.213213 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 940 # average number of cycles each access was blocked +system.cpu0.rob.rob_reads 124149615 # The number of ROB reads +system.cpu0.rob.rob_writes 103265708 # The number of ROB writes +system.cpu0.timesIdled 892080 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 160264371 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2282472691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 30545540 # Number of Instructions Simulated +system.cpu0.committedOps 39351100 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 30545540 # Number of Instructions Simulated +system.cpu0.cpi 7.789030 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.789030 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.128386 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.128386 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 279175646 # number of integer regfile reads +system.cpu0.int_regfile_writes 45166448 # number of integer regfile writes +system.cpu0.fp_regfile_reads 23007 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19790 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15439802 # number of misc regfile reads +system.cpu0.misc_regfile_writes 404480 # number of misc regfile writes +system.cpu0.icache.replacements 984632 # number of replacements +system.cpu0.icache.tagsinuse 511.564307 # Cycle average of tags in use +system.cpu0.icache.total_refs 10914069 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 985144 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.078653 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6937099000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 153.323923 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 358.240384 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.299461 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.699688 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999149 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5710872 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5203197 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10914069 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5710872 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5203197 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10914069 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5710872 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5203197 # 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miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.087644 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.090517 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.089016 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13723.784028 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13574.523196 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13651.305835 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13651.305835 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13651.305835 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 7371 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 409 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.022005 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41253 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39724 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80977 # 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number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 498131 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 486240 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984371 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5959731494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5688421497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11648152991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5959731494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5688421497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11648152991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5959731494 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5688421497 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11648152991 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7527500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7527500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7527500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7527500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081743 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080831 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081289 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081743 # 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average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643632 # number of replacements -system.cpu0.dcache.tagsinuse 511.992721 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21539031 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 644144 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.438223 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 318.855973 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 193.136748 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.622766 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.377220 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7102728 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6679613 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13782341 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3764279 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3497770 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7262049 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125347 # 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number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1588025 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1487769 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3075794 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184196 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 202038 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386234 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 129874 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 119141 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249015 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6257 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5931 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 333124 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 301746 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 634870 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 333124 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 301746 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 634870 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2896058500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2345588000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5241646500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4040706484 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4421917442 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8462623926 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72222000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74035000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146257000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 314070 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 321179 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635249 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 314070 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 321179 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635249 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2559621550 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2682909890 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5242531440 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5713299541 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5062841611 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10776141152 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 77981002 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68096502 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146077504 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 67000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 133000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6936764984 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6767505442 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13704270426 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6936764984 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6767505442 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13704270426 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91949852000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90406740000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356592000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14910322570 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18705155021 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33615477591 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106860174570 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109111895021 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215972069591 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028239 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024754 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026561 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023281 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025434 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024345 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046516 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048356 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047412 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000039 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026222 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025039 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025646 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026222 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025039 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025646 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13610.576652 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13541.952208 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13579.782066 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33576.301968 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34401.903281 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34002.691752 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11743.414634 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12210.951674 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11975.517891 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 67000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 134000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8272921091 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7745751501 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16018672592 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8272921091 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7745751501 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16018672592 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90317850501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 92017839000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182335689501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 18608772616 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14303930851 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 32912703467 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 156000 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 156000 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 108926623117 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 106321769851 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215248392968 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024709 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028567 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026587 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024933 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023757 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051475 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043710 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047379 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000043 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000038 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024801 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026572 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025666 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.024801 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026572 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13896.184228 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13279.234055 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13573.459198 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43991.095531 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42494.536818 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43275.068377 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12463.001758 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11481.453718 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11985.354775 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12090.909091 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20823.372030 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22427.821552 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21585.947400 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20823.372030 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22427.821552 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21585.947400 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13400 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1322,324 +1745,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7054454 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5657096 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 345347 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4549622 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3820237 # Number of BTB hits +system.cpu1.branchPred.lookups 7176614 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5748558 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 346164 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4712171 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3815419 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 83.968229 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 674890 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35092 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 80.969451 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 703194 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35756 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25326740 # DTB read hits -system.cpu1.dtb.read_misses 36422 # DTB read misses -system.cpu1.dtb.write_hits 5812086 # DTB write hits -system.cpu1.dtb.write_misses 9253 # DTB write misses -system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 25652921 # DTB read hits +system.cpu1.dtb.read_misses 36442 # DTB read misses +system.cpu1.dtb.write_hits 5708219 # DTB write hits +system.cpu1.dtb.write_misses 9483 # DTB write misses +system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5525 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1356 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 233 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5550 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1291 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 644 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25363162 # DTB read accesses -system.cpu1.dtb.write_accesses 5821339 # DTB write accesses +system.cpu1.dtb.perms_faults 574 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25689363 # DTB read accesses +system.cpu1.dtb.write_accesses 5717702 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31138826 # DTB hits -system.cpu1.dtb.misses 45675 # DTB misses -system.cpu1.dtb.accesses 31184501 # DTB accesses -system.cpu1.itb.inst_hits 6017589 # ITB inst hits -system.cpu1.itb.inst_misses 6780 # ITB inst misses +system.cpu1.dtb.hits 31361140 # DTB hits +system.cpu1.dtb.misses 45925 # DTB misses +system.cpu1.dtb.accesses 31407065 # DTB accesses +system.cpu1.itb.inst_hits 5722854 # ITB inst hits +system.cpu1.itb.inst_misses 6790 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 2604 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1493 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1206 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6024369 # ITB inst accesses -system.cpu1.itb.hits 6017589 # DTB hits -system.cpu1.itb.misses 6780 # DTB misses -system.cpu1.itb.accesses 6024369 # DTB accesses -system.cpu1.numCycles 234207757 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5729644 # ITB inst accesses +system.cpu1.itb.hits 5722854 # DTB hits +system.cpu1.itb.misses 6790 # DTB misses +system.cpu1.itb.accesses 5729644 # DTB accesses +system.cpu1.numCycles 238719781 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15218240 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46698589 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7054454 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4495127 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10302624 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2620130 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82175 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 46347162 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1067 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2022 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 43841 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1251673 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 166 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 6015552 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 445431 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2871 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 75042047 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.773320 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.138232 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14663434 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45610232 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7176614 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4518613 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10115214 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2414166 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 79241 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 48437095 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1874 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 41135 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1402245 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 183 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5721051 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 343472 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3001 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76398004 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.741963 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.097795 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64747187 86.28% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 625900 0.83% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 833929 1.11% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1208466 1.61% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1046555 1.39% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 538335 0.72% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1373859 1.83% 93.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 351234 0.47% 94.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4316582 5.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66290194 86.77% 86.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 639384 0.84% 87.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 858446 1.12% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1141205 1.49% 90.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1054322 1.38% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 565766 0.74% 92.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1279029 1.67% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 372986 0.49% 94.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4196672 5.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 75042047 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030120 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199390 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16229024 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47299345 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9347740 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 453958 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1709750 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 948283 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85990 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54953007 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286020 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1709750 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17168291 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18529773 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25747808 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8785346 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3098929 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51771461 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7122 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 486511 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2115721 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 96 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53850166 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237651325 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 237608915 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42410 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38062786 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15787379 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 405266 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 358955 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6248671 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9866186 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6689314 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 887473 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1140418 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47717114 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 944883 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60871845 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 81909 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10575332 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 28005773 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 237169 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 75042047 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.811170 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521401 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76398004 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030063 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.191062 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15662136 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49485106 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9174118 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 502006 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1572389 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 964164 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86078 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53732667 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 284993 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1572389 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16517156 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19371694 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27019391 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8745759 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3169437 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51316953 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13347 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 558580 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2084092 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 533 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53384018 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 234291448 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 234248948 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42500 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38701877 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14682140 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 422621 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 375998 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6399704 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9755366 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6540913 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 899316 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1131463 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47221133 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1016692 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 61223636 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 83704 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9695690 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24360360 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 252773 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76398004 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.801377 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.509980 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53284770 71.01% 71.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6662382 8.88% 79.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3536622 4.71% 84.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2873956 3.83% 88.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6247532 8.33% 96.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1425164 1.90% 98.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 742478 0.99% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 209609 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59534 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54279894 71.05% 71.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6964982 9.12% 80.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3572105 4.68% 84.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2997144 3.92% 88.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6191464 8.10% 96.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1336331 1.75% 98.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 781274 1.02% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 210623 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 64187 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 75042047 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76398004 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 26737 0.61% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4146600 94.82% 95.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 199958 4.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 28625 0.64% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4232850 94.77% 95.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 204916 4.59% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 167876 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28487291 46.80% 47.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46424 0.08% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 902 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26063934 42.82% 89.97% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6105398 10.03% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 196253 0.32% 0.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28636645 46.77% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45275 0.07% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1166 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26314487 42.98% 90.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6029771 9.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60871845 # Type of FU issued -system.cpu1.iq.rate 0.259905 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4373296 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071844 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 201275709 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59245662 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41829457 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10720 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5895 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4750 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65071600 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5665 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 304013 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 61223636 # Type of FU issued +system.cpu1.iq.rate 0.256467 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4466394 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072952 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 203430011 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57942058 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42278659 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11099 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5883 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4799 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65487820 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5957 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 306320 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2271620 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3204 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14692 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 855526 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2045827 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3210 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14938 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 792022 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16940305 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 458975 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17238980 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 391927 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1709750 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13959970 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 234377 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48767354 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 97921 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9866186 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6689314 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 671038 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 52079 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3815 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14692 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 167743 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133124 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 300867 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59498020 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25657253 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1373825 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1572389 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14646185 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 228906 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48337037 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 102627 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9755366 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6540913 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 729665 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50173 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3845 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14938 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 169845 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 132330 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 302175 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 60177661 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 26008514 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1045975 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105357 # number of nop insts executed -system.cpu1.iew.exec_refs 31711723 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5535621 # Number of branches executed -system.cpu1.iew.exec_stores 6054470 # Number of stores executed -system.cpu1.iew.exec_rate 0.254039 # Inst execution rate -system.cpu1.iew.wb_sent 58916799 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41834207 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22806182 # num instructions producing a value -system.cpu1.iew.wb_consumers 41818913 # num instructions consuming a value +system.cpu1.iew.exec_nop 99212 # number of nop insts executed +system.cpu1.iew.exec_refs 31985233 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5705434 # Number of branches executed +system.cpu1.iew.exec_stores 5976719 # Number of stores executed +system.cpu1.iew.exec_rate 0.252085 # Inst execution rate +system.cpu1.iew.wb_sent 59667880 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42283458 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23216135 # num instructions producing a value +system.cpu1.iew.wb_consumers 42895102 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178620 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545356 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.177126 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.541230 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10492813 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 707714 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260708 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73332297 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.516509 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.496867 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9567940 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 763919 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 261423 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74825615 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.512228 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.487191 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59797837 81.54% 81.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6663272 9.09% 90.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1912982 2.61% 93.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1016048 1.39% 94.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 959954 1.31% 95.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 526368 0.72% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 702800 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 373366 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1379670 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61056295 81.60% 81.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6800068 9.09% 90.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1929591 2.58% 93.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1057405 1.41% 94.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1013455 1.35% 96.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 520209 0.70% 96.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 685711 0.92% 97.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 375889 0.50% 98.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1386992 1.85% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73332297 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29243924 # Number of instructions committed -system.cpu1.commit.committedOps 37876758 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74825615 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29838157 # Number of instructions committed +system.cpu1.commit.committedOps 38327755 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13428354 # Number of memory references committed -system.cpu1.commit.loads 7594566 # Number of loads committed -system.cpu1.commit.membars 191899 # Number of memory barriers committed -system.cpu1.commit.branches 4767702 # Number of branches committed -system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33624060 # Number of committed integer instructions. -system.cpu1.commit.function_calls 478655 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1379670 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13458430 # Number of memory references committed +system.cpu1.commit.loads 7709539 # Number of loads committed +system.cpu1.commit.membars 201879 # Number of memory barriers committed +system.cpu1.commit.branches 4970440 # Number of branches committed +system.cpu1.commit.fp_insts 4743 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33879408 # Number of committed integer instructions. +system.cpu1.commit.function_calls 500692 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1386992 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119446868 # The number of ROB reads -system.cpu1.rob.rob_writes 98500710 # The number of ROB writes -system.cpu1.timesIdled 873517 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159165710 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285782593 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29172873 # Number of Instructions Simulated -system.cpu1.committedOps 37805707 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29172873 # Number of Instructions Simulated -system.cpu1.cpi 8.028272 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.028272 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124560 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124560 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 269572472 # number of integer regfile reads -system.cpu1.int_regfile_writes 42951903 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22113 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14815337 # number of misc regfile reads -system.cpu1.misc_regfile_writes 403940 # number of misc regfile writes +system.cpu1.rob.rob_reads 120414089 # The number of ROB reads +system.cpu1.rob.rob_writes 97409741 # The number of ROB writes +system.cpu1.timesIdled 885352 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 162321777 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2286481516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29771274 # Number of Instructions Simulated +system.cpu1.committedOps 38260872 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29771274 # Number of Instructions Simulated +system.cpu1.cpi 8.018460 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.018460 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124712 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124712 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 271859015 # number of integer regfile reads +system.cpu1.int_regfile_writes 43450852 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22226 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19958 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14811721 # number of misc regfile reads +system.cpu1.misc_regfile_writes 428358 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1654,17 +2077,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192618547941 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192618547941 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192618547941 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192618547941 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1456504103755 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1456504103755 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83057 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83064 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |