diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3')
3 files changed, 1393 insertions, 1415 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 85470f003..9fab0b34a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,7 +19,7 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -1000,6 +1000,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -1025,25 +1026,27 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 clock=1000 conf_table_reported=true in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -1173,7 +1176,7 @@ warn_access= pio=system.iobus.master[24] [system.realview.gic] -type=Gic +type=Pl390 clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 @@ -1452,6 +1455,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr index 4d4ac5cf7..5a85b4fca 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr @@ -14,3 +14,7 @@ warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 5746894a9..1af17ec8e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,131 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.542409 # Number of seconds simulated -sim_ticks 2542409356000 # Number of ticks simulated -final_tick 2542409356000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.542296 # Number of seconds simulated +sim_ticks 2542295570500 # Number of ticks simulated +final_tick 2542295570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77322 # Simulator instruction rate (inst/s) -host_op_rate 99492 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3259551931 # Simulator tick rate (ticks/s) -host_mem_usage 413868 # Number of bytes of host memory used -host_seconds 779.99 # Real time elapsed on the host -sim_insts 60310148 # Number of instructions simulated -sim_ops 77602492 # Number of ops (including micro ops) simulated +host_inst_rate 70655 # Simulator instruction rate (inst/s) +host_op_rate 90914 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2978397497 # Simulator tick rate (ticks/s) +host_mem_usage 409668 # Number of bytes of host memory used +host_seconds 853.58 # Real time elapsed on the host +sim_insts 60309877 # Number of instructions simulated +sim_ops 77602149 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1280 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 506624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4283408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 292928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4810268 # Number of bytes read from this memory -system.physmem.bytes_read::total 131006892 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 506624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 292928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu0.inst 504448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4169680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 296128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4925148 # Number of bytes read from this memory +system.physmem.bytes_read::total 131008300 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 504448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 296128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3787072 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1340604 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1675508 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1346312 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1669800 # Number of bytes written to this memory system.physmem.bytes_written::total 6803184 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 20 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7916 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 66962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4577 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75167 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293487 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 65185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4627 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 76962 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293509 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 59173 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 335151 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 418877 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 336578 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 417450 # Number of write requests responded to by this memory system.physmem.num_writes::total 813201 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47636124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 47638256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 503 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 199269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1684783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 115217 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1892012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51528638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 199269 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 115217 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314486 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489560 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 527297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 659024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2675881 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47636124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 198422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1640124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 116481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1937284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51531498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 198422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 116481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489627 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 656808 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2676000 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47638256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 199269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2212080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 115217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2551035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54204519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293487 # Total number of read requests seen +system.physmem.bw_total::cpu0.inst 198422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2169689 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 116481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2594092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54207499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293509 # Total number of read requests seen system.physmem.writeReqs 813201 # Total number of write requests seen -system.physmem.cpureqs 218488 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978783168 # Total number of bytes read from memory +system.physmem.cpureqs 218507 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978784576 # Total number of bytes read from memory system.physmem.bytesWritten 52044864 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131006892 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 131008300 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 6803184 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956241 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955734 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956495 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955436 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955557 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956169 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956091 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955522 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956030 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955423 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955981 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis +system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955738 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956489 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955445 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955564 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956162 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956093 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956035 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955984 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50833 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50906 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50278 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51363 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50911 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50805 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51195 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50636 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50911 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50191 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50281 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50906 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50808 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51188 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51253 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50731 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50630 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51233 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1790732 # Number of times wr buffer was full causing retry -system.physmem.totGap 2542408198000 # Total gap between requests +system.physmem.numWrRetry 1856479 # Number of times wr buffer was full causing retry +system.physmem.totGap 2542294418500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154628 # Categorize read packet sizes +system.physmem.readPktSize::6 154650 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2544760 # categorize write packet sizes +system.physmem.writePktSize::2 2610507 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes @@ -138,31 +134,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4687 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1054866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961470 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3604976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2700252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60049 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110004 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10070 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1054657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 991834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3604952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2700242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 110017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11014 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -174,60 +170,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35230 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 31921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 31858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32485 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 346733530557 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 439908911807 # Sum of mem lat for all requests -system.physmem.totBusLat 76467385000 # Total cycles spent in databus access -system.physmem.totBankLat 16707996250 # Total cycles spent in bank access -system.physmem.avgQLat 22671.99 # Average queueing delay per request -system.physmem.avgBankLat 1092.49 # Average bank access latency per request +system.physmem.totQLat 346840685210 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 440008538960 # Sum of mem lat for all requests +system.physmem.totBusLat 76467475000 # Total cycles spent in databus access +system.physmem.totBankLat 16700378750 # Total cycles spent in bank access +system.physmem.avgQLat 22678.97 # Average queueing delay per request +system.physmem.avgBankLat 1091.99 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28764.48 # Average memory access latency -system.physmem.avgRdBW 384.98 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28770.96 # Average memory access latency +system.physmem.avgRdBW 385.00 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.47 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.53 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.11 # Average write queue length over time -system.physmem.readRowHits 15218342 # Number of row buffer hits during reads -system.physmem.writeRowHits 794645 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.14 # Average write queue length over time +system.physmem.readRowHits 15218397 # Number of row buffer hits during reads +system.physmem.writeRowHits 794710 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes -system.physmem.avgGap 157847.98 # Average gap between requests +system.physmem.writeRowHitRate 97.73 # Row buffer hit rate for writes +system.physmem.avgGap 157840.70 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -240,239 +236,225 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64396 # number of replacements -system.l2c.tagsinuse 51411.059605 # Cycle average of tags in use -system.l2c.total_refs 1936288 # Total number of references to valid blocks. -system.l2c.sampled_refs 129787 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.918967 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2506346605000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36969.089517 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 15.370678 # Average occupied blocks per requestor +system.l2c.replacements 64418 # number of replacements +system.l2c.tagsinuse 51401.261729 # Cycle average of tags in use +system.l2c.total_refs 1905310 # Total number of references to valid blocks. +system.l2c.sampled_refs 129810 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.677683 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2531415043500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36947.323889 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 9.916328 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5186.086135 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3274.725116 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 19.219664 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.104011 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3007.163435 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2939.300701 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.564104 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000235 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 5145.662568 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3278.560293 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 13.240870 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3059.988680 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2946.568751 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563771 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000151 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # 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number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 482673 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 176185 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1470055 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 607854 # number of Writeback hits -system.l2c.Writeback_hits::total 607854 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits +system.l2c.occ_percent::cpu0.inst 0.078517 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.050027 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000202 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.046692 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.044961 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784321 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32362 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7566 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 491236 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 213718 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30461 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6864 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 480165 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 173950 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1436322 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608473 # number of Writeback hits +system.l2c.Writeback_hits::total 608473 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 19 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56342 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56524 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112866 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 48837 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7271 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 488824 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 267374 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 48027 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7206 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 482673 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 232709 # number of demand (read+write) hits -system.l2c.demand_hits::total 1582921 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 48837 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7271 # number of overall hits -system.l2c.overall_hits::cpu0.inst 488824 # number of overall hits -system.l2c.overall_hits::cpu0.data 267374 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 48027 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7206 # number of overall hits -system.l2c.overall_hits::cpu1.inst 482673 # number of overall hits -system.l2c.overall_hits::cpu1.data 232709 # number of overall hits -system.l2c.overall_hits::total 1582921 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 25 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu0.data 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 57779 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 55086 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112865 # 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number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30461 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6864 # number of overall hits +system.l2c.overall_hits::cpu1.inst 480165 # number of overall hits +system.l2c.overall_hits::cpu1.data 229036 # number of overall hits +system.l2c.overall_hits::total 1549187 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 20 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7806 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6093 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4582 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4589 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23119 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1580 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1330 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2910 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 61797 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 71443 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133240 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 7773 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6102 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4633 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4618 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23163 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1544 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1370 # 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mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541393 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000512 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000275 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015700 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.202381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000437 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000139 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009393 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.246200 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.089857 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000512 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000275 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015700 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.202381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000437 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000139 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009393 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.246200 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.089857 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94623358346 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95960323914 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 190588733167 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000618 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015557 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027582 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000492 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009544 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025749 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015819 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987844 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989884 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.988802 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.509683 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.570439 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541345 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000618 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015557 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.195830 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000492 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009544 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.253417 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091642 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000618 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015557 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.195830 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000492 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009544 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.253417 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091642 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44398.583251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46287.086671 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44663.967196 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10068.681646 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44601.319314 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46302.841888 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44663.031012 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10060.224093 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.748110 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39996.972474 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 36779.206178 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38271.613142 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10032.380233 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39775.018281 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37292.993425 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38412.050085 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40389.705841 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37350.714703 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39214.232388 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40217.548424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37825.820219 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39335.413644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40389.705841 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37350.714703 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39214.232388 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40217.548424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37825.820219 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39335.413644 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -667,680 +637,680 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7548901 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6013590 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 377467 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4898170 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4008296 # Number of BTB hits +system.cpu0.branchPred.lookups 7620138 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6076880 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 380507 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4965064 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4053585 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.832521 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 726547 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 38944 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.642150 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 731859 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39538 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25977003 # DTB read hits -system.cpu0.dtb.read_misses 44168 # DTB read misses -system.cpu0.dtb.write_hits 5905544 # DTB write hits -system.cpu0.dtb.write_misses 10435 # DTB write misses +system.cpu0.dtb.read_hits 26058653 # DTB read hits +system.cpu0.dtb.read_misses 40101 # DTB read misses +system.cpu0.dtb.write_hits 5895373 # DTB write hits +system.cpu0.dtb.write_misses 9447 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 8487 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1476 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 307 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5619 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1431 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 273 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 629 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26021171 # DTB read accesses -system.cpu0.dtb.write_accesses 5915979 # DTB write accesses +system.cpu0.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26098754 # DTB read accesses +system.cpu0.dtb.write_accesses 5904820 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31882547 # DTB hits -system.cpu0.dtb.misses 54603 # DTB misses -system.cpu0.dtb.accesses 31937150 # DTB accesses -system.cpu0.itb.inst_hits 6053570 # ITB inst hits -system.cpu0.itb.inst_misses 7437 # ITB inst misses +system.cpu0.dtb.hits 31954026 # DTB hits +system.cpu0.dtb.misses 49548 # DTB misses +system.cpu0.dtb.accesses 32003574 # DTB accesses +system.cpu0.itb.inst_hits 6112115 # ITB inst hits +system.cpu0.itb.inst_misses 7637 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2703 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2623 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1556 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1579 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6061007 # ITB inst accesses -system.cpu0.itb.hits 6053570 # DTB hits -system.cpu0.itb.misses 7437 # DTB misses -system.cpu0.itb.accesses 6061007 # DTB accesses -system.cpu0.numCycles 238938486 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6119752 # ITB inst accesses +system.cpu0.itb.hits 6112115 # DTB hits +system.cpu0.itb.misses 7637 # DTB misses +system.cpu0.itb.accesses 6119752 # DTB accesses +system.cpu0.numCycles 239063312 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15394391 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47363199 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7548901 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4734843 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10514679 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2521350 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 88217 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49746520 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1973 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 54986 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 100350 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6051440 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 388609 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3416 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77647495 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.755624 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.112120 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15490963 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47835555 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7620138 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4785444 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10608217 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2561094 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 89115 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49527666 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1654 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1892 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 49952 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101088 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 226 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6110008 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 396628 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3581 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77642580 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.762278 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.119818 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67140338 86.47% 86.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 685224 0.88% 87.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 881384 1.14% 88.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1215413 1.57% 90.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1119001 1.44% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 577018 0.74% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1310230 1.69% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 395483 0.51% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4323404 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67041875 86.35% 86.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 689016 0.89% 87.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 885560 1.14% 88.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1228014 1.58% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1141359 1.47% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 577108 0.74% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1324549 1.71% 93.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 398041 0.51% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4357058 5.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77647495 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031593 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.198223 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16447301 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49466389 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9519649 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 555058 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1656976 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1018880 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 89951 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 55851060 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 301878 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1656976 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17376198 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 19158247 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27017971 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9071618 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3364444 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53098048 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 14247 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 629745 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2187800 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 13035 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55196889 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 241870306 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 241822297 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48009 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40273759 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14923130 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 426834 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 378971 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6800028 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10269000 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6780798 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1063277 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1318043 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49318736 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1023913 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62924434 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 96522 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10293246 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26052938 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 249929 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77647495 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.810386 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.515841 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77642580 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031875 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.200096 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16540886 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49255967 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9607571 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 552371 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1683667 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1024811 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90579 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56316085 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 302289 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1683667 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17475063 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18984775 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27019953 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9154130 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3322955 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53494037 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13484 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 621738 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2157353 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 548 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55660367 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 243519467 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 243471355 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48112 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40417937 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15242430 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 429833 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 381699 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6758508 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10355148 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6782314 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1058612 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1316675 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49644359 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1043369 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63195717 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 96260 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10515144 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26542188 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 266673 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77642580 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.813931 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519230 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54849449 70.64% 70.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7244024 9.33% 79.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3688560 4.75% 84.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3114192 4.01% 88.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6252852 8.05% 96.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1400137 1.80% 98.59% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 804405 1.04% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 228817 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 65059 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54792876 70.57% 70.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7218069 9.30% 79.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3694351 4.76% 84.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3145323 4.05% 88.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6277418 8.09% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1407401 1.81% 98.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 809465 1.04% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 231906 0.30% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 65771 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77647495 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77642580 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 28907 0.65% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 5 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4221672 94.79% 95.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 203228 4.56% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29563 0.66% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4229523 94.72% 95.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 206294 4.62% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 196078 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29762339 47.30% 47.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47254 0.08% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1214 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26685508 42.41% 90.10% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6232016 9.90% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 195578 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29951554 47.39% 47.70% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46938 0.07% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1212 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26776565 42.37% 90.15% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6223855 9.85% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62924434 # Type of FU issued -system.cpu0.iq.rate 0.263350 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4453812 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070780 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208088796 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60644934 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43952872 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12311 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6553 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5522 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67175656 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6512 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 321336 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63195717 # Type of FU issued +system.cpu0.iq.rate 0.264347 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4465384 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070660 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208632682 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61211746 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44166006 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12339 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6563 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5520 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67458994 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6529 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 322005 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2241404 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3447 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16174 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 877395 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2276398 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3543 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16033 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 889328 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17145295 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 358927 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17163737 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367898 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1656976 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14313344 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 236698 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50458165 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105115 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10269000 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6780798 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 724480 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 58024 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3552 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16174 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 184745 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 145643 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 330388 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61778089 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26333265 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1146345 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1683667 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14223209 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 234272 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50804503 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105344 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10355148 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6782314 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 742198 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56887 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3242 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16033 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 187141 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 147345 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 334486 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62025172 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26418520 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1170545 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 115516 # number of nop insts executed -system.cpu0.iew.exec_refs 32508411 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5980040 # Number of branches executed -system.cpu0.iew.exec_stores 6175146 # Number of stores executed -system.cpu0.iew.exec_rate 0.258552 # Inst execution rate -system.cpu0.iew.wb_sent 61260719 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43958394 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24186405 # num instructions producing a value -system.cpu0.iew.wb_consumers 44536826 # num instructions consuming a value +system.cpu0.iew.exec_nop 116775 # number of nop insts executed +system.cpu0.iew.exec_refs 32585401 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6028949 # Number of branches executed +system.cpu0.iew.exec_stores 6166881 # Number of stores executed +system.cpu0.iew.exec_rate 0.259451 # Inst execution rate +system.cpu0.iew.wb_sent 61495183 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44171526 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24314220 # num instructions producing a value +system.cpu0.iew.wb_consumers 44686636 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.183974 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.543065 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184769 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544105 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10181243 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 773984 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 288739 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75990519 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.523900 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.505441 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10365934 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 776696 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 291216 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75958913 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.525792 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.508136 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61812445 81.34% 81.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6884323 9.06% 90.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2031918 2.67% 93.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1127942 1.48% 94.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1041381 1.37% 95.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 554423 0.73% 96.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 699295 0.92% 97.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 364332 0.48% 98.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1474460 1.94% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61730922 81.27% 81.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6914068 9.10% 90.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2040925 2.69% 93.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1133695 1.49% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1039727 1.37% 95.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 547660 0.72% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 699909 0.92% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 371161 0.49% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1480846 1.95% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75990519 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31157319 # Number of instructions committed -system.cpu0.commit.committedOps 39811398 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75958913 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31284581 # Number of instructions committed +system.cpu0.commit.committedOps 39938560 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13930999 # Number of memory references committed -system.cpu0.commit.loads 8027596 # Number of loads committed -system.cpu0.commit.membars 211461 # Number of memory barriers committed -system.cpu0.commit.branches 5178005 # Number of branches committed +system.cpu0.commit.refs 13971736 # Number of memory references committed +system.cpu0.commit.loads 8078750 # Number of loads committed +system.cpu0.commit.membars 212403 # Number of memory barriers committed +system.cpu0.commit.branches 5205711 # Number of branches committed system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35182368 # Number of committed integer instructions. -system.cpu0.commit.function_calls 511213 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1474460 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 35286774 # Number of committed integer instructions. +system.cpu0.commit.function_calls 514203 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1480846 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123547695 # The number of ROB reads -system.cpu0.rob.rob_writes 101683929 # The number of ROB writes -system.cpu0.timesIdled 881879 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161290991 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289851507 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31079277 # Number of Instructions Simulated -system.cpu0.committedOps 39733356 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31079277 # Number of Instructions Simulated -system.cpu0.cpi 7.688032 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.688032 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130072 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130072 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 279629599 # number of integer regfile reads -system.cpu0.int_regfile_writes 45168223 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22746 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19898 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15538839 # number of misc regfile reads -system.cpu0.misc_regfile_writes 427973 # number of misc regfile writes -system.cpu0.icache.replacements 984670 # number of replacements -system.cpu0.icache.tagsinuse 511.607871 # Cycle average of tags in use -system.cpu0.icache.total_refs 10994375 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 985182 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.159740 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6536916000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 357.062519 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 154.545352 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.697388 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.301846 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999234 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5513374 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5481001 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10994375 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5513374 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5481001 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10994375 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5513374 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5481001 # number of overall hits -system.cpu0.icache.overall_hits::total 10994375 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 537943 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 527405 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065348 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 537943 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 527405 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065348 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 537943 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 527405 # number of overall misses -system.cpu0.icache.overall_misses::total 1065348 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7287778496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7022356993 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14310135489 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7287778496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7022356993 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14310135489 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7287778496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7022356993 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14310135489 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6051317 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 6008406 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12059723 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6051317 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 6008406 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12059723 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6051317 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 6008406 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12059723 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088897 # 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Average percentage of cache occupancy +system.cpu0.dcache.replacements 643954 # number of replacements +system.cpu0.dcache.tagsinuse 511.992718 # Cycle average of tags in use +system.cpu0.dcache.total_refs 21537903 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 644466 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.419766 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 318.437002 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 193.555716 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.621947 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.378039 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7070467 # 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number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1823142 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1881611 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3704753 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1823142 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1881611 # number of overall misses -system.cpu0.dcache.overall_misses::total 3704753 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6341434500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4955315500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11296750000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 54124528351 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 59881914802 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114006443153 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91205000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94667500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 185872500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 39000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 65000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 104000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 60465962851 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 64837230302 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125303193153 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 60465962851 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 64837230302 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125303193153 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7496985 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7038797 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14535782 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5174957 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5047875 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10222832 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 131875 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 125418 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257293 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127193 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120434 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247627 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12671942 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12086672 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24758614 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12671942 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12086672 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24758614 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.056892 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045354 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051305 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.269881 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.309511 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289450 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051336 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054171 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052718 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000024 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000042 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000032 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143872 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.155677 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149635 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143872 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.155677 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149635 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14867.917649 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15522.372093 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15148.071418 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38753.829485 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38327.516204 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38528.732751 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13471.935007 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13933.985870 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13703.369213 # average LoadLockedReq miss latency +system.cpu0.dcache.ReadReq_hits::cpu0.data 7114821 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6667161 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13781982 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3771949 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3489739 # 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miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045186 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051677 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.269093 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.310622 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289658 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051437 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054518 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052929 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000031 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000050 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # 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number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 607854 # number of writebacks -system.cpu0.dcache.writebacks::total 607854 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 215439 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 144497 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 359936 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1276945 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1433111 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2710056 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 667 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 710 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1377 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1492384 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1577608 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3069992 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1492384 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1577608 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3069992 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 211079 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 174740 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 385819 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119679 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129263 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248942 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6103 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6084 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12187 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 330758 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 304003 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 634761 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 330758 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 304003 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 634761 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2867323500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2359031500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5226355000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4068255992 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4371447438 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8439703430 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71165500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73921500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145087000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 88000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6935579492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6730478938 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13666058430 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6935579492 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6730478938 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13666058430 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91842786000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90513364000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356150000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14606778738 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18392840622 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 32999619360 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.writebacks::writebacks 608473 # number of writebacks +system.cpu0.dcache.writebacks::total 608473 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 221772 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 142997 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 364769 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1269356 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1442834 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2712190 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 679 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 700 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1379 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1491128 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1585831 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3076959 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1491128 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1585831 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3076959 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 213739 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 172519 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386258 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119339 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129584 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248923 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6145 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6087 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12232 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 333078 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 302103 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635181 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 333078 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 302103 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635181 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2903093500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2321765000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5224858500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3977310493 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4483624933 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8460935426 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71679000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74936000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146615000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 110000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6880403993 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6805389933 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13685793926 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6880403993 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6805389933 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13685793926 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91929858500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90426612500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356471000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14888104285 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18626460302 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33514564587 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106449564738 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 108906204622 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215355769360 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028155 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024825 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026543 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023127 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025607 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046279 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048510 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047366 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000024 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026102 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025152 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025638 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026102 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025152 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025638 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13584.124901 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13500.237496 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13546.131735 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33993.064715 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33818.242173 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33902.288204 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11660.740619 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12150.147929 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.062772 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106817962785 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109053072802 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215871035587 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028309 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024707 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026578 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023125 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025599 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024350 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046319 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048895 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047566 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000031 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025082 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025658 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025082 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025658 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13582.422955 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13458.024913 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13526.861580 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33327.834932 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34600.143019 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33990.171362 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.605370 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12310.826351 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11986.183780 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20968.742984 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22139.514867 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21529.455070 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20968.742984 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22139.514867 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21529.455070 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20657.035268 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22526.720797 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21546.289839 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20657.035268 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22526.720797 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21546.289839 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1355,324 +1325,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7102253 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5695769 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 349355 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4570648 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3841672 # Number of BTB hits +system.cpu1.branchPred.lookups 7047379 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5653088 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 345044 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4644809 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3819502 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.050927 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 676938 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35276 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 82.231627 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 672042 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34964 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25380131 # DTB read hits -system.cpu1.dtb.read_misses 40834 # DTB read misses -system.cpu1.dtb.write_hits 5811015 # DTB write hits -system.cpu1.dtb.write_misses 9771 # DTB write misses +system.cpu1.dtb.read_hits 25308350 # DTB read hits +system.cpu1.dtb.read_misses 36279 # DTB read misses +system.cpu1.dtb.write_hits 5820677 # DTB write hits +system.cpu1.dtb.write_misses 9386 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 8065 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1494 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 315 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5518 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1305 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 250 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 637 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25420965 # DTB read accesses -system.cpu1.dtb.write_accesses 5820786 # DTB write accesses +system.cpu1.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25344629 # DTB read accesses +system.cpu1.dtb.write_accesses 5830063 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31191146 # DTB hits -system.cpu1.dtb.misses 50605 # DTB misses -system.cpu1.dtb.accesses 31241751 # DTB accesses -system.cpu1.itb.inst_hits 6010554 # ITB inst hits -system.cpu1.itb.inst_misses 6924 # ITB inst misses +system.cpu1.dtb.hits 31129027 # DTB hits +system.cpu1.dtb.misses 45665 # DTB misses +system.cpu1.dtb.accesses 31174692 # DTB accesses +system.cpu1.itb.inst_hits 5997294 # ITB inst hits +system.cpu1.itb.inst_misses 6928 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2690 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2607 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1453 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6017478 # ITB inst accesses -system.cpu1.itb.hits 6010554 # DTB hits -system.cpu1.itb.misses 6924 # DTB misses -system.cpu1.itb.accesses 6017478 # DTB accesses -system.cpu1.numCycles 234669310 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6004222 # ITB inst accesses +system.cpu1.itb.hits 5997294 # DTB hits +system.cpu1.itb.misses 6928 # DTB misses +system.cpu1.itb.accesses 6004222 # DTB accesses +system.cpu1.numCycles 234192897 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15209580 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46712783 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7102253 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4518610 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10317375 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2619576 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 83943 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47843149 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1067 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2062 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 49108 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 95676 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 6008408 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 439180 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3193 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 75397416 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.769986 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.133362 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15145693 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46615728 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7047379 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4491544 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10277592 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2615595 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 81100 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47506260 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2050 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 43629 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94802 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5995185 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 443145 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3161 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74942742 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.773391 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.139188 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 65087895 86.33% 86.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 627947 0.83% 87.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 837408 1.11% 88.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1205044 1.60% 89.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1066340 1.41% 91.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 537838 0.71% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1370888 1.82% 93.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 355288 0.47% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4308768 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64672921 86.30% 86.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 620255 0.83% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 831184 1.11% 88.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1205105 1.61% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1036791 1.38% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 535666 0.71% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1369144 1.83% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 351637 0.47% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4320039 5.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 75397416 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030265 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199058 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16234163 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47629419 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9365333 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 455355 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1710994 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 954633 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86850 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54991941 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 289065 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1710994 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17174187 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18737860 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25818505 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8802452 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3151356 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51852963 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7784 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 495819 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2156102 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 16790 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53921236 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237794819 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 237752758 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42061 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38119457 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15801778 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 406275 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 360043 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6312412 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9898501 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6682455 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 887681 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1092966 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47793867 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 962748 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60992947 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 83561 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10588710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 27790687 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 254225 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 75397416 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.808953 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.518534 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74942742 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030092 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.199048 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16159158 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47296340 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9320957 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 457304 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1706877 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 946060 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86144 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54858013 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286862 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1706877 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17095317 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18544880 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25731919 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8763106 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3098607 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51692102 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7152 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 482288 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2118635 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 58 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53768769 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237295359 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 237252975 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42384 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 37974901 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15793867 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 403461 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 357400 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6244351 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9843526 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6693253 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 891235 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1110531 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47673025 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 943085 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60813772 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 81704 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10584682 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 28040387 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 237278 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74942742 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.811470 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521589 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53544512 71.02% 71.02% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6720979 8.91% 79.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3575565 4.74% 84.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2884458 3.83% 88.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6227948 8.26% 96.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1437657 1.91% 98.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 736271 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 210447 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59579 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53203952 70.99% 70.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6663470 8.89% 79.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3519082 4.70% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2892768 3.86% 88.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6218608 8.30% 96.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1439258 1.92% 98.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 735883 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 209954 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59767 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 75397416 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74942742 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24253 0.55% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 3 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4149284 94.86% 95.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 200652 4.59% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24319 0.56% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4142702 94.84% 95.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 201068 4.60% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 167588 0.27% 0.27% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28559163 46.82% 47.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46488 0.08% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 897 0.00% 47.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.18% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26112884 42.81% 89.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6105909 10.01% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 168088 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28444166 46.77% 47.05% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46611 0.08% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 900 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26040619 42.82% 89.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6113365 10.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60992947 # Type of FU issued -system.cpu1.iq.rate 0.259910 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4374192 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071716 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 201880877 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59353845 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41952881 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10603 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5821 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4743 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65193949 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5602 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 306044 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60813772 # Type of FU issued +system.cpu1.iq.rate 0.259674 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4368089 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.071827 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 201054983 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59209073 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41787342 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10574 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5911 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4752 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65008196 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5577 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 302847 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2270775 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2267035 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3168 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14837 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 853246 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14674 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 853664 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16957357 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 451019 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16940133 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 457083 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1710994 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14077639 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 237686 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48863462 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 99358 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9898501 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6682455 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 687943 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 54116 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4064 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14837 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 169399 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 135230 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 304629 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59633634 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25710347 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1359313 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1706877 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 13961840 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 229523 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48721689 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98782 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9843526 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6693253 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 669936 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49642 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3791 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14674 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 166878 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133542 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 300420 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59454145 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25635874 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1359627 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 106847 # number of nop insts executed -system.cpu1.iew.exec_refs 31763994 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5570991 # Number of branches executed -system.cpu1.iew.exec_stores 6053647 # Number of stores executed -system.cpu1.iew.exec_rate 0.254118 # Inst execution rate -system.cpu1.iew.wb_sent 59059835 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41957624 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22877560 # num instructions producing a value -system.cpu1.iew.wb_consumers 41856848 # num instructions consuming a value +system.cpu1.iew.exec_nop 105579 # number of nop insts executed +system.cpu1.iew.exec_refs 31697240 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5530994 # Number of branches executed +system.cpu1.iew.exec_stores 6061366 # Number of stores executed +system.cpu1.iew.exec_rate 0.253868 # Inst execution rate +system.cpu1.iew.wb_sent 58875000 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41792094 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22753184 # num instructions producing a value +system.cpu1.iew.wb_consumers 41716740 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178795 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.546567 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178452 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.545421 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10488461 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 708523 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 263786 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73686422 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.514905 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.496046 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10509796 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 705807 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 260176 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73235865 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.516331 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.496791 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60141742 81.62% 81.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6665026 9.05% 90.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1916982 2.60% 93.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1022287 1.39% 94.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 952512 1.29% 95.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 518669 0.70% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 704589 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 372223 0.51% 98.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1392392 1.89% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59723279 81.55% 81.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6657456 9.09% 90.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1906988 2.60% 93.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1010218 1.38% 94.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 959564 1.31% 95.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 524950 0.72% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 702340 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 373722 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1377348 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73686422 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29303210 # Number of instructions committed -system.cpu1.commit.committedOps 37941475 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73235865 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29175677 # Number of instructions committed +system.cpu1.commit.committedOps 37813970 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13456935 # Number of memory references committed -system.cpu1.commit.loads 7627726 # Number of loads committed -system.cpu1.commit.membars 192181 # Number of memory barriers committed -system.cpu1.commit.branches 4783662 # Number of branches committed +system.cpu1.commit.refs 13416080 # Number of memory references committed +system.cpu1.commit.loads 7576491 # Number of loads committed +system.cpu1.commit.membars 191234 # Number of memory barriers committed +system.cpu1.commit.branches 4755917 # Number of branches committed system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33675461 # Number of committed integer instructions. -system.cpu1.commit.function_calls 480108 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1392392 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 33570741 # Number of committed integer instructions. +system.cpu1.commit.function_calls 477112 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1377348 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119835622 # The number of ROB reads -system.cpu1.rob.rob_writes 98622587 # The number of ROB writes -system.cpu1.timesIdled 873829 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159271894 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285541005 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29230871 # Number of Instructions Simulated -system.cpu1.committedOps 37869136 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29230871 # Number of Instructions Simulated -system.cpu1.cpi 8.028133 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.028133 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124562 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124562 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 270257014 # number of integer regfile reads -system.cpu1.int_regfile_writes 43086162 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22099 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19636 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14849439 # number of misc regfile reads -system.cpu1.misc_regfile_writes 404495 # number of misc regfile writes +system.cpu1.rob.rob_reads 119309924 # The number of ROB reads +system.cpu1.rob.rob_writes 98406667 # The number of ROB writes +system.cpu1.timesIdled 873323 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159250155 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285809379 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29104625 # Number of Instructions Simulated +system.cpu1.committedOps 37742918 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29104625 # Number of Instructions Simulated +system.cpu1.cpi 8.046587 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.046587 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124276 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124276 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 269354983 # number of integer regfile reads +system.cpu1.int_regfile_writes 42881539 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22070 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19722 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14807942 # number of misc regfile reads +system.cpu1.misc_regfile_writes 402452 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1687,17 +1657,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192737213912 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192737213912 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192737213912 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192737213912 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192818443837 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192818443837 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83053 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83054 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |