diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt | 2285 |
1 files changed, 1168 insertions, 1117 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 0d43a2133..120ee67e1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,140 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.904683 # Number of seconds simulated -sim_ticks 2904682547500 # Number of ticks simulated -final_tick 2904682547500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.904915 # Number of seconds simulated +sim_ticks 2904914753500 # Number of ticks simulated +final_tick 2904914753500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 744036 # Simulator instruction rate (inst/s) -host_op_rate 897074 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19213049576 # Simulator tick rate (ticks/s) -host_mem_usage 562336 # Number of bytes of host memory used -host_seconds 151.18 # Real time elapsed on the host -sim_insts 112485415 # Number of instructions simulated -sim_ops 135622211 # Number of ops (including micro ops) simulated +host_inst_rate 754235 # Simulator instruction rate (inst/s) +host_op_rate 909375 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19474929667 # Simulator tick rate (ticks/s) +host_mem_usage 559844 # Number of bytes of host memory used +host_seconds 149.16 # Real time elapsed on the host +sim_insts 112502966 # Number of instructions simulated +sim_ops 135643907 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 557732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4265248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 552740 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4263328 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 631552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4773892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 636352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4758276 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10229960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 557732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 631552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1189284 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5300352 # Number of bytes written to this memory +system.physmem.bytes_read::total 10212232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 552740 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 636352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1189092 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7616448 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 7636212 # Number of bytes written to this memory +system.physmem.bytes_written::total 7633972 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 67163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17090 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 67133 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9868 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74593 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9943 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74349 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168816 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 82818 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168539 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119007 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123423 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123388 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 192011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1468404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 190278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1467626 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 217425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1643516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3521886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 192011 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 217425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409437 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1824761 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 219060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1638009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3515501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 190278 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 219060 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 409338 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2621918 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6030 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 798137 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2628932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1824761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2627950 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2621918 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 192011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1474434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 190278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1473656 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 217425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1643519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 798468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6150817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168816 # Number of read requests accepted -system.physmem.writeReqs 123423 # Number of write requests accepted -system.physmem.readBursts 168816 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123423 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10794880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue -system.physmem.bytesWritten 7651200 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10229960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7636212 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9768 # Per bank write bursts -system.physmem.perBankRdBursts::1 9653 # Per bank write bursts -system.physmem.perBankRdBursts::2 10324 # Per bank write bursts -system.physmem.perBankRdBursts::3 9994 # Per bank write bursts -system.physmem.perBankRdBursts::4 18675 # Per bank write bursts -system.physmem.perBankRdBursts::5 10148 # Per bank write bursts -system.physmem.perBankRdBursts::6 10372 # Per bank write bursts -system.physmem.perBankRdBursts::7 10429 # Per bank write bursts -system.physmem.perBankRdBursts::8 9938 # Per bank write bursts -system.physmem.perBankRdBursts::9 10451 # Per bank write bursts -system.physmem.perBankRdBursts::10 9811 # Per bank write bursts -system.physmem.perBankRdBursts::11 9561 # Per bank write bursts -system.physmem.perBankRdBursts::12 9986 # Per bank write bursts -system.physmem.perBankRdBursts::13 9803 # Per bank write bursts -system.physmem.perBankRdBursts::14 9966 # Per bank write bursts -system.physmem.perBankRdBursts::15 9791 # Per bank write bursts -system.physmem.perBankWrBursts::0 7253 # Per bank write bursts -system.physmem.perBankWrBursts::1 7191 # Per bank write bursts -system.physmem.perBankWrBursts::2 8157 # Per bank write bursts -system.physmem.perBankWrBursts::3 7614 # Per bank write bursts -system.physmem.perBankWrBursts::4 7092 # Per bank write bursts -system.physmem.perBankWrBursts::5 7380 # Per bank write bursts -system.physmem.perBankWrBursts::6 7560 # Per bank write bursts -system.physmem.perBankWrBursts::7 7725 # Per bank write bursts -system.physmem.perBankWrBursts::8 7575 # Per bank write bursts -system.physmem.perBankWrBursts::9 8007 # Per bank write bursts -system.physmem.perBankWrBursts::10 7415 # Per bank write bursts -system.physmem.perBankWrBursts::11 7436 # Per bank write bursts -system.physmem.perBankWrBursts::12 7462 # Per bank write bursts -system.physmem.perBankWrBursts::13 7248 # Per bank write bursts -system.physmem.perBankWrBursts::14 7309 # Per bank write bursts -system.physmem.perBankWrBursts::15 7126 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 219060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1638012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6143452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168539 # Number of read requests accepted +system.physmem.writeReqs 159612 # Number of write requests accepted +system.physmem.readBursts 168539 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159612 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10780160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue +system.physmem.bytesWritten 9866880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10212232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9952308 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5435 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4495 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9752 # Per bank write bursts +system.physmem.perBankRdBursts::1 9630 # Per bank write bursts +system.physmem.perBankRdBursts::2 10293 # Per bank write bursts +system.physmem.perBankRdBursts::3 9989 # Per bank write bursts +system.physmem.perBankRdBursts::4 18671 # Per bank write bursts +system.physmem.perBankRdBursts::5 10140 # Per bank write bursts +system.physmem.perBankRdBursts::6 10341 # Per bank write bursts +system.physmem.perBankRdBursts::7 10423 # Per bank write bursts +system.physmem.perBankRdBursts::8 9932 # Per bank write bursts +system.physmem.perBankRdBursts::9 10445 # Per bank write bursts +system.physmem.perBankRdBursts::10 9791 # Per bank write bursts +system.physmem.perBankRdBursts::11 9555 # Per bank write bursts +system.physmem.perBankRdBursts::12 9939 # Per bank write bursts +system.physmem.perBankRdBursts::13 9802 # Per bank write bursts +system.physmem.perBankRdBursts::14 9961 # Per bank write bursts +system.physmem.perBankRdBursts::15 9776 # Per bank write bursts +system.physmem.perBankWrBursts::0 9466 # Per bank write bursts +system.physmem.perBankWrBursts::1 9312 # Per bank write bursts +system.physmem.perBankWrBursts::2 10445 # Per bank write bursts +system.physmem.perBankWrBursts::3 9717 # Per bank write bursts +system.physmem.perBankWrBursts::4 9000 # Per bank write bursts +system.physmem.perBankWrBursts::5 9463 # Per bank write bursts +system.physmem.perBankWrBursts::6 9580 # Per bank write bursts +system.physmem.perBankWrBursts::7 9878 # Per bank write bursts +system.physmem.perBankWrBursts::8 9939 # Per bank write bursts +system.physmem.perBankWrBursts::9 10290 # Per bank write bursts +system.physmem.perBankWrBursts::10 9717 # Per bank write bursts +system.physmem.perBankWrBursts::11 9744 # Per bank write bursts +system.physmem.perBankWrBursts::12 9808 # Per bank write bursts +system.physmem.perBankWrBursts::13 9372 # Per bank write bursts +system.physmem.perBankWrBursts::14 9292 # Per bank write bursts +system.physmem.perBankWrBursts::15 9147 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2904682181000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2904914374000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159244 # Read request sizes (log2) +system.physmem.readPktSize::6 158967 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 119042 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see +system.physmem.writePktSize::6 155231 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 244 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -164,170 +161,194 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58500 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 315.315419 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.678002 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.865134 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21233 36.30% 36.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14762 25.23% 61.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5741 9.81% 71.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3177 5.43% 76.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2294 3.92% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1562 2.67% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1019 1.74% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1097 1.88% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7615 13.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58500 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5866 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.752472 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 562.127013 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5865 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 10608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60664 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 340.349730 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 196.021429 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 354.920810 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21349 35.19% 35.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14624 24.11% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5778 9.52% 68.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3154 5.20% 74.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2318 3.82% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1542 2.54% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1044 1.72% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1115 1.84% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9740 16.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60664 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6204 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.148614 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 546.636063 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6203 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5866 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.380157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.599784 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.515949 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 16 0.27% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 10 0.17% 0.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 13 0.22% 0.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 18 0.31% 0.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4930 84.04% 85.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 59 1.01% 86.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 57 0.97% 86.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 249 4.24% 91.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 210 3.58% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.34% 95.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 11 0.19% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.14% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 30 0.51% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.09% 96.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.07% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.05% 96.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 157 2.68% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.07% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 19 0.32% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 6 0.10% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.10% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 6 0.10% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.12% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5866 # Writes before turning the bus around for reads -system.physmem.totQLat 1486855250 # Total ticks spent queuing -system.physmem.totMemAccLat 4649417750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 843350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8815.17 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6204 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6204 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.850097 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.346548 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.047003 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 14 0.23% 0.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 12 0.19% 0.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 8 0.13% 0.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 18 0.29% 0.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4939 79.61% 80.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 68 1.10% 81.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 50 0.81% 82.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 255 4.11% 86.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 123 1.98% 88.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 43 0.69% 89.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 46 0.74% 89.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 38 0.61% 90.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 127 2.05% 92.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.18% 92.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 16 0.26% 92.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.13% 93.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 34 0.55% 93.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 17 0.27% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 13 0.21% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 28 0.45% 94.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 70 1.13% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 11 0.18% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 7 0.11% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 13 0.21% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 92 1.48% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 97.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 13 0.21% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 5 0.08% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 13 0.21% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.06% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 6 0.10% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 29 0.47% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 12 0.19% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 7 0.11% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 6 0.10% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 6 0.10% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 4 0.06% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.06% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 6 0.10% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 2 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6204 # Writes before turning the bus around for reads +system.physmem.totQLat 1487388750 # Total ticks spent queuing +system.physmem.totMemAccLat 4645638750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 842200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8830.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27565.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27580.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.43 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.56 # Average write queue length when enqueuing -system.physmem.readRowHits 139006 # Number of row buffer hits during reads -system.physmem.writeRowHits 90713 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.41 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.88 # Row buffer hit rate for writes -system.physmem.avgGap 9939406.38 # Average gap between requests -system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2756105768250 # Time in different power states -system.physmem.memoryStateTime::REF 96993520000 # Time in different power states +system.physmem.avgWrQLen 11.55 # Average write queue length when enqueuing +system.physmem.readRowHits 138839 # Number of row buffer hits during reads +system.physmem.writeRowHits 123106 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.85 # Row buffer hit rate for writes +system.physmem.avgGap 8852370.93 # Average gap between requests +system.physmem.pageHitRate 81.19 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2756204372250 # Time in different power states +system.physmem.memoryStateTime::REF 97001320000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 51577106750 # Time in different power states +system.physmem.memoryStateTime::ACT 51708967750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 224736120 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 217523880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 122623875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 118688625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 697031400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 618579000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 388618560 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 386065440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 189719325120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 189719325120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86946648885 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 86006740545 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1666536838500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1667361319500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1944635822460 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1944428242110 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.484503 # Core power per rank (mW) -system.physmem.averagePower::1 669.413038 # Core power per rank (mW) +system.physmem.actEnergy::0 232462440 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 226157400 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 126839625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 123399375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 696064200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 617760000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 498059280 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 500962320 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 189734581920 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 189734581920 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 86971409685 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 86091461640 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1666655279250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1667427163500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1944914696400 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1944721486155 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.526666 # Core power per rank (mW) +system.physmem.averagePower::1 669.460155 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -370,25 +391,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12289553 # DTB read hits -system.cpu0.dtb.read_misses 5977 # DTB read misses -system.cpu0.dtb.write_hits 9834643 # DTB write hits -system.cpu0.dtb.write_misses 1047 # DTB write misses -system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12308215 # DTB read hits +system.cpu0.dtb.read_misses 6223 # DTB read misses +system.cpu0.dtb.write_hits 9796614 # DTB write hits +system.cpu0.dtb.write_misses 1025 # DTB write misses +system.cpu0.dtb.flush_tlb 2937 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4657 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4667 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 865 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 862 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12295530 # DTB read accesses -system.cpu0.dtb.write_accesses 9835690 # DTB write accesses +system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12314438 # DTB read accesses +system.cpu0.dtb.write_accesses 9797639 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 22124196 # DTB hits -system.cpu0.dtb.misses 7024 # DTB misses -system.cpu0.dtb.accesses 22131220 # DTB accesses +system.cpu0.dtb.hits 22104829 # DTB hits +system.cpu0.dtb.misses 7248 # DTB misses +system.cpu0.dtb.accesses 22112077 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -410,224 +431,228 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 58032770 # ITB inst hits -system.cpu0.itb.inst_misses 3465 # ITB inst misses +system.cpu0.itb.inst_hits 58194599 # ITB inst hits +system.cpu0.itb.inst_misses 3600 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 2937 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2765 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 58036235 # ITB inst accesses -system.cpu0.itb.hits 58032770 # DTB hits -system.cpu0.itb.misses 3465 # DTB misses -system.cpu0.itb.accesses 58036235 # DTB accesses -system.cpu0.numCycles 2905319694 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 58198199 # ITB inst accesses +system.cpu0.itb.hits 58194599 # DTB hits +system.cpu0.itb.misses 3600 # DTB misses +system.cpu0.itb.accesses 58198199 # DTB accesses +system.cpu0.numCycles 2905784484 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 56513131 # Number of instructions committed -system.cpu0.committedOps 68067849 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60172046 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 6287 # Number of float alu accesses -system.cpu0.num_func_calls 4924583 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7649378 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60172046 # number of integer instructions -system.cpu0.num_fp_insts 6287 # number of float instructions -system.cpu0.num_int_register_reads 109432768 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41532346 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4990 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 245794871 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26123486 # number of times the CC registers were written -system.cpu0.num_mem_refs 22763364 # number of memory refs -system.cpu0.num_load_insts 12450622 # Number of load instructions -system.cpu0.num_store_insts 10312742 # Number of store instructions -system.cpu0.num_idle_cycles 2685746001.120693 # Number of idle cycles -system.cpu0.num_busy_cycles 219573692.879307 # Number of busy cycles -system.cpu0.not_idle_fraction 0.075576 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.924424 # Percentage of idle cycles -system.cpu0.Branches 12983457 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46789630 67.21% 67.21% # Class of executed instruction -system.cpu0.op_class::IntMult 58620 0.08% 67.30% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4273 0.01% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::MemRead 12450622 17.88% 85.19% # Class of executed instruction -system.cpu0.op_class::MemWrite 10312742 14.81% 100.00% # Class of executed instruction +system.cpu0.committedInsts 56652370 # Number of instructions committed +system.cpu0.committedOps 68154355 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 60226518 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5995 # Number of float alu accesses +system.cpu0.num_func_calls 4919534 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7679282 # number of instructions that are conditional controls +system.cpu0.num_int_insts 60226518 # number of integer instructions +system.cpu0.num_fp_insts 5995 # number of float instructions +system.cpu0.num_int_register_reads 109459523 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41576844 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4468 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1530 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 246082665 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 26221599 # number of times the CC registers were written +system.cpu0.num_mem_refs 22745945 # number of memory refs +system.cpu0.num_load_insts 12471278 # Number of load instructions +system.cpu0.num_store_insts 10274667 # Number of store instructions +system.cpu0.num_idle_cycles 2686990403.807933 # Number of idle cycles +system.cpu0.num_busy_cycles 218794080.192067 # Number of busy cycles +system.cpu0.not_idle_fraction 0.075296 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.924704 # Percentage of idle cycles +system.cpu0.Branches 13013332 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46892920 67.27% 67.28% # Class of executed instruction +system.cpu0.op_class::IntMult 58660 0.08% 67.36% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4258 0.01% 67.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.37% # Class of executed instruction +system.cpu0.op_class::MemRead 12471278 17.89% 85.26% # Class of executed instruction +system.cpu0.op_class::MemWrite 10274667 14.74% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 69618091 # Class of executed instruction +system.cpu0.op_class::total 69703986 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 822992 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.850755 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43241503 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 823504 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.509160 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 3038 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 822947 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.850765 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43250055 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 823459 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.522415 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.068917 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.781838 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625135 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374574 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.083666 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.767099 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625163 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374545 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999709 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177151535 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177151535 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11581583 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11533865 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23115448 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9437909 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9389790 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18827699 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199753 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192262 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392015 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 227025 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 216269 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443294 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 235239 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 225055 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460294 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 21019492 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20923655 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41943147 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 21219245 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21115917 # number of overall hits -system.cpu0.dcache.overall_hits::total 42335162 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197297 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 205526 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 402823 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 150193 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 148466 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298659 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58530 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 60464 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118994 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 11127 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11645 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22772 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 177185510 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177185510 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11600521 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11519661 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23120182 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9401520 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9429674 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18831194 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 198556 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 193555 # 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number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 61059 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 116833 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4098 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4464 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8562 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 347203 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 353664 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 700867 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 404842 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 412886 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 817728 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2467868750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2647702500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5115571250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5416592829 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5704580119 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11121172948 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 696038250 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 742244000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1438282250 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48274750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52699750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100974500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 47998 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 47998 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884461579 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8352282619 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16236744198 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8580499829 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9094526619 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 17675026448 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2688395000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3103027500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791422500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2165315000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2264487500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429802500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4853710000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5367515000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221225000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016726 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017479 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017102 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015665 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015565 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015615 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223162 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.234333 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228687 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017195 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019582 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018362 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 347139 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 353700 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 700839 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 402913 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 414759 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 817672 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2517898250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2600172750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5118071000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5366137441 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5759365015 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11125502456 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 677278250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 762448500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1439726750 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48257750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52710750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100968500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 73500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 73500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 147000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884035691 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8359537765 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16243573456 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8561313941 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9121986265 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 17683300206 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2688812000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3102617000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791429000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2186315500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2243484000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429799500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4875127500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5346101000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221228500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016885 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017304 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017094 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015745 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.218539 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.238633 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228599 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017166 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019626 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018366 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016250 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016621 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016435 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018721 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019177 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018948 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12526.616669 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12903.159388 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12718.720786 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36064.216235 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38423.478231 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37237.026000 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12075.821059 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12533.247780 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12307.632572 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11788.705739 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11808.144746 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11798.843188 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23999 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23999 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.506490 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23616.434296 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.655297 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.687876 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22026.725583 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21614.799112 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016260 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016603 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016431 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018649 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019238 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018943 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12637.196667 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12818.141148 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12728.480263 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36283.672367 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38179.669835 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37241.048179 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12143.261197 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12487.078072 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12322.946000 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11775.927282 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11807.963710 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11792.630227 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 73500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 73500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22711.466274 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23634.542734 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23177.325257 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21248.542343 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21993.461902 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21626.398123 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -749,79 +778,79 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1698167 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.774848 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113885267 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1698679 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.043430 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1699785 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.774941 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113901535 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1700297 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 66.989200 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 25359588250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 419.089773 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 91.685075 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.818535 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.179072 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 418.326028 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 92.448913 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.817043 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.180564 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.997607 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117282637 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117282637 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 57188138 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 56697129 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113885267 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 57188138 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 56697129 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113885267 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13702.014876 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -830,46 +859,46 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 844632 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 854053 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1698685 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 844632 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11699.709629 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014572 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014847 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014572 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014847 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014708 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014572 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11698.151448 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency @@ -898,25 +927,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12236392 # DTB read hits -system.cpu1.dtb.read_misses 5657 # DTB read misses -system.cpu1.dtb.write_hits 9775692 # DTB write hits -system.cpu1.dtb.write_misses 790 # DTB write misses -system.cpu1.dtb.flush_tlb 2934 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 12222550 # DTB read hits +system.cpu1.dtb.read_misses 5478 # DTB read misses +system.cpu1.dtb.write_hits 9817405 # DTB write hits +system.cpu1.dtb.write_misses 801 # DTB write misses +system.cpu1.dtb.flush_tlb 2935 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4044 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4101 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 918 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 936 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12242049 # DTB read accesses -system.cpu1.dtb.write_accesses 9776482 # DTB write accesses +system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12228028 # DTB read accesses +system.cpu1.dtb.write_accesses 9818206 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22012084 # DTB hits -system.cpu1.dtb.misses 6447 # DTB misses -system.cpu1.dtb.accesses 22018531 # DTB accesses +system.cpu1.dtb.hits 22039955 # DTB hits +system.cpu1.dtb.misses 6279 # DTB misses +system.cpu1.dtb.accesses 22046234 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -938,93 +967,94 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 57551182 # ITB inst hits -system.cpu1.itb.inst_misses 3277 # ITB inst misses +system.cpu1.itb.inst_hits 57407239 # ITB inst hits +system.cpu1.itb.inst_misses 3155 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2934 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 2935 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2396 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2356 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 57554459 # ITB inst accesses -system.cpu1.itb.hits 57551182 # DTB hits -system.cpu1.itb.misses 3277 # DTB misses -system.cpu1.itb.accesses 57554459 # DTB accesses -system.cpu1.numCycles 2904045401 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 57410394 # ITB inst accesses +system.cpu1.itb.hits 57407239 # DTB hits +system.cpu1.itb.misses 3155 # DTB misses +system.cpu1.itb.accesses 57410394 # DTB accesses +system.cpu1.numCycles 2904045023 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 55972284 # Number of instructions committed -system.cpu1.committedOps 67554362 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 59752131 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5003 # Number of float alu accesses -system.cpu1.num_func_calls 4972365 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7584533 # number of instructions that are conditional controls -system.cpu1.num_int_insts 59752131 # number of integer instructions -system.cpu1.num_fp_insts 5003 # number of float instructions -system.cpu1.num_int_register_reads 108688988 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41135378 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3588 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 244071190 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 25783552 # number of times the CC registers were written -system.cpu1.num_mem_refs 22653716 # number of memory refs -system.cpu1.num_load_insts 12397911 # Number of load instructions -system.cpu1.num_store_insts 10255805 # Number of store instructions -system.cpu1.num_idle_cycles 2693922745.089012 # Number of idle cycles -system.cpu1.num_busy_cycles 210122655.910988 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072355 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927645 # Percentage of idle cycles -system.cpu1.Branches 12941389 # Number of branches fetched -system.cpu1.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 46411475 67.14% 67.14% # Class of executed instruction -system.cpu1.op_class::IntMult 56055 0.08% 67.22% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4164 0.01% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::MemRead 12397911 17.94% 85.16% # Class of executed instruction -system.cpu1.op_class::MemWrite 10255805 14.84% 100.00% # Class of executed instruction +system.cpu1.committedInsts 55850596 # Number of instructions committed +system.cpu1.committedOps 67489552 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 59717976 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5231 # Number of float alu accesses +system.cpu1.num_func_calls 4978644 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7556287 # number of instructions that are conditional controls +system.cpu1.num_int_insts 59717976 # number of integer instructions +system.cpu1.num_fp_insts 5231 # number of float instructions +system.cpu1.num_int_register_reads 108697708 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41105654 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4046 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1186 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 243864682 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 25692319 # number of times the CC registers were written +system.cpu1.num_mem_refs 22680019 # number of memory refs +system.cpu1.num_load_insts 12382292 # Number of load instructions +system.cpu1.num_store_insts 10297727 # Number of store instructions +system.cpu1.num_idle_cycles 2693854199.172201 # Number of idle cycles +system.cpu1.num_busy_cycles 210190823.827799 # Number of busy cycles +system.cpu1.not_idle_fraction 0.072379 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.927621 # Percentage of idle cycles +system.cpu1.Branches 12914403 # Number of branches fetched +system.cpu1.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 46321486 67.07% 67.07% # Class of executed instruction +system.cpu1.op_class::IntMult 56040 0.08% 67.15% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4215 0.01% 67.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.16% # Class of executed instruction +system.cpu1.op_class::MemRead 12382292 17.93% 85.09% # Class of executed instruction +system.cpu1.op_class::MemWrite 10297727 14.91% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69125543 # Class of executed instruction +system.cpu1.op_class::total 69061894 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iobus.trans_dist::ReadReq 30195 # Transaction distribution system.iobus.trans_dist::ReadResp 30195 # Transaction distribution system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1115,38 +1145,40 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347067538 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804759 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36804503 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.083103 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084296 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309429741000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.083103 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067694 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067694 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 309429812000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084296 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067768 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067768 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9591408658 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9591408658 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles @@ -1161,288 +1193,303 @@ system.iocache.overall_accesses::realview.ide 234 system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264780.495197 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264780.495197 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 55572 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7176 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.744147 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2203719731 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2203719731 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7707754664 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7707754664 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212780.329726 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212780.329726 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 89435 # number of replacements -system.l2c.tags.tagsinuse 64928.071220 # Cycle average of tags in use -system.l2c.tags.total_refs 2766032 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 64927.975067 # Cycle average of tags in use +system.l2c.tags.total_refs 2767630 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 154676 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.882748 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 17.893080 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50556.019197 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943993 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 50554.064375 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943925 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3889.866505 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2064.899938 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768384 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5760.330465 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2651.242275 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.771424 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 3889.108934 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2070.927660 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768402 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5762.879674 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2645.281633 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.771394 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059355 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.031508 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.059343 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.031600 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000073 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.087896 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.040455 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.990724 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.087935 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.040364 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.990722 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65236 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6815 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56246 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6816 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56245 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.995422 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26292076 # Number of tag accesses -system.l2c.tags.data_accesses 26292076 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6208 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3383 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 836467 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 253621 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5323 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2799 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 844177 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 261864 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2213842 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 686960 # number of Writeback hits -system.l2c.Writeback_hits::total 686960 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits +system.l2c.tags.tag_accesses 26305647 # Number of tag accesses +system.l2c.tags.data_accesses 26305647 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6459 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3454 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 839902 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 253579 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5229 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2754 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 842358 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 261770 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2215505 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 686899 # number of Writeback hits +system.l2c.Writeback_hits::total 686899 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 11 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 86549 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78519 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 165068 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6208 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3383 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 836467 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 340170 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5323 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2799 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 844177 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 340383 # number of demand (read+write) hits -system.l2c.demand_hits::total 2378910 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6208 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3383 # number of overall hits -system.l2c.overall_hits::cpu0.inst 836467 # number of overall hits -system.l2c.overall_hits::cpu0.data 340170 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5323 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2799 # number of overall hits -system.l2c.overall_hits::cpu1.inst 844177 # number of overall hits -system.l2c.overall_hits::cpu1.data 340383 # number of overall hits -system.l2c.overall_hits::total 2378910 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 84423 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 80742 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 165165 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6459 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3454 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 839902 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 338002 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5229 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2754 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 842358 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 342512 # number of demand (read+write) hits +system.l2c.demand_hits::total 2380670 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6459 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3454 # number of overall hits +system.l2c.overall_hits::cpu0.inst 839902 # number of overall hits +system.l2c.overall_hits::cpu0.data 338002 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5229 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2754 # number of overall hits +system.l2c.overall_hits::cpu1.inst 842358 # number of overall hits +system.l2c.overall_hits::cpu1.data 342512 # number of overall hits +system.l2c.overall_hits::total 2380670 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 8151 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5123 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 8073 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5538 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9868 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 7019 # number of ReadReq misses -system.l2c.ReadReq_misses::total 30170 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1297 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1431 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses +system.l2c.ReadReq_misses::cpu1.inst 9945 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6604 # number of ReadReq misses +system.l2c.ReadReq_misses::total 30169 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1350 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1371 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2721 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 62336 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 68504 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130840 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 62109 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60112.752384 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57307.407335 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60084.515606 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56618.658303 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57321.604441 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59800.427350 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56812.065606 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57370.855040 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59942.185008 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57386.469559 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60112.752384 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57307.407335 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60084.515606 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56618.658303 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57321.604441 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59800.427350 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56812.065606 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57370.855040 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1604,57 +1655,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70576 # Transaction distribution -system.membus.trans_dist::ReadResp 70576 # Transaction distribution +system.membus.trans_dist::ReadReq 70575 # Transaction distribution +system.membus.trans_dist::ReadResp 70575 # Transaction distribution system.membus.trans_dist::WriteReq 27613 # Transaction distribution system.membus.trans_dist::WriteResp 27613 # Transaction distribution -system.membus.trans_dist::Writeback 82818 # Transaction distribution +system.membus.trans_dist::Writeback 119007 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4495 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution -system.membus.trans_dist::ReadExReq 129059 # Transaction distribution -system.membus.trans_dist::ReadExResp 129059 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4497 # Transaction distribution +system.membus.trans_dist::ReadExReq 129060 # Transaction distribution +system.membus.trans_dist::ReadExResp 129060 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438204 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 545868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 618565 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 437896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 545560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 654447 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15546876 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15710301 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18029597 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 219 # Total snoops (count) -system.membus.snoop_fanout::samples 283019 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15529084 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15692509 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20327965 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 498 # Total snoops (count) +system.membus.snoop_fanout::samples 319191 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 283019 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 319191 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 283019 # Request fanout histogram -system.membus.reqLayer0.occupancy 87171000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 319191 # Request fanout histogram +system.membus.reqLayer0.occupancy 87172500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1736000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1735000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1336695000 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1640329489 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1662315000 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 1640286255 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38340241 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38333497 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1687,54 +1738,54 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2301469 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2301454 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2303097 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2303082 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 686960 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36226 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 686899 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2744 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2753 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295908 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295908 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415392 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457281 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18122 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34351 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5925146 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96868901 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24732 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46156 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205690309 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 53730 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3283144 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.011105 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104794 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 2746 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295999 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295999 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3418625 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457116 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18180 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34622 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5928543 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108853880 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96862117 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24836 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205787617 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 53694 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3284793 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.011099 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104766 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3246684 98.89% 98.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36460 1.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3248335 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3283144 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4418882248 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3284793 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4419462750 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 7658490749 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 7665779999 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3782924511 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3782690745 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11939000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11971000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22834207 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22951201 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |