diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt | 2139 |
1 files changed, 1151 insertions, 988 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 120ee67e1..15d0bc0bd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.904915 # Number of seconds simulated -sim_ticks 2904914753500 # Number of ticks simulated -final_tick 2904914753500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.904914 # Number of seconds simulated +sim_ticks 2904913754500 # Number of ticks simulated +final_tick 2904913754500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 754235 # Simulator instruction rate (inst/s) -host_op_rate 909375 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19474929667 # Simulator tick rate (ticks/s) -host_mem_usage 559844 # Number of bytes of host memory used -host_seconds 149.16 # Real time elapsed on the host -sim_insts 112502966 # Number of instructions simulated -sim_ops 135643907 # Number of ops (including micro ops) simulated +host_inst_rate 719084 # Simulator instruction rate (inst/s) +host_op_rate 866994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18567568294 # Simulator tick rate (ticks/s) +host_mem_usage 616260 # Number of bytes of host memory used +host_seconds 156.45 # Real time elapsed on the host +sim_insts 112501381 # Number of instructions simulated +sim_ops 135642071 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 552740 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4263328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 553252 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4270880 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 636352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4758276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 635584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4758596 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10212232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 552740 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 636352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1189092 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7616448 # Number of bytes written to this memory +system.physmem.bytes_read::total 10219848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 553252 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 635584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1188836 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7620224 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 7633972 # Number of bytes written to this memory +system.physmem.bytes_written::total 7637748 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17090 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 67133 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17098 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 67251 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9943 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74349 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74354 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168539 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119007 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168658 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119066 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123388 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123447 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 190278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1467626 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 190454 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1470226 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 219060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1638009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 218796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1638120 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3515501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 190278 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 219060 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2621918 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3518124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 190454 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 218796 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 409250 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2623219 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6030 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2627950 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2621918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2629251 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2623219 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 190278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1473656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 190454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1476256 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 219060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1638012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 218796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1638122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6143452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168539 # Number of read requests accepted -system.physmem.writeReqs 159612 # Number of write requests accepted -system.physmem.readBursts 168539 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159612 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10780160 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue -system.physmem.bytesWritten 9866880 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10212232 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9952308 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5435 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 6147376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168658 # Number of read requests accepted +system.physmem.writeReqs 159671 # Number of write requests accepted +system.physmem.readBursts 168658 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159671 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10788160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue +system.physmem.bytesWritten 9869632 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10219848 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9956084 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5450 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4495 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9752 # Per bank write bursts -system.physmem.perBankRdBursts::1 9630 # Per bank write bursts -system.physmem.perBankRdBursts::2 10293 # Per bank write bursts -system.physmem.perBankRdBursts::3 9989 # Per bank write bursts -system.physmem.perBankRdBursts::4 18671 # Per bank write bursts +system.physmem.perBankRdBursts::0 9771 # Per bank write bursts +system.physmem.perBankRdBursts::1 9508 # Per bank write bursts +system.physmem.perBankRdBursts::2 10210 # Per bank write bursts +system.physmem.perBankRdBursts::3 9949 # Per bank write bursts +system.physmem.perBankRdBursts::4 18798 # Per bank write bursts system.physmem.perBankRdBursts::5 10140 # Per bank write bursts -system.physmem.perBankRdBursts::6 10341 # Per bank write bursts -system.physmem.perBankRdBursts::7 10423 # Per bank write bursts +system.physmem.perBankRdBursts::6 10351 # Per bank write bursts +system.physmem.perBankRdBursts::7 10416 # Per bank write bursts system.physmem.perBankRdBursts::8 9932 # Per bank write bursts -system.physmem.perBankRdBursts::9 10445 # Per bank write bursts -system.physmem.perBankRdBursts::10 9791 # Per bank write bursts -system.physmem.perBankRdBursts::11 9555 # Per bank write bursts -system.physmem.perBankRdBursts::12 9939 # Per bank write bursts -system.physmem.perBankRdBursts::13 9802 # Per bank write bursts +system.physmem.perBankRdBursts::9 10416 # Per bank write bursts +system.physmem.perBankRdBursts::10 9794 # Per bank write bursts +system.physmem.perBankRdBursts::11 9556 # Per bank write bursts +system.physmem.perBankRdBursts::12 10053 # Per bank write bursts +system.physmem.perBankRdBursts::13 9934 # Per bank write bursts system.physmem.perBankRdBursts::14 9961 # Per bank write bursts system.physmem.perBankRdBursts::15 9776 # Per bank write bursts -system.physmem.perBankWrBursts::0 9466 # Per bank write bursts -system.physmem.perBankWrBursts::1 9312 # Per bank write bursts -system.physmem.perBankWrBursts::2 10445 # Per bank write bursts -system.physmem.perBankWrBursts::3 9717 # Per bank write bursts -system.physmem.perBankWrBursts::4 9000 # Per bank write bursts -system.physmem.perBankWrBursts::5 9463 # Per bank write bursts -system.physmem.perBankWrBursts::6 9580 # Per bank write bursts -system.physmem.perBankWrBursts::7 9878 # Per bank write bursts -system.physmem.perBankWrBursts::8 9939 # Per bank write bursts -system.physmem.perBankWrBursts::9 10290 # Per bank write bursts -system.physmem.perBankWrBursts::10 9717 # Per bank write bursts -system.physmem.perBankWrBursts::11 9744 # Per bank write bursts -system.physmem.perBankWrBursts::12 9808 # Per bank write bursts -system.physmem.perBankWrBursts::13 9372 # Per bank write bursts -system.physmem.perBankWrBursts::14 9292 # Per bank write bursts -system.physmem.perBankWrBursts::15 9147 # Per bank write bursts +system.physmem.perBankWrBursts::0 9468 # Per bank write bursts +system.physmem.perBankWrBursts::1 9241 # Per bank write bursts +system.physmem.perBankWrBursts::2 10223 # Per bank write bursts +system.physmem.perBankWrBursts::3 9791 # Per bank write bursts +system.physmem.perBankWrBursts::4 9126 # Per bank write bursts +system.physmem.perBankWrBursts::5 9458 # Per bank write bursts +system.physmem.perBankWrBursts::6 9597 # Per bank write bursts +system.physmem.perBankWrBursts::7 9810 # Per bank write bursts +system.physmem.perBankWrBursts::8 9882 # Per bank write bursts +system.physmem.perBankWrBursts::9 10274 # Per bank write bursts +system.physmem.perBankWrBursts::10 9701 # Per bank write bursts +system.physmem.perBankWrBursts::11 9802 # Per bank write bursts +system.physmem.perBankWrBursts::12 9921 # Per bank write bursts +system.physmem.perBankWrBursts::13 9488 # Per bank write bursts +system.physmem.perBankWrBursts::14 9342 # Per bank write bursts +system.physmem.perBankWrBursts::15 9089 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2904914374000 # Total gap between requests +system.physmem.totGap 2904913375000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158967 # Read request sizes (log2) +system.physmem.readPktSize::6 159086 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 155231 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 244 # What read queue length does an incoming req see +system.physmem.writePktSize::6 155290 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 243 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -164,152 +164,150 @@ system.physmem.rdQLenPdf::31 0 # Wh system.physmem.wrQLenPdf::0 200 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 193 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 183 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 9964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 10874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 340.349730 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 196.021429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 354.920810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21349 35.19% 35.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14624 24.11% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5778 9.52% 68.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3154 5.20% 74.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2318 3.82% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1542 2.54% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1044 1.72% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1115 1.84% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9740 16.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60664 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6204 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.148614 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 546.636063 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6203 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60740 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 340.100889 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 196.092266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 354.277091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21340 35.13% 35.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14718 24.23% 59.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5632 9.27% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3268 5.38% 74.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2341 3.85% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1599 2.63% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1029 1.69% 82.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1125 1.85% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9688 15.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60740 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6228 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.064066 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 545.583235 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6227 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6204 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6204 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.850097 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.346548 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.047003 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 14 0.23% 0.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 12 0.19% 0.42% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6228 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6228 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.761240 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.356568 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.463142 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 15 0.24% 0.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 11 0.18% 0.42% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::8-11 8 0.13% 0.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 18 0.29% 0.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4939 79.61% 80.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 68 1.10% 81.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 50 0.81% 82.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 255 4.11% 86.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 123 1.98% 88.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 43 0.69% 89.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.74% 89.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 38 0.61% 90.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 127 2.05% 92.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.18% 92.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 16 0.26% 92.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.13% 93.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 34 0.55% 93.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 17 0.27% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 13 0.21% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 28 0.45% 94.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 70 1.13% 95.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.18% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.11% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 13 0.21% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 92 1.48% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 97.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 13 0.21% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.08% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 13 0.21% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.06% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 6 0.10% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.05% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 29 0.47% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 12 0.19% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 7 0.11% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.10% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 6 0.10% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 4 0.06% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.06% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 6 0.10% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6204 # Writes before turning the bus around for reads -system.physmem.totQLat 1487388750 # Total ticks spent queuing -system.physmem.totMemAccLat 4645638750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 842200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8830.38 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::12-15 13 0.21% 0.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4938 79.29% 80.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 76 1.22% 81.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 62 1.00% 82.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 242 3.89% 86.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 139 2.23% 88.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 50 0.80% 89.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 31 0.50% 89.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 38 0.61% 90.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 131 2.10% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 23 0.37% 92.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 11 0.18% 92.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 18 0.29% 93.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 33 0.53% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 12 0.19% 93.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 9 0.14% 94.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 29 0.47% 94.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 74 1.19% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 10 0.16% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 6 0.10% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 12 0.19% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 105 1.69% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 8 0.13% 98.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 5 0.08% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 14 0.22% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 5 0.08% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 10 0.16% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 36 0.58% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 6 0.10% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 5 0.08% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.08% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.05% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.08% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 2 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6228 # Writes before turning the bus around for reads +system.physmem.totQLat 1469432250 # Total ticks spent queuing +system.physmem.totMemAccLat 4630026000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 842825000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8717.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27580.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27467.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s @@ -319,36 +317,41 @@ system.physmem.busUtil 0.06 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.55 # Average write queue length when enqueuing -system.physmem.readRowHits 138839 # Number of row buffer hits during reads -system.physmem.writeRowHits 123106 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.21 # Average write queue length when enqueuing +system.physmem.readRowHits 138952 # Number of row buffer hits during reads +system.physmem.writeRowHits 123085 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.85 # Row buffer hit rate for writes -system.physmem.avgGap 8852370.93 # Average gap between requests -system.physmem.pageHitRate 81.19 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2756204372250 # Time in different power states -system.physmem.memoryStateTime::REF 97001320000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 51708967750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 232462440 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 226157400 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 126839625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 123399375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 696064200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 617760000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 498059280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 500962320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 189734581920 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 189734581920 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86971409685 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 86091461640 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1666655279250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1667427163500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1944914696400 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1944721486155 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.526666 # Core power per rank (mW) -system.physmem.averagePower::1 669.460155 # Core power per rank (mW) +system.physmem.writeRowHitRate 79.81 # Row buffer hit rate for writes +system.physmem.avgGap 8847568.67 # Average gap between requests +system.physmem.pageHitRate 81.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 232530480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 126876750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 695315400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 497106720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189734581920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86967425385 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666658766000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1944912602655 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.525949 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772474399000 # Time in different power states +system.physmem_0.memoryStateTime::REF 97001320000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35434263500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 226663920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123675750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 619483800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 502193520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189734581920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 86205812760 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1667326855500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1944739267170 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.466276 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2773597933750 # Time in different power states +system.physmem_1.memoryStateTime::REF 97001320000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34314407250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -368,6 +371,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -389,27 +400,68 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 7245 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7245 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2256 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4989 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7245 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7245 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7245 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6163 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11073.588350 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8976.658748 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6262.578720 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-2047 6 0.10% 0.10% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::2048-4095 1618 26.25% 26.35% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::4096-6143 2 0.03% 26.38% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::10240-12287 3154 51.18% 77.56% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::12288-14335 39 0.63% 78.19% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::14336-16383 18 0.29% 78.48% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::20480-22527 1281 20.79% 99.27% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::22528-24575 45 0.73% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6163 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 809116500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 809116500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 809116500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3931 63.78% 63.78% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 2232 36.22% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6163 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7245 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7245 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6163 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6163 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 13408 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12308215 # DTB read hits -system.cpu0.dtb.read_misses 6223 # DTB read misses -system.cpu0.dtb.write_hits 9796614 # DTB write hits -system.cpu0.dtb.write_misses 1025 # DTB write misses +system.cpu0.dtb.read_hits 12308192 # DTB read hits +system.cpu0.dtb.read_misses 6208 # DTB read misses +system.cpu0.dtb.write_hits 9797532 # DTB write hits +system.cpu0.dtb.write_misses 1037 # DTB write misses system.cpu0.dtb.flush_tlb 2937 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4667 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4666 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 862 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 859 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12314438 # DTB read accesses -system.cpu0.dtb.write_accesses 9797639 # DTB write accesses +system.cpu0.dtb.read_accesses 12314400 # DTB read accesses +system.cpu0.dtb.write_accesses 9798569 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 22104829 # DTB hits -system.cpu0.dtb.misses 7248 # DTB misses -system.cpu0.dtb.accesses 22112077 # DTB accesses +system.cpu0.dtb.hits 22105724 # DTB hits +system.cpu0.dtb.misses 7245 # DTB misses +system.cpu0.dtb.accesses 22112969 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -431,7 +483,36 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 58194599 # ITB inst hits +system.cpu0.itb.walker.walks 3600 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3600 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 840 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2760 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3600 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3600 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3600 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2772 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 11755.230880 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9457.284814 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6774.641568 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 701 25.29% 25.29% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1365 49.24% 74.53% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 705 25.43% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::73728-81919 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2772 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1932 69.70% 69.70% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 840 30.30% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2772 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3600 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3600 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2772 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2772 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6372 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 58198432 # ITB inst hits system.cpu0.itb.inst_misses 3600 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -448,38 +529,38 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 58198199 # ITB inst accesses -system.cpu0.itb.hits 58194599 # DTB hits +system.cpu0.itb.inst_accesses 58202032 # ITB inst accesses +system.cpu0.itb.hits 58198432 # DTB hits system.cpu0.itb.misses 3600 # DTB misses -system.cpu0.itb.accesses 58198199 # DTB accesses -system.cpu0.numCycles 2905784484 # number of cpu cycles simulated +system.cpu0.itb.accesses 58202032 # DTB accesses +system.cpu0.numCycles 2905779233 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 56652370 # Number of instructions committed -system.cpu0.committedOps 68154355 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60226518 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5995 # Number of float alu accesses -system.cpu0.num_func_calls 4919534 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7679282 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60226518 # number of integer instructions -system.cpu0.num_fp_insts 5995 # number of float instructions -system.cpu0.num_int_register_reads 109459523 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41576844 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4468 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1530 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 246082665 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26221599 # number of times the CC registers were written -system.cpu0.num_mem_refs 22745945 # number of memory refs -system.cpu0.num_load_insts 12471278 # Number of load instructions -system.cpu0.num_store_insts 10274667 # Number of store instructions -system.cpu0.num_idle_cycles 2686990403.807933 # Number of idle cycles -system.cpu0.num_busy_cycles 218794080.192067 # Number of busy cycles -system.cpu0.not_idle_fraction 0.075296 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.924704 # Percentage of idle cycles -system.cpu0.Branches 13013332 # Number of branches fetched +system.cpu0.committedInsts 56657023 # Number of instructions committed +system.cpu0.committedOps 68159505 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 60230099 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 6043 # Number of float alu accesses +system.cpu0.num_func_calls 4917301 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7681441 # number of instructions that are conditional controls +system.cpu0.num_int_insts 60230099 # number of integer instructions +system.cpu0.num_fp_insts 6043 # number of float instructions +system.cpu0.num_int_register_reads 109460291 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41577079 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4484 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1562 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 246097869 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 26230649 # number of times the CC registers were written +system.cpu0.num_mem_refs 22747427 # number of memory refs +system.cpu0.num_load_insts 12471045 # Number of load instructions +system.cpu0.num_store_insts 10276382 # Number of store instructions +system.cpu0.num_idle_cycles 2686979283.194706 # Number of idle cycles +system.cpu0.num_busy_cycles 218799949.805294 # Number of busy cycles +system.cpu0.not_idle_fraction 0.075298 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.924702 # Percentage of idle cycles +system.cpu0.Branches 13013493 # Number of branches fetched system.cpu0.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46892920 67.27% 67.28% # Class of executed instruction -system.cpu0.op_class::IntMult 58660 0.08% 67.36% # Class of executed instruction +system.cpu0.op_class::IntAlu 46896636 67.27% 67.28% # Class of executed instruction +system.cpu0.op_class::IntMult 58754 0.08% 67.36% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.36% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.36% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 67.36% # Class of executed instruction @@ -507,23 +588,23 @@ system.cpu0.op_class::SimdFloatMisc 4258 0.01% 67.37% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.37% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.37% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.37% # Class of executed instruction -system.cpu0.op_class::MemRead 12471278 17.89% 85.26% # Class of executed instruction -system.cpu0.op_class::MemWrite 10274667 14.74% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 12471045 17.89% 85.26% # Class of executed instruction +system.cpu0.op_class::MemWrite 10276382 14.74% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 69703986 # Class of executed instruction +system.cpu0.op_class::total 69709278 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3038 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 822947 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.850765 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43250055 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 823459 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.522415 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 822797 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.850764 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43249693 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 823309 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.531544 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.083666 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.767099 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625163 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374545 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.252560 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.598204 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625493 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374215 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999709 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id @@ -531,128 +612,128 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::1 368 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177185510 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177185510 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11600521 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11519661 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23120182 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9401520 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9429674 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18831194 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 198556 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 193555 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392111 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 227604 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 215818 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443422 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 235826 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 224574 # number of StoreCondReq hits +system.cpu0.dcache.tags.tag_accesses 177183348 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177183348 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11600363 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11519690 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23120053 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9402507 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9428435 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18830942 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 198621 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 193510 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392131 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 227529 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 215892 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443421 # 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number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22768 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 347411 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 354044 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 701455 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 404068 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 416359 # number of overall misses -system.cpu0.dcache.overall_misses::total 820427 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2923278500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3014210500 # 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number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 9080124936 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 17693502697 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8613377761 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 9080124936 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 17693502697 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11799929 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 11722711 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23522640 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9550382 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9579302 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19129684 # 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number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460402 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 21349452 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21303379 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42652831 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 21604665 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21559249 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43163914 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016908 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017333 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.017120 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015487 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015745 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 21350311 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21302013 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42652324 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 21605662 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21557749 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43163411 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016912 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017319 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.017115 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015484 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015749 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.221999 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.243542 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232784 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046613 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.051170 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048836 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.222165 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.243321 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232751 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046775 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.051003 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048839 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000004 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000004 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016273 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016619 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016446 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018703 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019312 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.019007 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14651.776540 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14834.078102 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14743.759808 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38468.575527 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40381.579838 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39434.538871 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12145.488857 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12484.405877 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12318.750824 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016613 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016443 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018707 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019302 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14645.339136 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14803.006832 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14724.849536 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38482.948511 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40265.954026 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39383.379963 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12196.417376 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12466.107903 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12333.856729 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 75500 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 75500 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 75500 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24790.665837 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25719.208451 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25259.327321 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21314.605485 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21869.904186 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21596.414362 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24790.907697 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25658.188286 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25228.534250 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21311.221639 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21821.243544 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21569.945442 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 38 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -661,113 +742,113 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 2 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 686899 # number of writebacks -system.cpu0.dcache.writebacks::total 686899 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 272 # number of ReadReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 686778 # number of writebacks +system.cpu0.dcache.writebacks::total 686778 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 344 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 616 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7030 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7175 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 620 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7049 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7156 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14205 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 272 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 276 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu1.data 344 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 616 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 272 # number of overall MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 620 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 276 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu1.data 344 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 616 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 199245 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 202851 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 402096 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 147894 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 150849 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 298743 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 55774 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 61059 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 116833 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4098 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4464 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8562 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.overall_mshr_hits::total 620 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 199290 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 202677 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 401967 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 147875 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 150867 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 298742 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 55842 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 60970 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 116812 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4116 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4447 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8563 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 1 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 347139 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 353700 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 700839 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 402913 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 414759 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 817672 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2517898250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2600172750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5118071000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5366137441 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5759365015 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11125502456 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 677278250 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 762448500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1439726750 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48257750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52710750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100968500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 347165 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 353544 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 700709 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 403007 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 414514 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 817521 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2517038250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2591733500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5108771750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5367510939 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5742623268 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11110134207 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 678934750 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 762190250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1441125000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48430250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52495750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100926000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 73500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 73500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 147000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884035691 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8359537765 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16243573456 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8561313941 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9121986265 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 17683300206 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2688812000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3102617000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791429000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2186315500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2243484000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429799500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4875127500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5346101000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221228500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016885 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017304 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017094 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015745 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884549189 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8334356768 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16218905957 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8563483939 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9096547018 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 17660030957 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2685824500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3105604250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791428750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2183466000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2246337500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429803500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4869290500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5351941750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221232250 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016889 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017289 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017089 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015484 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015749 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.218539 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.238633 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228599 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017166 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019626 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018366 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.218687 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.238410 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228556 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017244 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019548 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018368 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016260 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016603 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016431 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018649 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019238 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018943 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12637.196667 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12818.141148 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12728.480263 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36283.672367 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38179.669835 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37241.048179 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12143.261197 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12487.078072 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12322.946000 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11775.927282 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11807.963710 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11792.630227 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016597 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016428 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018653 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019228 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12630.027849 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12787.506723 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12709.430749 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36297.622580 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38064.144366 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37189.729623 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12158.138140 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12501.070198 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12337.131459 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11766.338678 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11804.756015 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11786.289852 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 73500 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73500 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 73500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22711.466274 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23634.542734 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23177.325257 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21248.542343 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21993.461902 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21626.398123 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22711.244477 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23573.746883 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23146.421634 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21248.970710 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21945.089956 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21601.929439 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -778,16 +859,16 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1699785 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.774941 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113901535 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1700297 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 66.989200 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1699876 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.774945 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113899876 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1700388 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 66.984639 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 25359588250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 418.326028 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 92.448913 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.817043 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.180564 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 419.439814 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 91.335131 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.819218 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.178389 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.997607 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id @@ -795,62 +876,62 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117302141 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117302141 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 57346605 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 56554930 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113901535 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 57346605 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 56554930 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113901535 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 57346605 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 56554930 # number of overall hits -system.cpu0.icache.overall_hits::total 113901535 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 847994 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 852309 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1700303 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 847994 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 852309 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1700303 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 847994 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 852309 # number of overall misses -system.cpu0.icache.overall_misses::total 1700303 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11562218249 # 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number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 58194599 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 57407239 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115601838 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 58194599 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 57407239 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115601838 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014572 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014847 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014708 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014572 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014847 # 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average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13768.901596 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13702.014876 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 117300664 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117300664 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 57350245 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 56549631 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113899876 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 57350245 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 56549631 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113899876 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 57350245 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 56549631 # 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number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 57401838 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115600270 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 58198432 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 57401838 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115600270 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014574 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014846 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014709 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014574 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014846 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014709 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014574 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014846 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014709 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13637.591120 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13777.620342 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13707.771257 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13637.591120 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13777.620342 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13707.771257 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13637.591120 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13777.620342 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13707.771257 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -859,51 +940,59 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 847994 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 852309 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1700303 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 847994 # 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number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19901259002 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 597905000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 597905000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014572 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014847 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014572 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014847 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014708 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014572 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014847 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014708 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11631.383891 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11764.580979 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11698.151448 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11631.383891 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11764.580979 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11698.151448 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11631.383891 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11764.580979 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11698.151448 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014574 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014846 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014709 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014574 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014846 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014709 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014574 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014846 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014709 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11634.175602 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11773.316226 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11703.910389 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11634.175602 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11773.316226 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11703.910389 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11634.175602 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11773.316226 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11703.910389 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -925,27 +1014,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 6287 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6287 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1877 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4409 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 6286 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6286 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6286 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5205 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10664.029395 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8432.528945 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7016.441417 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 4168 80.08% 80.08% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 1031 19.81% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-81919 3 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-98303 2 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-180223 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5205 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2238481496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.553158 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.497166 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000247500 44.68% 44.68% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1238233996 55.32% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2238481496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3350 64.37% 64.37% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1854 35.63% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5204 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5204 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5204 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11491 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12222550 # DTB read hits -system.cpu1.dtb.read_misses 5478 # DTB read misses -system.cpu1.dtb.write_hits 9817405 # DTB write hits -system.cpu1.dtb.write_misses 801 # DTB write misses +system.cpu1.dtb.read_hits 12222323 # DTB read hits +system.cpu1.dtb.read_misses 5479 # DTB read misses +system.cpu1.dtb.write_hits 9816234 # DTB write hits +system.cpu1.dtb.write_misses 808 # DTB write misses system.cpu1.dtb.flush_tlb 2935 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4101 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4100 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 936 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 935 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12228028 # DTB read accesses -system.cpu1.dtb.write_accesses 9818206 # DTB write accesses +system.cpu1.dtb.read_accesses 12227802 # DTB read accesses +system.cpu1.dtb.write_accesses 9817042 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22039955 # DTB hits -system.cpu1.dtb.misses 6279 # DTB misses -system.cpu1.dtb.accesses 22046234 # DTB accesses +system.cpu1.dtb.hits 22038557 # DTB hits +system.cpu1.dtb.misses 6287 # DTB misses +system.cpu1.dtb.accesses 22044844 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -967,8 +1098,40 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 57407239 # ITB inst hits -system.cpu1.itb.inst_misses 3155 # ITB inst misses +system.cpu1.itb.walker.walks 3158 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3158 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 699 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2459 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3158 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3158 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3158 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2331 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10972.758473 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8658.635701 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6654.132285 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::2048-4095 701 30.07% 30.07% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 5 0.21% 30.29% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 1063 45.60% 75.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 47 2.02% 77.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 1 0.04% 77.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-22527 442 18.96% 96.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 72 3.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2331 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000205500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000205500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000205500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1632 70.01% 70.01% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 699 29.99% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2331 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3158 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3158 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2331 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2331 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5489 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 57401838 # ITB inst hits +system.cpu1.itb.inst_misses 3158 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -977,45 +1140,45 @@ system.cpu1.itb.flush_tlb 2935 # Nu system.cpu1.itb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2356 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2358 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 57410394 # ITB inst accesses -system.cpu1.itb.hits 57407239 # DTB hits -system.cpu1.itb.misses 3155 # DTB misses -system.cpu1.itb.accesses 57410394 # DTB accesses -system.cpu1.numCycles 2904045023 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 57404996 # ITB inst accesses +system.cpu1.itb.hits 57401838 # DTB hits +system.cpu1.itb.misses 3158 # DTB misses +system.cpu1.itb.accesses 57404996 # DTB accesses +system.cpu1.numCycles 2904048276 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 55850596 # Number of instructions committed -system.cpu1.committedOps 67489552 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 59717976 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5231 # Number of float alu accesses -system.cpu1.num_func_calls 4978644 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7556287 # number of instructions that are conditional controls -system.cpu1.num_int_insts 59717976 # number of integer instructions -system.cpu1.num_fp_insts 5231 # number of float instructions -system.cpu1.num_int_register_reads 108697708 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41105654 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4046 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1186 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 243864682 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 25692319 # number of times the CC registers were written -system.cpu1.num_mem_refs 22680019 # number of memory refs -system.cpu1.num_load_insts 12382292 # Number of load instructions -system.cpu1.num_store_insts 10297727 # Number of store instructions -system.cpu1.num_idle_cycles 2693854199.172201 # Number of idle cycles -system.cpu1.num_busy_cycles 210190823.827799 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072379 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927621 # Percentage of idle cycles -system.cpu1.Branches 12914403 # Number of branches fetched +system.cpu1.committedInsts 55844358 # Number of instructions committed +system.cpu1.committedOps 67482566 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 59712832 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5183 # Number of float alu accesses +system.cpu1.num_func_calls 4980648 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7553958 # number of instructions that are conditional controls +system.cpu1.num_int_insts 59712832 # number of integer instructions +system.cpu1.num_fp_insts 5183 # number of float instructions +system.cpu1.num_int_register_reads 108693830 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41104260 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4030 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1154 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 243842957 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 25682716 # number of times the CC registers were written +system.cpu1.num_mem_refs 22677996 # number of memory refs +system.cpu1.num_load_insts 12382220 # Number of load instructions +system.cpu1.num_store_insts 10295776 # Number of store instructions +system.cpu1.num_idle_cycles 2693878470.584054 # Number of idle cycles +system.cpu1.num_busy_cycles 210169805.415946 # Number of busy cycles +system.cpu1.not_idle_fraction 0.072371 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.927629 # Percentage of idle cycles +system.cpu1.Branches 12913817 # Number of branches fetched system.cpu1.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 46321486 67.07% 67.07% # Class of executed instruction -system.cpu1.op_class::IntMult 56040 0.08% 67.15% # Class of executed instruction +system.cpu1.op_class::IntAlu 46316521 67.07% 67.07% # Class of executed instruction +system.cpu1.op_class::IntMult 55928 0.08% 67.15% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.15% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.15% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.15% # Class of executed instruction @@ -1043,11 +1206,11 @@ system.cpu1.op_class::SimdFloatMisc 4215 0.01% 67.16% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 67.16% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.16% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.16% # Class of executed instruction -system.cpu1.op_class::MemRead 12382292 17.93% 85.09% # Class of executed instruction -system.cpu1.op_class::MemWrite 10297727 14.91% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12382220 17.93% 85.09% # Class of executed instruction +system.cpu1.op_class::MemWrite 10295776 14.91% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69061894 # Class of executed instruction +system.cpu1.op_class::total 69054794 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iobus.trans_dist::ReadReq 30195 # Transaction distribution @@ -1145,21 +1308,21 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347067538 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347068533 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804503 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.084296 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084285 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309429812000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084296 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 309430209000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084285 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.067768 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.067768 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1177,8 +1340,8 @@ system.iocache.overall_misses::realview.ide 234 # system.iocache.overall_misses::total 234 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9591408658 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9591408658 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9589202651 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9589202651 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles @@ -1201,17 +1364,17 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264780.495197 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264780.495197 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264719.596152 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264719.596152 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55572 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 55434 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7176 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7152 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.744147 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.750839 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1227,8 +1390,8 @@ system.iocache.overall_mshr_misses::realview.ide 234 system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7707754664 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7707754664 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7705544661 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7705544661 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57217.681950 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68392.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60635.205879 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56507.069783 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57254.032801 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60112.752384 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57307.407335 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59800.427350 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56812.065606 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57370.855040 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60355.215939 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57217.681950 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68392.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60635.205879 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56507.069783 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57254.032801 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1655,57 +1818,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70575 # Transaction distribution -system.membus.trans_dist::ReadResp 70575 # Transaction distribution +system.membus.trans_dist::ReadReq 70570 # Transaction distribution +system.membus.trans_dist::ReadResp 70570 # Transaction distribution system.membus.trans_dist::WriteReq 27613 # Transaction distribution system.membus.trans_dist::WriteResp 27613 # Transaction distribution -system.membus.trans_dist::Writeback 119007 # Transaction distribution +system.membus.trans_dist::Writeback 119066 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4495 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4497 # Transaction distribution -system.membus.trans_dist::ReadExReq 129060 # Transaction distribution -system.membus.trans_dist::ReadExResp 129060 # Transaction distribution +system.membus.trans_dist::ReadExReq 129184 # Transaction distribution +system.membus.trans_dist::ReadExResp 129184 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 437896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 545560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438193 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 545857 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 654447 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 654744 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15529084 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15692509 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15540476 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15703901 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20327965 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20339357 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 319191 # Request fanout histogram +system.membus.snoop_fanout::samples 319369 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 319191 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 319369 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 319191 # Request fanout histogram -system.membus.reqLayer0.occupancy 87172500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 319369 # Request fanout histogram +system.membus.reqLayer0.occupancy 87174000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1735000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1737000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1662315000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1663053000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1640286255 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1641418005 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38333497 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1738,54 +1901,54 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2303097 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2303082 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2303048 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2303033 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 686899 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 686778 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2744 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2746 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295999 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295999 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3418625 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457116 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18180 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34622 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5928543 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108853880 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96862117 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24836 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205787617 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 53694 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3284793 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.011099 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104766 # Request fanout histogram +system.toL2Bus.trans_dist::ReadExReq 295998 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295998 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3418807 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2456695 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18188 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34627 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5928317 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108859704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96844773 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24844 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46792 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205776113 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 53699 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3284622 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.011100 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104768 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3248335 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3248164 98.89% 98.89% # Request fanout histogram system.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3284793 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4419462750 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3284622 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4418893499 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 7665779999 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 7666187498 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3782690745 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3782041495 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11971000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11977000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22951201 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22953702 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |