diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini | 121 | ||||
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt | 2283 |
2 files changed, 1257 insertions, 1147 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index 78712e3a3..927b487de 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,22 +12,23 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts @@ -112,6 +121,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -134,18 +144,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -156,6 +169,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -178,14 +192,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -204,18 +221,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -227,6 +247,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null @@ -248,17 +269,20 @@ workload= [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -277,30 +301,36 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -313,6 +343,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -335,6 +366,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -344,6 +376,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -366,6 +399,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -373,6 +407,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -384,6 +419,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -410,6 +446,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -421,19 +458,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -443,6 +484,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -452,6 +494,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -480,6 +523,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -489,8 +533,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -502,6 +578,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -517,6 +594,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -531,6 +610,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -540,6 +620,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -561,8 +642,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -571,6 +654,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -581,6 +665,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -591,6 +676,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -601,6 +687,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -615,6 +702,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -628,6 +716,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -645,6 +734,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -657,6 +747,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -668,6 +759,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -678,6 +770,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -690,6 +783,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -703,6 +797,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -713,6 +808,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -723,6 +819,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -733,6 +830,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -745,6 +843,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -759,6 +858,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -771,6 +871,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -785,6 +886,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -795,6 +897,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -805,6 +908,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -815,6 +919,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -823,6 +928,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -831,6 +937,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -840,11 +947,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 87a0dc109..98143dc12 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,145 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.631415 # Number of seconds simulated -sim_ticks 2631415171500 # Number of ticks simulated -final_tick 2631415171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.629717 # Number of seconds simulated +sim_ticks 2629717216500 # Number of ticks simulated +final_tick 2629717216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 471038 # Simulator instruction rate (inst/s) -host_op_rate 599389 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20585916294 # Simulator tick rate (ticks/s) -host_mem_usage 424736 # Number of bytes of host memory used -host_seconds 127.83 # Real time elapsed on the host -sim_insts 60210883 # Number of instructions simulated -sim_ops 76617506 # Number of ops (including micro ops) simulated +host_inst_rate 340896 # Simulator instruction rate (inst/s) +host_op_rate 433786 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14888327014 # Simulator tick rate (ticks/s) +host_mem_usage 445372 # Number of bytes of host memory used +host_seconds 176.63 # Real time elapsed on the host +sim_insts 60212334 # Number of instructions simulated +sim_ops 76619433 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 278752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4724944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 298016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4661584 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4336188 # Number of bytes read from this memory -system.physmem.bytes_read::total 134022064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 278752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704484 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3690496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1530592 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1485560 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706648 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 406404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4399060 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 298016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 406404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704420 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3689984 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1527272 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1489008 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706264 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73861 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10859 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 72871 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 67782 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690904 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 382648 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 371390 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811702 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47220316 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6366 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 68770 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690901 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57656 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 381818 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 372252 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811726 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47250805 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 105932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1795590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 113326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1772656 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 161788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1647854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50931554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 105932 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 161788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1402476 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 581661 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 564548 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2548685 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1402476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47220316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 154543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1672826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50964230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 113326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 154543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267869 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1403187 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 580774 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 566224 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550184 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1403187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47250805 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 105932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2377252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 113326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2353430 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 161788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2212402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53480239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690904 # Number of read requests accepted -system.physmem.writeReqs 811702 # Number of write requests accepted -system.physmem.readBursts 15690904 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811702 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004216000 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 154543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2239050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53514414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690901 # Number of read requests accepted +system.physmem.writeReqs 811726 # Number of write requests accepted +system.physmem.readBursts 15690901 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811726 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004215808 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6838848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134022064 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6706648 # Total written bytes from the system interface side +system.physmem.bytesWritten 6837952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134021512 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706264 # Total written bytes from the system interface side system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 704845 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write +system.physmem.mergedWrBursts 704883 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4518 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980392 # Per bank write bursts system.physmem.perBankRdBursts::1 980205 # Per bank write bursts system.physmem.perBankRdBursts::2 980222 # Per bank write bursts -system.physmem.perBankRdBursts::3 980428 # Per bank write bursts +system.physmem.perBankRdBursts::3 980431 # Per bank write bursts system.physmem.perBankRdBursts::4 986950 # Per bank write bursts -system.physmem.perBankRdBursts::5 980709 # Per bank write bursts -system.physmem.perBankRdBursts::6 980611 # Per bank write bursts -system.physmem.perBankRdBursts::7 980420 # Per bank write bursts +system.physmem.perBankRdBursts::5 980708 # Per bank write bursts +system.physmem.perBankRdBursts::6 980610 # Per bank write bursts +system.physmem.perBankRdBursts::7 980424 # Per bank write bursts system.physmem.perBankRdBursts::8 980615 # Per bank write bursts system.physmem.perBankRdBursts::9 980431 # Per bank write bursts system.physmem.perBankRdBursts::10 979815 # Per bank write bursts -system.physmem.perBankRdBursts::11 979555 # Per bank write bursts -system.physmem.perBankRdBursts::12 980153 # Per bank write bursts -system.physmem.perBankRdBursts::13 980095 # Per bank write bursts -system.physmem.perBankRdBursts::14 980165 # Per bank write bursts +system.physmem.perBankRdBursts::11 979558 # Per bank write bursts +system.physmem.perBankRdBursts::12 980154 # Per bank write bursts +system.physmem.perBankRdBursts::13 980093 # Per bank write bursts +system.physmem.perBankRdBursts::14 980155 # Per bank write bursts system.physmem.perBankRdBursts::15 980109 # Per bank write bursts -system.physmem.perBankWrBursts::0 6734 # Per bank write bursts -system.physmem.perBankWrBursts::1 6600 # Per bank write bursts -system.physmem.perBankWrBursts::2 6608 # Per bank write bursts -system.physmem.perBankWrBursts::3 6671 # Per bank write bursts -system.physmem.perBankWrBursts::4 6747 # Per bank write bursts -system.physmem.perBankWrBursts::5 7057 # Per bank write bursts -system.physmem.perBankWrBursts::6 7034 # Per bank write bursts -system.physmem.perBankWrBursts::7 6884 # Per bank write bursts -system.physmem.perBankWrBursts::8 7000 # Per bank write bursts -system.physmem.perBankWrBursts::9 6825 # Per bank write bursts +system.physmem.perBankWrBursts::0 6731 # Per bank write bursts +system.physmem.perBankWrBursts::1 6599 # Per bank write bursts +system.physmem.perBankWrBursts::2 6610 # Per bank write bursts +system.physmem.perBankWrBursts::3 6672 # Per bank write bursts +system.physmem.perBankWrBursts::4 6746 # Per bank write bursts +system.physmem.perBankWrBursts::5 7052 # Per bank write bursts +system.physmem.perBankWrBursts::6 7033 # Per bank write bursts +system.physmem.perBankWrBursts::7 6881 # Per bank write bursts +system.physmem.perBankWrBursts::8 7002 # Per bank write bursts +system.physmem.perBankWrBursts::9 6827 # Per bank write bursts system.physmem.perBankWrBursts::10 6323 # Per bank write bursts -system.physmem.perBankWrBursts::11 6129 # Per bank write bursts +system.physmem.perBankWrBursts::11 6122 # Per bank write bursts system.physmem.perBankWrBursts::12 6612 # Per bank write bursts -system.physmem.perBankWrBursts::13 6395 # Per bank write bursts -system.physmem.perBankWrBursts::14 6622 # Per bank write bursts +system.physmem.perBankWrBursts::13 6399 # Per bank write bursts +system.physmem.perBankWrBursts::14 6618 # Per bank write bursts system.physmem.perBankWrBursts::15 6616 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2631410752000 # Total gap between requests +system.physmem.totGap 2629712785000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6700 # Read request sizes (log2) +system.physmem.readPktSize::2 6706 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152172 # Read request sizes (log2) +system.physmem.readPktSize::6 152163 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754038 # Write request sizes (log2) +system.physmem.writePktSize::2 754070 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57664 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1280991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1124435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1124568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3790382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2700913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2699740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2717442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 51875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 37 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57656 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1290849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1134741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1135188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3791353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2690884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2690157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2706986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 51561 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 56279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20472 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -155,28 +167,28 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5010 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 4995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4689 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -187,301 +199,302 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11200.204894 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1031.239605 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16762.903946 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23441 25.97% 25.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14726 16.31% 42.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2829 3.13% 45.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2153 2.39% 47.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1359 1.51% 49.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1176 1.30% 50.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 955 1.06% 51.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1145 1.27% 52.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 612 0.68% 53.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 559 0.62% 54.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 621 0.69% 54.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 534 0.59% 55.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 322 0.36% 55.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 268 0.30% 56.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 218 0.24% 56.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 586 0.65% 57.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 164 0.18% 57.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 127 0.14% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 130 0.14% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 257 0.28% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 105 0.12% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2231 2.47% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 89 0.10% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 142 0.16% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 48 0.05% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 45 0.05% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 41 0.05% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 166 0.18% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 19 0.02% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 18 0.02% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 150 0.17% 61.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 341 0.38% 61.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 18 0.02% 61.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 19 0.02% 61.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 17 0.02% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 76 0.08% 61.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 15 0.02% 61.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 8 0.01% 61.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 16 0.02% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 76 0.08% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 11 0.01% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 6 0.01% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 7 0.01% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 22 0.02% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 8 0.01% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 3 0.00% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 6 0.01% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 382 0.42% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 8 0.01% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 6 0.01% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 146 0.16% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 2 0.00% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 137 0.15% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 6 0.01% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 197 0.22% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 7 0.01% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 7 0.01% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 32 0.04% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 137 0.15% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 6 0.01% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 2 0.00% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 6 0.01% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 337 0.37% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 1 0.00% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 1 0.00% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 2 0.00% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 130 0.14% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 2 0.00% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 1 0.00% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 71 0.08% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 129 0.14% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 3 0.00% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 75 0.08% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 261 0.29% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 1 0.00% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 1 0.00% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 62 0.07% 64.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 15 0.02% 64.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 204 0.23% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 122 0.14% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 133 0.15% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 389 0.43% 65.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 64 0.07% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 68 0.08% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 120 0.13% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 252 0.28% 65.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 133 0.15% 65.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 13 0.01% 66.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 68 0.08% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 520 0.58% 66.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 68 0.08% 66.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 11 0.01% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 136 0.15% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 250 0.28% 67.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 121 0.13% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 68 0.08% 67.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 65 0.07% 67.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 388 0.43% 67.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 132 0.15% 68.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 68.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 121 0.13% 68.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10823 2 0.00% 68.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 55 0.06% 68.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 259 0.29% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 71 0.08% 68.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 69 0.08% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 128 0.14% 68.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 328 0.36% 69.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 133 0.15% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 193 0.21% 69.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 136 0.15% 69.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 377 0.42% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 11 0.01% 70.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 64 0.07% 70.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 70 0.08% 70.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 322 0.36% 70.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 132 0.15% 70.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 68 0.08% 70.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 129 0.14% 70.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 391 0.43% 71.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 67 0.07% 71.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 129 0.14% 71.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 641 0.71% 72.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 136 0.15% 72.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 66 0.07% 72.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 2 0.00% 72.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 391 0.43% 73.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 128 0.14% 73.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 67 0.07% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 131 0.15% 73.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 320 0.35% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 67 0.07% 73.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 67 0.07% 73.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 13 0.01% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 1 0.00% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 376 0.42% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 137 0.15% 74.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 192 0.21% 74.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 131 0.15% 74.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 326 0.36% 75.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 124 0.14% 75.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 68 0.08% 75.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21056-21063 1 0.00% 75.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 71 0.08% 75.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 259 0.29% 75.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 56 0.06% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 120 0.13% 75.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 134 0.15% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 388 0.43% 76.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 64 0.07% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 67 0.07% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 121 0.13% 76.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 253 0.28% 77.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 133 0.15% 77.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 10 0.01% 77.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 70 0.08% 77.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 519 0.57% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 69 0.08% 77.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 10 0.01% 77.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 133 0.15% 78.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 251 0.28% 78.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 120 0.13% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 70 0.08% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 64 0.07% 78.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 387 0.43% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 134 0.15% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 119 0.13% 79.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 56 0.06% 79.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 259 0.29% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 71 0.08% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 68 0.08% 79.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 125 0.14% 80.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 325 0.36% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 133 0.15% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 192 0.21% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 136 0.15% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 377 0.42% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 11 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 65 0.07% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 69 0.08% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 321 0.36% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 130 0.14% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 67 0.07% 82.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 128 0.14% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 390 0.43% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 1 0.00% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 67 0.07% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 130 0.14% 82.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 640 0.71% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 132 0.15% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 70 0.08% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 1 0.00% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 389 0.43% 84.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 128 0.14% 84.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 67 0.07% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 130 0.14% 84.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 318 0.35% 84.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 68 0.08% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 64 0.07% 85.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 10 0.01% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 377 0.42% 85.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 136 0.15% 85.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 192 0.21% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 132 0.15% 86.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 324 0.36% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 125 0.14% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 68 0.08% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 71 0.08% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 259 0.29% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 56 0.06% 87.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 119 0.13% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 134 0.15% 87.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 387 0.43% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 64 0.07% 87.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 69 0.08% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 119 0.13% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 251 0.28% 88.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 133 0.15% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 9 0.01% 88.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 68 0.08% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 518 0.57% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 69 0.08% 89.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 10 0.01% 89.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 133 0.15% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 252 0.28% 89.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 120 0.13% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 67 0.07% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 64 0.07% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 388 0.43% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 134 0.15% 90.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 119 0.13% 90.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 56 0.06% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 260 0.29% 90.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 71 0.08% 91.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 69 0.08% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 124 0.14% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 325 0.36% 91.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 131 0.15% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 191 0.21% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 137 0.15% 92.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 375 0.42% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 11 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 66 0.07% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 66 0.07% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 319 0.35% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 133 0.15% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 90454 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11177.544033 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1030.436917 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16744.733089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23393 25.86% 25.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14737 16.29% 42.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2929 3.24% 45.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2185 2.42% 47.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1403 1.55% 49.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1153 1.27% 50.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 940 1.04% 51.67% # Bytes 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+system.physmem.bytesPerActivate::40448-40455 192 0.21% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 259 0.29% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 3 0.00% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 192 0.21% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 9 0.01% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 452 0.50% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 64 0.07% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 5 0.01% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 255 0.28% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.06% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::45568-45575 72 0.08% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 4 0.00% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 385 0.43% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 194 0.21% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 76 0.08% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 128 0.14% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 209 0.23% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 65 0.07% 93.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::47616-47623 67 0.07% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 129 0.14% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 390 0.43% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 1 0.00% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 67 0.07% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 131 0.15% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5359 5.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90271 # Bytes accessed per row activation -system.physmem.totQLat 377292466250 # Total ticks spent queuing -system.physmem.totMemAccLat 474547986250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454375000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18801145000 # Total ticks spent accessing banks -system.physmem.avgQLat 24045.34 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1198.22 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 73 0.08% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 459 0.51% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 3 0.00% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 69 0.08% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48448-48455 1 0.00% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 129 0.14% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 129 0.14% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5220 5.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90454 # Bytes accessed per row activation +system.physmem.totQLat 377144928750 # Total ticks spent queuing +system.physmem.totMemAccLat 474552728750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454360000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18953440000 # Total ticks spent accessing banks +system.physmem.avgQLat 24035.94 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1207.93 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30243.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30243.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage @@ -489,268 +502,256 @@ system.physmem.busUtilRead 2.98 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing -system.physmem.readRowHits 15616441 # Number of row buffer hits during reads -system.physmem.writeRowHits 91020 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.18 # Row buffer hit rate for writes -system.physmem.avgGap 159454.26 # Average gap between requests +system.physmem.readRowHits 15616330 # Number of row buffer hits during reads +system.physmem.writeRowHits 90931 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.11 # Row buffer hit rate for writes +system.physmem.avgGap 159351.16 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54391586 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743633 # Transaction distribution -system.membus.trans_dist::ReadResp 16743633 # Transaction distribution -system.membus.trans_dist::WriteReq 763392 # Transaction distribution -system.membus.trans_dist::WriteResp 763392 # Transaction distribution -system.membus.trans_dist::Writeback 57664 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution -system.membus.trans_dist::ReadExReq 131346 # Transaction distribution -system.membus.trans_dist::ReadExResp 131346 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.physmem.prechargeAllPercent 2.39 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 54426353 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743636 # Transaction distribution +system.membus.trans_dist::ReadResp 16743636 # Transaction distribution +system.membus.trans_dist::WriteReq 763424 # Transaction distribution +system.membus.trans_dist::WriteResp 763424 # Transaction distribution +system.membus.trans_dist::Writeback 57656 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4518 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4518 # Transaction distribution +system.membus.trans_dist::ReadExReq 131342 # Transaction distribution +system.membus.trans_dist::ReadExResp 131342 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892518 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279376 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892570 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279432 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343440 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35343496 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18870589 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471520 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18869661 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143126845 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143126845 # Total data (bytes) +system.membus.tot_pkt_size::total 143125917 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143125917 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1220589500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225680000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3747000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3756000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18118484000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171618500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4951896724 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4990533473 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35075499000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35075577250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 62057 # number of replacements -system.l2c.tags.tagsinuse 51615.015118 # Cycle average of tags in use -system.l2c.tags.total_refs 1699237 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127445 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.333101 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2576505750500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38217.986822 # Average occupied blocks per requestor +system.l2c.tags.replacements 62046 # number of replacements +system.l2c.tags.tagsinuse 51605.865819 # Cycle average of tags in use +system.l2c.tags.total_refs 1699437 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127429 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.336344 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2574782383500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38213.733489 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2603.292629 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3037.110347 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2749.245070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3097.480060 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4418.327235 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3338.297198 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583160 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 4271.539066 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3273.867246 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583095 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.039723 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046343 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.041950 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.047264 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.067418 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.050938 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787583 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9914 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3649 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 415311 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 183212 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10008 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3517 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 429187 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 187142 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241940 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596380 # number of Writeback hits -system.l2c.Writeback_hits::total 596380 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.065179 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.049955 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787443 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 9827 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3607 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 412393 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 183168 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10051 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3578 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 432141 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 187290 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1242055 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596450 # number of Writeback hits +system.l2c.Writeback_hits::total 596450 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56696 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57849 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114545 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9914 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3649 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 415311 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 239908 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10008 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3517 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 429187 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 244991 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356485 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9914 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3649 # number of overall hits -system.l2c.overall_hits::cpu0.inst 415311 # number of overall hits -system.l2c.overall_hits::cpu0.data 239908 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10008 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3517 # number of overall hits -system.l2c.overall_hits::cpu1.inst 429187 # number of overall hits -system.l2c.overall_hits::cpu1.data 244991 # number of overall hits -system.l2c.overall_hits::total 1356485 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 57240 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57291 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114531 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9827 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3607 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 412393 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 240408 # number 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+system.l2c.demand_mshr_miss_rate::cpu0.data 0.234426 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014479 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.221499 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101827 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010184 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.234426 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014479 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.221499 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101827 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61802.163093 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58312.750412 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61683.277185 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63889.532561 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60684.612984 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58328.476926 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63871.851321 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60487.476586 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58415.657469 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58335.455393 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 58377.311545 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58336.694106 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58312.496793 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58324.919986 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58652.733738 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58312.750412 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58579.590165 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58740.851846 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58689.738300 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58328.476926 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58702.597502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58617.684463 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58652.733738 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58312.750412 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58579.590165 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58740.851846 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58689.738300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58328.476926 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58702.597502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58617.684463 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -902,45 +903,45 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52751818 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471631 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471631 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596380 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2913 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2913 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247521 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247521 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725079 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753474 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20108 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50543 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549204 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54752376 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83781573 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79692 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138642313 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138642313 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 169620 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808134500 # Layer occupancy (ticks) +system.toL2Bus.throughput 52790683 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471881 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471881 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763424 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763424 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596450 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2909 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2909 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247508 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247508 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725145 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753790 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20211 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50526 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549672 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54754616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83791781 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28748 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138654661 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138654661 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 169908 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808598000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865505750 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865648250 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4420696776 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4421117527 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12940000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13024000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30620250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30647250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48128720 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715358 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715358 # Transaction distribution +system.iobus.throughput 48159799 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution system.iobus.trans_dist::WriteResp 8167 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -962,12 +963,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382990 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447050 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33447054 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -989,14 +990,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390397 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646645 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646645 # Total data (bytes) +system.iobus.tot_pkt_size::total 126646653 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646653 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1042,141 +1043,141 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374819000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42584048000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42583673750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7352406 # DTB read hits -system.cpu0.dtb.read_misses 6766 # DTB read misses -system.cpu0.dtb.write_hits 5599485 # DTB write hits -system.cpu0.dtb.write_misses 1847 # DTB write misses -system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7421376 # DTB read hits +system.cpu0.dtb.read_misses 6854 # DTB read misses +system.cpu0.dtb.write_hits 5628030 # DTB write hits +system.cpu0.dtb.write_misses 1815 # DTB write misses +system.cpu0.dtb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6337 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 6418 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 131 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 151 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7359172 # DTB read accesses -system.cpu0.dtb.write_accesses 5601332 # DTB write accesses +system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7428230 # DTB read accesses +system.cpu0.dtb.write_accesses 5629845 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12951891 # DTB hits -system.cpu0.dtb.misses 8613 # DTB misses -system.cpu0.dtb.accesses 12960504 # DTB accesses -system.cpu0.itb.inst_hits 30170189 # ITB inst hits -system.cpu0.itb.inst_misses 3579 # ITB inst misses +system.cpu0.dtb.hits 13049406 # DTB hits +system.cpu0.dtb.misses 8669 # DTB misses +system.cpu0.dtb.accesses 13058075 # DTB accesses +system.cpu0.itb.inst_hits 30610107 # ITB inst hits +system.cpu0.itb.inst_misses 3562 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2748 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30173768 # ITB inst accesses -system.cpu0.itb.hits 30170189 # DTB hits -system.cpu0.itb.misses 3579 # DTB misses -system.cpu0.itb.accesses 30173768 # DTB accesses -system.cpu0.numCycles 2629696361 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30613669 # ITB inst accesses +system.cpu0.itb.hits 30610107 # DTB hits +system.cpu0.itb.misses 3562 # DTB misses +system.cpu0.itb.accesses 30613669 # DTB accesses +system.cpu0.numCycles 2628235952 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29597158 # Number of instructions committed -system.cpu0.committedOps 37762240 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33970200 # Number of integer alu accesses +system.cpu0.committedInsts 29990580 # Number of instructions committed +system.cpu0.committedOps 38158663 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34282971 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4584 # Number of float alu accesses -system.cpu0.num_func_calls 1050225 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3920547 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33970200 # number of integer instructions +system.cpu0.num_func_calls 1059870 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3968282 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34282971 # number of integer instructions system.cpu0.num_fp_insts 4584 # number of float instructions -system.cpu0.num_int_register_reads 194623734 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36521551 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3225 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1362 # number of times the floating registers were written -system.cpu0.num_mem_refs 13522491 # number of memory refs -system.cpu0.num_load_insts 7673972 # Number of load instructions -system.cpu0.num_store_insts 5848519 # Number of store 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13862.229035 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27780.625274 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26962.721579 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 27371.161182 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27780.625274 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26962.721579 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 27371.161182 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1349,77 +1350,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596380 # number of writebacks -system.cpu0.dcache.writebacks::total 596380 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182326 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186686 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369012 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127483 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 122951 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250434 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6110 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5462 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11572 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 309809 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 309637 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619446 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 309809 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 309637 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619446 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2351238750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2390198500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741437250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5650406828 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5242308905 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10892715733 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69656750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67531500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137188250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8001645578 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7632507405 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15634152983 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8001645578 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7632507405 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15634152983 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91105263250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90961118500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182066381750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13264461491 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12970911500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235372991 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104369724741 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103932030000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208301754741 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027478 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026929 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027198 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025037 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023951 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049024 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044361 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046706 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12895.795169 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.308764 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12849.005588 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44322.826008 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42637.383226 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43495.354996 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11400.450082 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12363.877700 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11855.189250 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 596450 # number of writebacks +system.cpu0.dcache.writebacks::total 596450 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182495 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186610 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369105 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126878 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 123539 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250417 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6016 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5563 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11579 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 309373 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 310149 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619522 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 309373 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 310149 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619522 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2359626750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2381686500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741313250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5588242867 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5334624365 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10922867232 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69088500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68209750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137298250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7947869617 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7716310865 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15664180482 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7947869617 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7716310865 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15664180482 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91489795250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90582792250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182072587500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13259276491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12977158000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26236434491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104749071741 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103559950250 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208309021991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027230 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027204 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024775 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024203 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048296 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.045152 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046732 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026167 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026037 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026167 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026037 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12929.815885 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12762.909276 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12845.432194 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44044.222537 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43181.702661 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43618.712915 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11484.125665 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12261.324825 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11857.522239 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1432,68 +1433,68 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7647205 # DTB read hits -system.cpu1.dtb.read_misses 7298 # DTB read misses -system.cpu1.dtb.write_hits 5633094 # DTB write hits -system.cpu1.dtb.write_misses 1843 # DTB write misses -system.cpu1.dtb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7578699 # DTB read hits +system.cpu1.dtb.read_misses 7251 # DTB read misses +system.cpu1.dtb.write_hits 5604812 # DTB write hits +system.cpu1.dtb.write_misses 1846 # DTB write misses +system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6730 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6708 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7654503 # DTB read accesses -system.cpu1.dtb.write_accesses 5634937 # DTB write accesses +system.cpu1.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7585950 # DTB read accesses +system.cpu1.dtb.write_accesses 5606658 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13280299 # DTB hits -system.cpu1.dtb.misses 9141 # DTB misses -system.cpu1.dtb.accesses 13289440 # DTB accesses -system.cpu1.itb.inst_hits 31334771 # ITB inst hits -system.cpu1.itb.inst_misses 3728 # ITB inst misses +system.cpu1.dtb.hits 13183511 # DTB hits +system.cpu1.dtb.misses 9097 # DTB misses +system.cpu1.dtb.accesses 13192608 # DTB accesses +system.cpu1.itb.inst_hits 30896338 # ITB inst hits +system.cpu1.itb.inst_misses 3789 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2858 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2857 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31338499 # ITB inst accesses -system.cpu1.itb.hits 31334771 # DTB hits -system.cpu1.itb.misses 3728 # DTB misses -system.cpu1.itb.accesses 31338499 # DTB accesses -system.cpu1.numCycles 2633133982 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30900127 # ITB inst accesses +system.cpu1.itb.hits 30896338 # DTB hits +system.cpu1.itb.misses 3789 # DTB misses +system.cpu1.itb.accesses 30900127 # DTB accesses +system.cpu1.numCycles 2631198481 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30613725 # Number of instructions committed -system.cpu1.committedOps 38855266 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34913201 # Number of integer alu accesses +system.cpu1.committedInsts 30221754 # Number of instructions committed +system.cpu1.committedOps 38460770 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34602143 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5685 # Number of float alu accesses -system.cpu1.num_func_calls 1090107 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4028756 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34913201 # number of integer instructions +system.cpu1.num_func_calls 1080538 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3981203 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34602143 # number of integer instructions system.cpu1.num_fp_insts 5685 # number of float instructions -system.cpu1.num_int_register_reads 200222637 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37674133 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4268 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written -system.cpu1.num_mem_refs 13877284 # number of memory refs -system.cpu1.num_load_insts 7989860 # Number of load instructions -system.cpu1.num_store_insts 5887424 # Number of store instructions -system.cpu1.num_idle_cycles 2288817928.029144 # Number of idle cycles -system.cpu1.num_busy_cycles 344316053.970855 # Number of busy cycles -system.cpu1.not_idle_fraction 0.130763 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.869237 # Percentage of idle cycles +system.cpu1.num_int_register_reads 198301383 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37233535 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4147 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1540 # number of times the floating registers were written +system.cpu1.num_mem_refs 13778426 # number of memory refs +system.cpu1.num_load_insts 7920474 # Number of load instructions +system.cpu1.num_store_insts 5857952 # Number of store instructions +system.cpu1.num_idle_cycles 2292395060.642381 # Number of idle cycles +system.cpu1.num_busy_cycles 338803420.357619 # Number of busy cycles +system.cpu1.not_idle_fraction 0.128764 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.871236 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1510,10 +1511,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1557205456000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1557205456000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1557221573750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1557221573750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |