diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing')
5 files changed, 12665 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini new file mode 100644 index 000000000..c7f535fb7 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -0,0 +1,795 @@ +[root] +type=Root +children=system +full_system=true +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +atags_addr=256 +boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm +boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +clock=1000 +dtb_filename= +early_kernel_symbols=false +enable_context_switch_stats_dump=false +flags_addr=268435504 +gic_cpu_addr=520093952 +init_param=0 +kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +load_addr_mask=268435455 +machine_type=RealView_PBX +mem_mode=timing +mem_ranges=0:134217727 +memories=system.physmem system.realview.nvmem +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +readfile=tests/halt.sh +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.bridge] +type=Bridge +clock=1000 +delay=50000 +ranges=268435456:520093695 1073741824:1610612735 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img +read_only=true + +[system.cpu0] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb tracer +checker=Null +clock=500 +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +switched_out=false +system=system +tracer=system.cpu0.tracer +workload= +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +clock=500 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +size=32768 +system=system +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=ArmTableWalker +clock=500 +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[3] + +[system.cpu0.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +clock=500 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +size=32768 +system=system +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.interrupts] +type=ArmInterrupts + +[system.cpu0.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + +[system.cpu0.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=ArmTableWalker +clock=500 +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[2] + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu1] +type=TimingSimpleCPU +children=dtb interrupts isa itb tracer +checker=Null +clock=500 +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +isa=system.cpu1.isa +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +switched_out=true +system=system +tracer=system.cpu1.tracer +workload= + +[system.cpu1.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=ArmTableWalker +clock=500 +num_squash_per_cycle=2 +sys=system + +[system.cpu1.interrupts] +type=ArmInterrupts + +[system.cpu1.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + +[system.cpu1.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=ArmTableWalker +clock=500 +num_squash_per_cycle=2 +sys=system + +[system.cpu1.tracer] +type=ExeTracer + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=NoncoherentBus +block_size=64 +clock=1000 +header_cycles=1 +use_default_range=false +width=8 +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma + +[system.iocache] +type=BaseCache +addr_ranges=0:134217727 +assoc=8 +block_size=64 +clock=1000 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +size=1024 +system=system +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[25] +mem_side=system.membus.slave[2] + +[system.l2c] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +size=4194304 +system=system +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.membus] +type=CoherentBus +children=badaddr_responder +block_size=64 +clock=1000 +header_cycles=1 +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +slave=system.system_port system.l2c.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 +conf_table_reported=true +in_addr_map=true +lines_per_rowbuffer=64 +mem_sched_policy=fcfs +null=false +page_policy=open +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 +zero=false +port=system.membus.master[2] + +[system.realview] +type=RealView +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +intrctrl=system.intrctrl +max_mem_size=268435456 +mem_start_addr=0 +pci_cfg_base=0 +system=system + +[system.realview.a9scu] +type=A9SCU +clock=1000 +pio_addr=520093696 +pio_latency=100000 +system=system +pio=system.membus.master[5] + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268451840 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=402653184 +BAR0LegacyIO=true +BAR0Size=16 +BAR1=402653440 +BAR1LegacyIO=true +BAR1Size=1 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clock=1000 +config_latency=20000 +ctrl_offset=2 +disks=system.cf0 +io_shift=1 +pci_bus=2 +pci_dev=7 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[8] +dma=system.iobus.slave[2] +pio=system.iobus.master[7] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clock=1000 +gic=system.realview.gic +int_num=55 +pio_addr=268566528 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.dmac_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268632064 +pio_latency=100000 +system=system +pio=system.iobus.master[9] + +[system.realview.flash_fake] +type=IsaFake +clock=1000 +fake_mem=true +pio_addr=1073741824 +pio_latency=100000 +pio_size=536870912 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[24] + +[system.realview.gic] +type=Gic +clock=1000 +cpu_addr=520093952 +cpu_pio_delay=10000 +dist_addr=520097792 +dist_pio_delay=10000 +int_latency=10000 +it_lines=128 +platform=system.realview +system=system +pio=system.membus.master[3] + +[system.realview.gpio0_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268513280 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.gpio1_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268517376 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.realview.gpio2_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268521472 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clock=1000 +gic=system.realview.gic +int_delay=1000000 +int_num=52 +is_mouse=false +pio_addr=268460032 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[5] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clock=1000 +gic=system.realview.gic +int_delay=1000000 +int_num=53 +is_mouse=true +pio_addr=268464128 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.l2x0_fake] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=520101888 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.master[4] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clock=1000 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=520095232 +pio_latency=100000 +system=system +pio=system.membus.master[6] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268455936 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clock=1000 +conf_table_reported=false +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=2147483648:2214592511 +zero=true +port=system.membus.master[1] + +[system.realview.realview_io] +type=RealViewCtrl +clock=1000 +idreg=0 +pio_addr=268435456 +pio_latency=100000 +proc_id0=201326592 +proc_id1=201327138 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clock=1000 +gic=system.realview.gic +int_delay=100000 +int_num=42 +pio_addr=268529664 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[23] + +[system.realview.sci_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268492800 +pio_latency=100000 +system=system +pio=system.iobus.master[20] + +[system.realview.smc_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=269357056 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=true +pio_addr=268439552 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.ssp_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268488704 +pio_latency=100000 +system=system +pio=system.iobus.master[19] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clock=1000 +clock0=1000000 +clock1=1000000 +gic=system.realview.gic +int_num0=36 +int_num1=36 +pio_addr=268505088 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clock=1000 +clock0=1000000 +clock1=1000000 +gic=system.realview.gic +int_num0=37 +int_num1=37 +pio_addr=268509184 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clock=1000 +end_on_eot=false +gic=system.realview.gic +int_delay=100000 +int_num=44 +pio_addr=268472320 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268476416 +pio_latency=100000 +system=system +pio=system.iobus.master[10] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268480512 +pio_latency=100000 +system=system +pio=system.iobus.master[11] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268484608 +pio_latency=100000 +system=system +pio=system.iobus.master[12] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268500992 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=8 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port + +[system.vncserver] +type=VncServer +frame_capture=false +number=0 +port=5900 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr new file mode 100755 index 000000000..98bbe4187 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr @@ -0,0 +1,40 @@ +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: The clidr register always reports 0 caches. +warn: clidr LoUIS field of 0b001 to match current ARM implementations. +warn: The csselr register isn't implemented. +warn: The ccsidr register isn't implemented and always reads as 0. +hack: be nice to actually delete the event here +warn: instruction 'mcr bpiallis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr dccimvac' unimplemented +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented +warn: LCD dual screen mode not supported +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout new file mode 100755 index 000000000..7e73e93b0 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout @@ -0,0 +1,10763 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Dec 11 2012 16:28:23 +gem5 started Dec 11 2012 16:28:35 +gem5 executing on e103721-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: Using bootloader at address 0x80000000 +info: Entering event queue @ 0. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1000000000. Starting simulation... +switching cpus +info: Entering event queue @ 1000161000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2000161000. Starting simulation... +switching cpus +info: Entering event queue @ 2000162000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 3000162000. Starting simulation... +switching cpus +info: Entering event queue @ 3000209500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 4000209500. Starting simulation... +switching cpus +info: Entering event queue @ 4000253500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 5000253500. Starting simulation... +switching cpus +info: Entering event queue @ 5000254500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 6000254500. Starting simulation... +switching cpus +info: Entering event queue @ 6000255500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 7000255500. Starting simulation... +switching cpus +info: Entering event queue @ 7000257500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 8000257500. Starting simulation... +switching cpus +info: Entering event queue @ 8000258500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 9000258500. Starting simulation... +switching cpus +info: Entering event queue @ 9000473000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 10000473000. Starting simulation... +switching cpus +info: Entering event queue @ 10000475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 11000475000. Starting simulation... +switching cpus +info: Entering event queue @ 11000476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 12000476000. Starting simulation... +switching cpus +info: Entering event queue @ 12000477500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 13000477500. Starting simulation... +switching cpus +info: Entering event queue @ 13000479500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 14000479500. Starting simulation... +switching cpus +info: Entering event queue @ 14000481500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 15000481500. Starting simulation... +switching cpus +info: Entering event queue @ 15000483500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 16000483500. Starting simulation... +switching cpus +info: Entering event queue @ 16000485500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 17000485500. Starting simulation... +switching cpus +info: Entering event queue @ 17000486500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 18000486500. Starting simulation... +info: Entering event queue @ 18000493500. Starting simulation... +switching cpus +info: Entering event queue @ 18000496000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 19000496000. Starting simulation... +switching cpus +info: Entering event queue @ 19000497000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 20000497000. Starting simulation... +switching cpus +info: Entering event queue @ 20000498000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 21000498000. Starting simulation... +info: Entering event queue @ 21000511500. Starting simulation... +switching cpus +info: Entering event queue @ 21000513000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 22000513000. Starting simulation... +info: Entering event queue @ 22000516500. Starting simulation... +switching cpus +info: Entering event queue @ 22000518000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 23000518000. Starting simulation... +switching cpus +info: Entering event queue @ 23000519000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 24000519000. Starting simulation... +switching cpus +info: Entering event queue @ 24000634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 25000634000. Starting simulation... +info: Entering event queue @ 25000647000. Starting simulation... +switching cpus +info: Entering event queue @ 25000650500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 26000650500. Starting simulation... +info: Entering event queue @ 26000657000. Starting simulation... +switching cpus +info: Entering event queue @ 26000658500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 27000658500. Starting simulation... +info: Entering event queue @ 27000664500. Starting simulation... +switching cpus +info: Entering event queue @ 27000667000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 28000667000. Starting simulation... +switching cpus +info: Entering event queue @ 28000668000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 29000668000. Starting simulation... +switching cpus +info: Entering event queue @ 29000669000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 30000669000. Starting simulation... +switching cpus +info: Entering event queue @ 30000671000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 31000671000. Starting simulation... +info: Entering event queue @ 31000679500. Starting simulation... +switching cpus +info: Entering event queue @ 31000682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 32000682000. Starting simulation... +switching cpus +info: Entering event queue @ 32000683000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 33000683000. Starting simulation... +switching cpus +info: Entering event queue @ 33000684000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 34000684000. Starting simulation... +switching cpus +info: Entering event queue @ 34000685000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 35000685000. Starting simulation... +info: Entering event queue @ 35000871500. Starting simulation... +switching cpus +info: Entering event queue @ 35000872500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 36000872500. Starting simulation... +switching cpus +info: Entering event queue @ 36000875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 37000875000. Starting simulation... +switching cpus +info: Entering event queue @ 37001097000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 38001097000. Starting simulation... +switching cpus +info: Entering event queue @ 38001098000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 39001098000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 40001098000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 41001098000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 42001098000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 43001098000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 44001098000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 45001098000. Starting simulation... +switching cpus +info: Entering event queue @ 45001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 46001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 47001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 48001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 49001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 50001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 51001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 52001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 53001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 54001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 55001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 56001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 57001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 58001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 59001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 60001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 61001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 62001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 63001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 64001099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 65001099000. Starting simulation... +info: Entering event queue @ 66306421000. Starting simulation... +switching cpus +info: Entering event queue @ 66306423000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 67306423000. Starting simulation... +switching cpus +info: Entering event queue @ 67306432500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 68306432500. Starting simulation... +switching cpus +info: Entering event queue @ 68306442500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 69306442500. Starting simulation... +switching cpus +info: Entering event queue @ 69306452500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 70306452500. Starting simulation... +switching cpus +info: Entering event queue @ 70306453500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 71306453500. Starting simulation... +switching cpus +info: Entering event queue @ 71306514500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 72306514500. Starting simulation... +switching cpus +info: Entering event queue @ 72306516500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 73306516500. Starting simulation... +switching cpus +info: Entering event queue @ 73306518500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 74306518500. Starting simulation... +switching cpus +info: Entering event queue @ 74306519500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 75306519500. Starting simulation... +switching cpus +info: Entering event queue @ 75306520500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 76306520500. Starting simulation... +info: Entering event queue @ 76306542500. Starting simulation... +switching cpus +info: Entering event queue @ 76306583500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 77306583500. Starting simulation... +switching cpus +info: Entering event queue @ 77306585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 78306585500. Starting simulation... +switching cpus +info: Entering event queue @ 78306586500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 79306586500. Starting simulation... +switching cpus +info: Entering event queue @ 79306587500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 80306587500. Starting simulation... +switching cpus +info: Entering event queue @ 80306589500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 81306589500. Starting simulation... +info: Entering event queue @ 81306614500. Starting simulation... +switching cpus +info: Entering event queue @ 81306676500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 82306676500. Starting simulation... +info: Entering event queue @ 82306698500. Starting simulation... +switching cpus +info: Entering event queue @ 82306739500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 83306739500. Starting simulation... +switching cpus +info: Entering event queue @ 83306740500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 84306740500. Starting simulation... +switching cpus +info: Entering event queue @ 84306741500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 85306741500. Starting simulation... +switching cpus +info: Entering event queue @ 85306742500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 86306742500. Starting simulation... +switching cpus +info: Entering event queue @ 86306743500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 87306743500. Starting simulation... +info: Entering event queue @ 87306763500. Starting simulation... +switching cpus +info: Entering event queue @ 87306822500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 88306822500. Starting simulation... +switching cpus +info: Entering event queue @ 88306823500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 89306823500. Starting simulation... +switching cpus +info: Entering event queue @ 89306824500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 90306824500. Starting simulation... +info: Entering event queue @ 90306840500. Starting simulation... +switching cpus +info: Entering event queue @ 90306899500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 91306899500. Starting simulation... +switching cpus +info: Entering event queue @ 91306906500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 92306906500. Starting simulation... +switching cpus +info: Entering event queue @ 92306907500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 93306907500. Starting simulation... +switching cpus +info: Entering event queue @ 93306908500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 94306908500. Starting simulation... +switching cpus +info: Entering event queue @ 94306931500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 95306931500. Starting simulation... +switching cpus +info: Entering event queue @ 95306933500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 96306933500. Starting simulation... +switching cpus +info: Entering event queue @ 96307006500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 97307006500. Starting simulation... +info: Entering event queue @ 97307011500. Starting simulation... +switching cpus +info: Entering event queue @ 97307013000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 98307013000. Starting simulation... +info: Entering event queue @ 99022063000. Starting simulation... +switching cpus +info: Entering event queue @ 99022065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 100022065000. Starting simulation... +switching cpus +info: Entering event queue @ 100022065500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 101022065500. Starting simulation... +switching cpus +info: Entering event queue @ 101022067500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 102022067500. Starting simulation... +switching cpus +info: Entering event queue @ 102022068500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 103022068500. Starting simulation... +switching cpus +info: Entering event queue @ 103022072000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 104022072000. Starting simulation... +switching cpus +info: Entering event queue @ 104022073000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 105022073000. Starting simulation... +switching cpus +info: Entering event queue @ 105022074500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 106022074500. Starting simulation... +switching cpus +info: Entering event queue @ 106022075000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 107022075000. Starting simulation... +info: Entering event queue @ 107022087500. Starting simulation... +switching cpus +info: Entering event queue @ 107022090000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 108022090000. Starting simulation... +switching cpus +info: Entering event queue @ 108022090500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 109022090500. Starting simulation... +switching cpus +info: Entering event queue @ 109022092500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 110022092500. Starting simulation... +info: Entering event queue @ 110022099500. Starting simulation... +switching cpus +info: Entering event queue @ 110022103000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 111022103000. Starting simulation... +switching cpus +info: Entering event queue @ 111022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 112022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 113022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 114022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 115022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 116022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 117022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 118022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 119022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 120022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 121022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 122022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 123022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 124022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 125022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 126022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 127022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 128022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 129022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 130022104000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 131022104000. Starting simulation... +info: Entering event queue @ 131758663000. Starting simulation... +switching cpus +info: Entering event queue @ 131758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 132758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 133758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 134758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 135758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 136758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 137758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 138758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 139758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 140758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 141758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 142758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 143758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 144758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 145758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 146758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 147758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 148758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 149758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 150758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 151758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 152758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 153758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 154758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 155758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 156758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 157758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 158758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 159758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 160758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 161758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 162758665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 163758665000. Starting simulation... +info: Entering event queue @ 164494807000. Starting simulation... +switching cpus +info: Entering event queue @ 164494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 165494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 166494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 167494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 168494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 169494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 170494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 171494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 172494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 173494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 174494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 175494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 176494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 177494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 178494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 179494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 180494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 181494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 182494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 183494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 184494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 185494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 186494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 187494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 188494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 189494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 190494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 191494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 192494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 193494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 194494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 195494809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 196494809000. Starting simulation... +info: Entering event queue @ 197230954000. Starting simulation... +switching cpus +info: Entering event queue @ 197230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 198230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 199230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 200230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 201230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 202230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 203230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 204230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 205230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 206230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 207230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 208230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 209230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 210230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 211230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 212230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 213230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 214230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 215230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 216230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 217230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 218230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 219230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 220230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 221230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 222230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 223230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 224230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 225230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 226230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 227230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 228230956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 229230956000. Starting simulation... +info: Entering event queue @ 229967245000. Starting simulation... +switching cpus +info: Entering event queue @ 229967247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 230967247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 231967247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 232967247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 233967247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 234967247000. Starting simulation... +switching cpus +info: Entering event queue @ 234967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 235967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 236967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 237967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 238967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 239967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 240967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 241967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 242967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 243967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 244967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 245967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 246967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 247967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 248967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 249967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 250967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 251967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 252967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 253967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 254967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 255967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 256967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 257967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 258967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 259967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 260967248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 261967248000. Starting simulation... +info: Entering event queue @ 262703389000. Starting simulation... +switching cpus +info: Entering event queue @ 262703391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 263703391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 264703391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 265703391000. Starting simulation... +info: Entering event queue @ 265703411000. Starting simulation... +switching cpus +info: Entering event queue @ 265703413500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 266703413500. Starting simulation... +switching cpus +info: Entering event queue @ 266703416000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 267703416000. Starting simulation... +switching cpus +info: Entering event queue @ 267703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 268703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 269703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 270703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 271703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 272703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 273703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 274703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 275703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 276703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 277703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 278703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 279703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 280703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 281703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 282703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 283703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 284703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 285703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 286703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 287703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 288703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 289703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 290703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 291703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 292703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 293703417000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 294703417000. Starting simulation... +info: Entering event queue @ 295439680000. Starting simulation... +switching cpus +info: Entering event queue @ 295439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 296439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 297439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 298439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 299439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 300439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 301439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 302439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 303439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 304439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 305439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 306439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 307439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 308439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 309439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 310439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 311439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 312439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 313439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 314439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 315439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 316439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 317439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 318439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 319439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 320439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 321439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 322439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 323439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 324439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 325439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 326439682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 327439682000. Starting simulation... +info: Entering event queue @ 328175821000. Starting simulation... +switching cpus +info: Entering event queue @ 328175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 329175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 330175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 331175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 332175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 333175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 334175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 335175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 336175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 337175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 338175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 339175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 340175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 341175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 342175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 343175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 344175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 345175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 346175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 347175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 348175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 349175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 350175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 351175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 352175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 353175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 354175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 355175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 356175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 357175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 358175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 359175823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 360175823000. Starting simulation... +info: Entering event queue @ 360912115000. Starting simulation... +switching cpus +info: Entering event queue @ 360912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 361912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 362912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 363912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 364912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 365912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 366912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 367912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 368912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 369912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 370912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 371912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 372912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 373912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 374912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 375912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 376912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 377912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 378912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 379912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 380912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 381912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 382912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 383912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 384912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 385912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 386912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 387912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 388912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 389912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 390912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 391912117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 392912117000. Starting simulation... +info: Entering event queue @ 393648256000. Starting simulation... +switching cpus +info: Entering event queue @ 393648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 394648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 395648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 396648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 397648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 398648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 399648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 400648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 401648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 402648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 403648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 404648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 405648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 406648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 407648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 408648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 409648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 410648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 411648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 412648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 413648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 414648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 415648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 416648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 417648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 418648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 419648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 420648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 421648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 422648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 423648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 424648258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 425648258000. Starting simulation... +info: Entering event queue @ 426384856000. Starting simulation... +switching cpus +info: Entering event queue @ 426384858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 427384858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 428384858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 429384858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 430384858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 431384858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 432384858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 433384858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 434384858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 435384858000. Starting simulation... +switching cpus +info: Entering event queue @ 435384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 436384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 437384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 438384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 439384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 440384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 441384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 442384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 443384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 444384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 445384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 446384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 447384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 448384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 449384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 450384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 451384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 452384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 453384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 454384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 455384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 456384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 457384859000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 458384859000. Starting simulation... +info: Entering event queue @ 459121147000. Starting simulation... +switching cpus +info: Entering event queue @ 459121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 460121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 461121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 462121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 463121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 464121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 465121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 466121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 467121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 468121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 469121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 470121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 471121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 472121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 473121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 474121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 475121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 476121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 477121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 478121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 479121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 480121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 481121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 482121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 483121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 484121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 485121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 486121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 487121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 488121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 489121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 490121149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 491121149000. Starting simulation... +info: Entering event queue @ 491857291000. Starting simulation... +switching cpus +info: Entering event queue @ 491857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 492857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 493857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 494857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 495857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 496857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 497857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 498857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 499857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 500857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 501857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 502857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 503857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 504857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 505857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 506857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 507857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 508857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 509857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 510857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 511857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 512857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 513857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 514857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 515857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 516857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 517857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 518857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 519857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 520857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 521857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 522857293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 523857293000. Starting simulation... +info: Entering event queue @ 524593582000. Starting simulation... +switching cpus +info: Entering event queue @ 524593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 525593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 526593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 527593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 528593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 529593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 530593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 531593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 532593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 533593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 534593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 535593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 536593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 537593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 538593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 539593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 540593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 541593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 542593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 543593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 544593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 545593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 546593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 547593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 548593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 549593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 550593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 551593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 552593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 553593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 554593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 555593584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 556593584000. Starting simulation... +info: Entering event queue @ 557329726000. Starting simulation... +switching cpus +info: Entering event queue @ 557329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 558329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 559329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 560329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 561329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 562329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 563329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 564329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 565329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 566329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 567329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 568329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 569329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 570329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 571329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 572329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 573329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 574329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 575329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 576329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 577329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 578329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 579329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 580329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 581329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 582329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 583329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 584329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 585329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 586329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 587329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 588329728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 589329728000. Starting simulation... +info: Entering event queue @ 590065873000. Starting simulation... +switching cpus +info: Entering event queue @ 590065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 591065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 592065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 593065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 594065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 595065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 596065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 597065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 598065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 599065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 600065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 601065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 602065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 603065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 604065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 605065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 606065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 607065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 608065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 609065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 610065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 611065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 612065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 613065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 614065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 615065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 616065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 617065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 618065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 619065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 620065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 621065875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 622065875000. Starting simulation... +info: Entering event queue @ 622802473000. Starting simulation... +switching cpus +info: Entering event queue @ 622802475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 623802475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 624802475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 625802475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 626802475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 627802475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 628802475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 629802475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 630802475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 631802475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 632802475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 633802475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 634802475000. Starting simulation... +switching cpus +info: Entering event queue @ 634802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 635802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 636802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 637802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 638802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 639802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 640802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 641802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 642802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 643802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 644802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 645802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 646802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 647802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 648802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 649802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 650802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 651802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 652802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 653802476000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 654802476000. Starting simulation... +info: Entering event queue @ 655538305000. Starting simulation... +switching cpus +info: Entering event queue @ 655538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 656538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 657538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 658538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 659538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 660538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 661538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 662538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 663538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 664538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 665538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 666538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 667538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 668538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 669538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 670538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 671538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 672538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 673538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 674538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 675538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 676538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 677538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 678538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 679538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 680538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 681538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 682538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 683538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 684538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 685538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 686538307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 687538307000. Starting simulation... +info: Entering event queue @ 688274905000. Starting simulation... +switching cpus +info: Entering event queue @ 688274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 689274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 690274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 691274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 692274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 693274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 694274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 695274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 696274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 697274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 698274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 699274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 700274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 701274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 702274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 703274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 704274907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 705274907000. Starting simulation... +switching cpus +info: Entering event queue @ 705274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 706274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 707274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 708274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 709274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 710274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 711274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 712274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 713274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 714274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 715274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 716274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 717274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 718274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 719274908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 720274908000. Starting simulation... +info: Entering event queue @ 721011196000. Starting simulation... +switching cpus +info: Entering event queue @ 721011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 722011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 723011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 724011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 725011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 726011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 727011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 728011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 729011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 730011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 731011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 732011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 733011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 734011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 735011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 736011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 737011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 738011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 739011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 740011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 741011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 742011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 743011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 744011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 745011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 746011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 747011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 748011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 749011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 750011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 751011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 752011198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 753011198000. Starting simulation... +info: Entering event queue @ 753747337000. Starting simulation... +switching cpus +info: Entering event queue @ 753747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 754747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 755747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 756747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 757747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 758747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 759747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 760747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 761747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 762747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 763747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 764747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 765747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 766747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 767747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 768747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 769747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 770747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 771747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 772747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 773747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 774747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 775747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 776747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 777747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 778747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 779747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 780747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 781747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 782747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 783747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 784747339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 785747339000. Starting simulation... +info: Entering event queue @ 786483631000. Starting simulation... +switching cpus +info: Entering event queue @ 786483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 787483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 788483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 789483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 790483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 791483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 792483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 793483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 794483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 795483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 796483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 797483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 798483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 799483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 800483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 801483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 802483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 803483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 804483633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 805483633000. Starting simulation... +switching cpus +info: Entering event queue @ 805483634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 806483634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 807483634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 808483634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 809483634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 810483634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 811483634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 812483634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 813483634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 814483634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 815483634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 816483634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 817483634000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 818483634000. Starting simulation... +info: Entering event queue @ 819219772000. Starting simulation... +switching cpus +info: Entering event queue @ 819219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 820219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 821219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 822219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 823219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 824219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 825219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 826219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 827219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 828219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 829219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 830219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 831219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 832219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 833219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 834219774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 835219774000. Starting simulation... +switching cpus +info: Entering event queue @ 835219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 836219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 837219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 838219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 839219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 840219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 841219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 842219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 843219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 844219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 845219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 846219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 847219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 848219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 849219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 850219775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 851219775000. Starting simulation... +info: Entering event queue @ 851956063000. Starting simulation... +switching cpus +info: Entering event queue @ 851956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 852956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 853956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 854956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 855956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 856956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 857956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 858956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 859956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 860956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 861956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 862956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 863956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 864956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 865956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 866956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 867956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 868956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 869956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 870956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 871956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 872956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 873956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 874956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 875956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 876956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 877956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 878956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 879956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 880956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 881956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 882956065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 883956065000. Starting simulation... +info: Entering event queue @ 884692663000. Starting simulation... +switching cpus +info: Entering event queue @ 884692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 885692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 886692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 887692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 888692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 889692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 890692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 891692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 892692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 893692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 894692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 895692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 896692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 897692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 898692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 899692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 900692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 901692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 902692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 903692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 904692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 905692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 906692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 907692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 908692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 909692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 910692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 911692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 912692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 913692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 914692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 915692665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 916692665000. Starting simulation... +info: Entering event queue @ 917428807000. Starting simulation... +switching cpus +info: Entering event queue @ 917428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 918428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 919428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 920428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 921428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 922428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 923428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 924428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 925428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 926428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 927428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 928428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 929428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 930428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 931428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 932428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 933428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 934428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 935428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 936428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 937428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 938428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 939428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 940428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 941428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 942428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 943428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 944428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 945428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 946428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 947428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 948428809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 949428809000. Starting simulation... +info: Entering event queue @ 950164954000. Starting simulation... +switching cpus +info: Entering event queue @ 950164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 951164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 952164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 953164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 954164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 955164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 956164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 957164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 958164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 959164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 960164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 961164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 962164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 963164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 964164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 965164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 966164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 967164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 968164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 969164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 970164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 971164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 972164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 973164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 974164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 975164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 976164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 977164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 978164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 979164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 980164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 981164956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 982164956000. Starting simulation... +info: Entering event queue @ 982901245000. Starting simulation... +switching cpus +info: Entering event queue @ 982901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 983901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 984901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 985901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 986901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 987901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 988901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 989901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 990901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 991901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 992901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 993901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 994901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 995901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 996901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 997901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 998901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 999901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1000901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1001901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1002901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1003901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1004901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1005901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1006901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1007901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1008901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1009901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1010901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1011901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1012901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1013901247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1014901247000. Starting simulation... +info: Entering event queue @ 1015637389000. Starting simulation... +switching cpus +info: Entering event queue @ 1015637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1016637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1017637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1018637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1019637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1020637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1021637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1022637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1023637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1024637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1025637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1026637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1027637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1028637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1029637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1030637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1031637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1032637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1033637391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1034637391000. Starting simulation... +switching cpus +info: Entering event queue @ 1034637391500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1035637391500. Starting simulation... +switching cpus +info: Entering event queue @ 1035637392500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1036637392500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1037637392500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1038637392500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1039637392500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1040637392500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1041637392500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1042637392500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1043637392500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1044637392500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1045637392500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1046637392500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1047637392500. Starting simulation... +info: Entering event queue @ 1048373680000. Starting simulation... +switching cpus +info: Entering event queue @ 1048373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1049373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1050373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1051373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1052373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1053373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1054373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1055373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1056373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1057373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1058373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1059373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1060373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1061373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1062373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1063373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1064373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1065373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1066373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1067373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1068373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1069373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1070373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1071373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1072373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1073373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1074373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1075373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1076373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1077373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1078373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1079373682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1080373682000. Starting simulation... +info: Entering event queue @ 1081109821000. Starting simulation... +switching cpus +info: Entering event queue @ 1081109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1082109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1083109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1084109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1085109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1086109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1087109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1088109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1089109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1090109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1091109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1092109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1093109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1094109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1095109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1096109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1097109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1098109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1099109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1100109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1101109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1102109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1103109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1104109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1105109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1106109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1107109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1108109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1109109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1110109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1111109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1112109823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1113109823000. Starting simulation... +info: Entering event queue @ 1113846115000. Starting simulation... +switching cpus +info: Entering event queue @ 1113846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1114846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1115846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1116846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1117846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1118846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1119846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1120846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1121846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1122846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1123846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1124846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1125846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1126846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1127846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1128846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1129846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1130846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1131846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1132846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1133846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1134846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1135846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1136846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1137846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1138846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1139846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1140846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1141846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1142846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1143846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1144846117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1145846117000. Starting simulation... +info: Entering event queue @ 1146582256000. Starting simulation... +switching cpus +info: Entering event queue @ 1146582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1147582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1148582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1149582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1150582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1151582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1152582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1153582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1154582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1155582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1156582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1157582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1158582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1159582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1160582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1161582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1162582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1163582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1164582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1165582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1166582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1167582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1168582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1169582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1170582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1171582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1172582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1173582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1174582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1175582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1176582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1177582258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1178582258000. Starting simulation... +info: Entering event queue @ 1179318856000. Starting simulation... +switching cpus +info: Entering event queue @ 1179318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1180318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1181318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1182318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1183318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1184318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1185318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1186318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1187318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1188318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1189318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1190318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1191318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1192318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1193318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1194318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1195318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1196318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1197318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1198318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1199318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1200318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1201318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1202318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1203318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1204318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1205318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1206318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1207318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1208318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1209318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1210318858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1211318858000. Starting simulation... +info: Entering event queue @ 1212055147000. Starting simulation... +switching cpus +info: Entering event queue @ 1212055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1213055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1214055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1215055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1216055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1217055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1218055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1219055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1220055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1221055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1222055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1223055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1224055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1225055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1226055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1227055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1228055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1229055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1230055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1231055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1232055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1233055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1234055149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1235055149000. Starting simulation... +switching cpus +info: Entering event queue @ 1235055150000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1236055150000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1237055150000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1238055150000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1239055150000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1240055150000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1241055150000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1242055150000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1243055150000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1244055150000. Starting simulation... +info: Entering event queue @ 1244791291000. Starting simulation... +switching cpus +info: Entering event queue @ 1244791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1245791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1246791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1247791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1248791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1249791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1250791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1251791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1252791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1253791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1254791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1255791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1256791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1257791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1258791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1259791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1260791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1261791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1262791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1263791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1264791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1265791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1266791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1267791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1268791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1269791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1270791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1271791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1272791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1273791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1274791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1275791293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1276791293000. Starting simulation... +info: Entering event queue @ 1277527582000. Starting simulation... +switching cpus +info: Entering event queue @ 1277527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1278527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1279527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1280527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1281527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1282527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1283527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1284527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1285527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1286527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1287527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1288527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1289527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1290527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1291527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1292527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1293527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1294527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1295527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1296527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1297527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1298527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1299527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1300527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1301527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1302527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1303527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1304527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1305527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1306527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1307527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1308527584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1309527584000. Starting simulation... +info: Entering event queue @ 1310263726000. Starting simulation... +switching cpus +info: Entering event queue @ 1310263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1311263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1312263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1313263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1314263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1315263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1316263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1317263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1318263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1319263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1320263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1321263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1322263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1323263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1324263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1325263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1326263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1327263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1328263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1329263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1330263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1331263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1332263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1333263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1334263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1335263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1336263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1337263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1338263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1339263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1340263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1341263728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1342263728000. Starting simulation... +info: Entering event queue @ 1342999873000. Starting simulation... +switching cpus +info: Entering event queue @ 1342999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1343999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1344999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1345999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1346999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1347999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1348999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1349999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1350999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1351999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1352999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1353999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1354999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1355999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1356999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1357999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1358999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1359999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1360999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1361999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1362999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1363999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1364999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1365999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1366999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1367999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1368999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1369999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1370999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1371999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1372999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1373999875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1374999875000. Starting simulation... +info: Entering event queue @ 1375736473000. Starting simulation... +switching cpus +info: Entering event queue @ 1375736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1376736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1377736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1378736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1379736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1380736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1381736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1382736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1383736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1384736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1385736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1386736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1387736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1388736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1389736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1390736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1391736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1392736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1393736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1394736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1395736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1396736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1397736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1398736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1399736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1400736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1401736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1402736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1403736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1404736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1405736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1406736475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1407736475000. Starting simulation... +info: Entering event queue @ 1408472305000. Starting simulation... +switching cpus +info: Entering event queue @ 1408472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1409472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1410472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1411472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1412472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1413472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1414472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1415472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1416472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1417472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1418472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1419472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1420472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1421472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1422472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1423472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1424472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1425472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1426472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1427472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1428472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1429472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1430472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1431472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1432472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1433472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1434472307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1435472307000. Starting simulation... +switching cpus +info: Entering event queue @ 1435472308000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1436472308000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1437472308000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1438472308000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1439472308000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1440472308000. Starting simulation... +info: Entering event queue @ 1441208905000. Starting simulation... +switching cpus +info: Entering event queue @ 1441208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1442208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1443208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1444208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1445208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1446208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1447208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1448208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1449208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1450208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1451208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1452208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1453208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1454208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1455208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1456208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1457208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1458208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1459208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1460208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1461208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1462208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1463208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1464208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1465208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1466208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1467208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1468208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1469208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1470208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1471208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1472208907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1473208907000. Starting simulation... +info: Entering event queue @ 1473945196000. Starting simulation... +switching cpus +info: Entering event queue @ 1473945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1474945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1475945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1476945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1477945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1478945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1479945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1480945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1481945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1482945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1483945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1484945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1485945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1486945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1487945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1488945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1489945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1490945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1491945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1492945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1493945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1494945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1495945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1496945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1497945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1498945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1499945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1500945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1501945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1502945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1503945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1504945198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1505945198000. Starting simulation... +info: Entering event queue @ 1506681337000. Starting simulation... +switching cpus +info: Entering event queue @ 1506681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1507681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1508681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1509681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1510681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1511681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1512681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1513681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1514681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1515681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1516681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1517681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1518681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1519681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1520681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1521681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1522681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1523681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1524681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1525681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1526681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1527681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1528681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1529681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1530681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1531681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1532681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1533681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1534681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1535681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1536681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1537681339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1538681339000. Starting simulation... +info: Entering event queue @ 1539417631000. Starting simulation... +switching cpus +info: Entering event queue @ 1539417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1540417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1541417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1542417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1543417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1544417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1545417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1546417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1547417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1548417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1549417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1550417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1551417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1552417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1553417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1554417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1555417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1556417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1557417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1558417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1559417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1560417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1561417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1562417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1563417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1564417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1565417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1566417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1567417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1568417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1569417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1570417633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1571417633000. Starting simulation... +info: Entering event queue @ 1572153772000. Starting simulation... +switching cpus +info: Entering event queue @ 1572153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1573153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1574153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1575153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1576153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1577153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1578153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1579153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1580153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1581153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1582153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1583153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1584153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1585153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1586153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1587153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1588153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1589153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1590153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1591153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1592153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1593153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1594153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1595153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1596153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1597153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1598153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1599153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1600153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1601153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1602153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1603153774000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1604153774000. Starting simulation... +info: Entering event queue @ 1604890063000. Starting simulation... +switching cpus +info: Entering event queue @ 1604890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1605890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1606890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1607890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1608890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1609890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1610890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1611890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1612890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1613890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1614890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1615890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1616890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1617890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1618890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1619890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1620890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1621890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1622890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1623890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1624890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1625890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1626890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1627890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1628890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1629890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1630890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1631890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1632890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1633890065000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1634890065000. Starting simulation... +switching cpus +info: Entering event queue @ 1634890066000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1635890066000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1636890066000. Starting simulation... +info: Entering event queue @ 1637626663000. Starting simulation... +switching cpus +info: Entering event queue @ 1637626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1638626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1639626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1640626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1641626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1642626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1643626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1644626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1645626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1646626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1647626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1648626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1649626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1650626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1651626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1652626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1653626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1654626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1655626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1656626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1657626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1658626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1659626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1660626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1661626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1662626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1663626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1664626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1665626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1666626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1667626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1668626665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1669626665000. Starting simulation... +info: Entering event queue @ 1670362807000. Starting simulation... +switching cpus +info: Entering event queue @ 1670362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1671362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1672362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1673362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1674362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1675362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1676362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1677362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1678362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1679362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1680362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1681362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1682362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1683362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1684362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1685362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1686362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1687362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1688362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1689362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1690362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1691362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1692362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1693362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1694362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1695362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1696362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1697362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1698362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1699362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1700362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1701362809000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1702362809000. Starting simulation... +info: Entering event queue @ 1703098954000. Starting simulation... +switching cpus +info: Entering event queue @ 1703098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1704098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1705098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1706098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1707098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1708098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1709098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1710098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1711098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1712098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1713098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1714098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1715098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1716098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1717098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1718098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1719098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1720098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1721098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1722098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1723098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1724098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1725098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1726098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1727098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1728098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1729098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1730098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1731098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1732098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1733098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1734098956000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1735098956000. Starting simulation... +info: Entering event queue @ 1735835245000. Starting simulation... +switching cpus +info: Entering event queue @ 1735835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1736835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1737835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1738835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1739835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1740835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1741835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1742835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1743835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1744835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1745835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1746835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1747835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1748835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1749835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1750835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1751835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1752835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1753835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1754835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1755835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1756835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1757835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1758835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1759835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1760835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1761835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1762835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1763835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1764835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1765835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1766835247000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1767835247000. Starting simulation... +info: Entering event queue @ 1768571389000. Starting simulation... +switching cpus +info: Entering event queue @ 1768571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1769571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1770571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1771571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1772571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1773571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1774571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1775571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1776571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1777571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1778571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1779571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1780571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1781571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1782571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1783571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1784571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1785571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1786571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1787571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1788571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1789571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1790571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1791571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1792571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1793571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1794571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1795571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1796571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1797571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1798571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1799571391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1800571391000. Starting simulation... +info: Entering event queue @ 1801307680000. Starting simulation... +switching cpus +info: Entering event queue @ 1801307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1802307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1803307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1804307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1805307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1806307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1807307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1808307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1809307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1810307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1811307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1812307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1813307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1814307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1815307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1816307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1817307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1818307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1819307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1820307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1821307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1822307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1823307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1824307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1825307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1826307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1827307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1828307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1829307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1830307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1831307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1832307682000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1833307682000. Starting simulation... +info: Entering event queue @ 1834043821000. Starting simulation... +switching cpus +info: Entering event queue @ 1834043823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1835043823000. Starting simulation... +switching cpus +info: Entering event queue @ 1835043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1836043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1837043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1838043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1839043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1840043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1841043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1842043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1843043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1844043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1845043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1846043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1847043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1848043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1849043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1850043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1851043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1852043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1853043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1854043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1855043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1856043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1857043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1858043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1859043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1860043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1861043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1862043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1863043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1864043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1865043824000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1866043824000. Starting simulation... +info: Entering event queue @ 1866780115000. Starting simulation... +switching cpus +info: Entering event queue @ 1866780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1867780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1868780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1869780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1870780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1871780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1872780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1873780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1874780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1875780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1876780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1877780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1878780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1879780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1880780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1881780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1882780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1883780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1884780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1885780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1886780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1887780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1888780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1889780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1890780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1891780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1892780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1893780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1894780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1895780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1896780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1897780117000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1898780117000. Starting simulation... +info: Entering event queue @ 1899516256000. Starting simulation... +switching cpus +info: Entering event queue @ 1899516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1900516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1901516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1902516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1903516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1904516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1905516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1906516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1907516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1908516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1909516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1910516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1911516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1912516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1913516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1914516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1915516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1916516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1917516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1918516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1919516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1920516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1921516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1922516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1923516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1924516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1925516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1926516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1927516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1928516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1929516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1930516258000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1931516258000. Starting simulation... +info: Entering event queue @ 1932252856000. Starting simulation... +switching cpus +info: Entering event queue @ 1932252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1933252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1934252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1935252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1936252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1937252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1938252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1939252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1940252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1941252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1942252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1943252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1944252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1945252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1946252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1947252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1948252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1949252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1950252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1951252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1952252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1953252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1954252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1955252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1956252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1957252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1958252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1959252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1960252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1961252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1962252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1963252858000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1964252858000. Starting simulation... +info: Entering event queue @ 1964989147000. Starting simulation... +switching cpus +info: Entering event queue @ 1964989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1965989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1966989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1967989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1968989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1969989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1970989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1971989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1972989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1973989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1974989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1975989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1976989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1977989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1978989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1979989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1980989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1981989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1982989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1983989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1984989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1985989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1986989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1987989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1988989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1989989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1990989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1991989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1992989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1993989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1994989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1995989149000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 1996989149000. Starting simulation... +info: Entering event queue @ 1997725291000. Starting simulation... +switching cpus +info: Entering event queue @ 1997725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1998725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1999725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2000725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2001725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2002725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2003725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2004725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2005725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2006725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2007725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2008725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2009725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2010725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2011725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2012725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2013725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2014725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2015725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2016725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2017725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2018725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2019725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2020725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2021725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2022725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2023725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2024725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2025725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2026725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2027725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2028725293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2029725293000. Starting simulation... +info: Entering event queue @ 2030461582000. Starting simulation... +switching cpus +info: Entering event queue @ 2030461584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2031461584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2032461584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2033461584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2034461584000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2035461584000. Starting simulation... +switching cpus +info: Entering event queue @ 2035461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2036461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2037461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2038461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2039461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2040461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2041461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2042461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2043461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2044461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2045461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2046461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2047461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2048461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2049461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2050461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2051461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2052461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2053461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2054461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2055461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2056461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2057461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2058461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2059461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2060461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2061461585000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2062461585000. Starting simulation... +info: Entering event queue @ 2063197726000. Starting simulation... +switching cpus +info: Entering event queue @ 2063197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2064197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2065197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2066197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2067197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2068197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2069197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2070197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2071197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2072197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2073197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2074197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2075197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2076197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2077197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2078197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2079197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2080197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2081197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2082197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2083197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2084197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2085197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2086197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2087197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2088197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2089197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2090197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2091197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2092197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2093197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2094197728000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2095197728000. Starting simulation... +info: Entering event queue @ 2095933873000. Starting simulation... +switching cpus +info: Entering event queue @ 2095933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2096933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2097933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2098933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2099933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2100933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2101933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2102933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2103933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2104933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2105933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2106933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2107933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2108933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2109933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2110933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2111933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2112933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2113933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2114933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2115933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2116933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2117933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2118933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2119933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2120933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2121933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2122933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2123933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2124933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2125933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2126933875000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2127933875000. Starting simulation... +info: Entering event queue @ 2128670473000. Starting simulation... +switching cpus +info: Entering event queue @ 2128670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2129670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2130670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2131670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2132670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2133670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2134670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2135670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2136670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2137670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2138670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2139670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2140670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2141670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2142670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2143670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2144670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2145670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2146670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2147670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2148670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2149670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2150670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2151670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2152670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2153670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2154670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2155670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2156670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2157670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2158670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2159670475000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2160670475000. Starting simulation... +info: Entering event queue @ 2161406305000. Starting simulation... +switching cpus +info: Entering event queue @ 2161406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2162406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2163406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2164406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2165406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2166406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2167406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2168406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2169406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2170406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2171406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2172406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2173406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2174406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2175406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2176406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2177406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2178406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2179406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2180406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2181406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2182406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2183406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2184406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2185406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2186406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2187406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2188406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2189406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2190406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2191406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2192406307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2193406307000. Starting simulation... +info: Entering event queue @ 2194142905000. Starting simulation... +switching cpus +info: Entering event queue @ 2194142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2195142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2196142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2197142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2198142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2199142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2200142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2201142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2202142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2203142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2204142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2205142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2206142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2207142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2208142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2209142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2210142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2211142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2212142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2213142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2214142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2215142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2216142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2217142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2218142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2219142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2220142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2221142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2222142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2223142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2224142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2225142907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2226142907000. Starting simulation... +info: Entering event queue @ 2226879196000. Starting simulation... +switching cpus +info: Entering event queue @ 2226879198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2227879198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2228879198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2229879198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2230879198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2231879198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2232879198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2233879198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2234879198000. Starting simulation... +switching cpus +info: Entering event queue @ 2234879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2235879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2236879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2237879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2238879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2239879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2240879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2241879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2242879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2243879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2244879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2245879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2246879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2247879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2248879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2249879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2250879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2251879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2252879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2253879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2254879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2255879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2256879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2257879199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2258879199000. Starting simulation... +info: Entering event queue @ 2259615337000. Starting simulation... +switching cpus +info: Entering event queue @ 2259615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2260615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2261615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2262615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2263615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2264615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2265615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2266615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2267615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2268615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2269615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2270615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2271615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2272615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2273615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2274615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2275615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2276615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2277615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2278615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2279615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2280615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2281615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2282615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2283615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2284615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2285615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2286615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2287615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2288615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2289615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2290615339000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2291615339000. Starting simulation... +info: Entering event queue @ 2292351631000. Starting simulation... +switching cpus +info: Entering event queue @ 2292351633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2293351633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2294351633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2295351633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2296351633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2297351633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2298351633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2299351633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2300351633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2301351633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2302351633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2303351633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2304351633000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2305351633000. Starting simulation... +switching cpus +info: Entering event queue @ 2305351696000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2306351696000. Starting simulation... +switching cpus +info: Entering event queue @ 2306351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2307351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2308351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2309351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2310351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2311351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2312351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2313351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2314351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2315351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2316351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2317351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2318351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2319351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2320351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2321351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2322351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2323351697000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2324351697000. Starting simulation... +info: Entering event queue @ 2325088231000. Starting simulation... +switching cpus +info: Entering event queue @ 2325088237000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2326088237000. Starting simulation... +switching cpus +info: Entering event queue @ 2326088238500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2327088238500. Starting simulation... +switching cpus +info: Entering event queue @ 2327088324000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2328088324000. Starting simulation... +switching cpus +info: Entering event queue @ 2328088325000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2329088325000. Starting simulation... +switching cpus +info: Entering event queue @ 2329088480000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2330088480000. Starting simulation... +switching cpus +info: Entering event queue @ 2330088481000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2331088481000. Starting simulation... +switching cpus +info: Entering event queue @ 2331088482000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2332088482000. Starting simulation... +switching cpus +info: Entering event queue @ 2332088483000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2333088483000. Starting simulation... +switching cpus +info: Entering event queue @ 2333088484000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2334088484000. Starting simulation... +switching cpus +info: Entering event queue @ 2334088485000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2335088485000. Starting simulation... +switching cpus +info: Entering event queue @ 2335088511000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2336088511000. Starting simulation... +switching cpus +info: Entering event queue @ 2336088552000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2337088552000. Starting simulation... +switching cpus +info: Entering event queue @ 2337088554000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2338088554000. Starting simulation... +switching cpus +info: Entering event queue @ 2338088597000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2339088597000. Starting simulation... +switching cpus +info: Entering event queue @ 2339088612000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2340088612000. Starting simulation... +switching cpus +info: Entering event queue @ 2340088674000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2341088674000. Starting simulation... +switching cpus +info: Entering event queue @ 2341088772000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2342088772000. Starting simulation... +switching cpus +info: Entering event queue @ 2342088773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2343088773000. Starting simulation... +switching cpus +info: Entering event queue @ 2343088775000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2344088775000. Starting simulation... +switching cpus +info: Entering event queue @ 2344088789000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2345088789000. Starting simulation... +switching cpus +info: Entering event queue @ 2345088919000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2346088919000. Starting simulation... +switching cpus +info: Entering event queue @ 2346088990000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2347088990000. Starting simulation... +switching cpus +info: Entering event queue @ 2347089092000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2348089092000. Starting simulation... +switching cpus +info: Entering event queue @ 2348089095500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2349089095500. Starting simulation... +switching cpus +info: Entering event queue @ 2349089096500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2350089096500. Starting simulation... +switching cpus +info: Entering event queue @ 2350089098500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2351089098500. Starting simulation... +switching cpus +info: Entering event queue @ 2351089113000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2352089113000. Starting simulation... +switching cpus +info: Entering event queue @ 2352089199000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2353089199000. Starting simulation... +switching cpus +info: Entering event queue @ 2353089200000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2354089200000. Starting simulation... +switching cpus +info: Entering event queue @ 2354089248000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2355089248000. Starting simulation... +switching cpus +info: Entering event queue @ 2355089265000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2356089265000. Starting simulation... +switching cpus +info: Entering event queue @ 2356089316000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2357089316000. Starting simulation... +info: Entering event queue @ 2357824372000. Starting simulation... +switching cpus +info: Entering event queue @ 2357824374000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2358824374000. Starting simulation... +switching cpus +info: Entering event queue @ 2358824488000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2359824488000. Starting simulation... +switching cpus +info: Entering event queue @ 2359824489000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2360824489000. Starting simulation... +switching cpus +info: Entering event queue @ 2360824618000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2361824618000. Starting simulation... +switching cpus +info: Entering event queue @ 2361824637000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2362824637000. Starting simulation... +switching cpus +info: Entering event queue @ 2362824638000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2363824638000. Starting simulation... +switching cpus +info: Entering event queue @ 2363824687000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2364824687000. Starting simulation... +switching cpus +info: Entering event queue @ 2364824823000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2365824823000. Starting simulation... +switching cpus +info: Entering event queue @ 2365824964000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2366824964000. Starting simulation... +switching cpus +info: Entering event queue @ 2366824989000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2367824989000. Starting simulation... +switching cpus +info: Entering event queue @ 2367825012000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2368825012000. Starting simulation... +switching cpus +info: Entering event queue @ 2368825145000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2369825145000. Starting simulation... +switching cpus +info: Entering event queue @ 2369825146000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2370825146000. Starting simulation... +switching cpus +info: Entering event queue @ 2370825288000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2371825288000. Starting simulation... +switching cpus +info: Entering event queue @ 2371825289000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2372825289000. Starting simulation... +switching cpus +info: Entering event queue @ 2372825296000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2373825296000. Starting simulation... +switching cpus +info: Entering event queue @ 2373825361000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2374825361000. Starting simulation... +switching cpus +info: Entering event queue @ 2374825463000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2375825463000. Starting simulation... +switching cpus +info: Entering event queue @ 2375825612000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2376825612000. Starting simulation... +switching cpus +info: Entering event queue @ 2376825684000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2377825684000. Starting simulation... +switching cpus +info: Entering event queue @ 2377825750000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2378825750000. Starting simulation... +switching cpus +info: Entering event queue @ 2378825867000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2379825867000. Starting simulation... +switching cpus +info: Entering event queue @ 2379825907000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2380825907000. Starting simulation... +switching cpus +info: Entering event queue @ 2380825985000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2381825985000. Starting simulation... +switching cpus +info: Entering event queue @ 2381826127000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2382826127000. Starting simulation... +switching cpus +info: Entering event queue @ 2382826217000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2383826217000. Starting simulation... +switching cpus +info: Entering event queue @ 2383826218000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2384826218000. Starting simulation... +switching cpus +info: Entering event queue @ 2384826219000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2385826219000. Starting simulation... +switching cpus +info: Entering event queue @ 2385826249000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2386826249000. Starting simulation... +switching cpus +info: Entering event queue @ 2386826330000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2387826330000. Starting simulation... +switching cpus +info: Entering event queue @ 2387826331000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2388826331000. Starting simulation... +switching cpus +info: Entering event queue @ 2388826388000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2389826388000. Starting simulation... +info: Entering event queue @ 2390560663000. Starting simulation... +switching cpus +info: Entering event queue @ 2390560665000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2391560665000. Starting simulation... +switching cpus +info: Entering event queue @ 2391560666000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2392560666000. Starting simulation... +switching cpus +info: Entering event queue @ 2392560703000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2393560703000. Starting simulation... +switching cpus +info: Entering event queue @ 2393560798000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2394560798000. Starting simulation... +switching cpus +info: Entering event queue @ 2394560799000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2395560799000. Starting simulation... +switching cpus +info: Entering event queue @ 2395560928000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2396560928000. Starting simulation... +switching cpus +info: Entering event queue @ 2396561075000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2397561075000. Starting simulation... +switching cpus +info: Entering event queue @ 2397561139000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2398561139000. Starting simulation... +switching cpus +info: Entering event queue @ 2398561189000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2399561189000. Starting simulation... +switching cpus +info: Entering event queue @ 2399561344000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2400561344000. Starting simulation... +switching cpus +info: Entering event queue @ 2400561484000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2401561484000. Starting simulation... +switching cpus +info: Entering event queue @ 2401561534000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2402561534000. Starting simulation... +switching cpus +info: Entering event queue @ 2402561628000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2403561628000. Starting simulation... +switching cpus +info: Entering event queue @ 2403561712000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2404561712000. Starting simulation... +switching cpus +info: Entering event queue @ 2404561726000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2405561726000. Starting simulation... +switching cpus +info: Entering event queue @ 2405561835000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2406561835000. Starting simulation... +switching cpus +info: Entering event queue @ 2406561960000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2407561960000. Starting simulation... +switching cpus +info: Entering event queue @ 2407562071000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2408562071000. Starting simulation... +switching cpus +info: Entering event queue @ 2408562185000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2409562185000. Starting simulation... +switching cpus +info: Entering event queue @ 2409562309000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2410562309000. Starting simulation... +switching cpus +info: Entering event queue @ 2410562346000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2411562346000. Starting simulation... +switching cpus +info: Entering event queue @ 2411562485000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2412562485000. Starting simulation... +switching cpus +info: Entering event queue @ 2412562486000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2413562486000. Starting simulation... +switching cpus +info: Entering event queue @ 2413562559000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2414562559000. Starting simulation... +switching cpus +info: Entering event queue @ 2414562654000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2415562654000. Starting simulation... +switching cpus +info: Entering event queue @ 2415562655000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2416562655000. Starting simulation... +switching cpus +info: Entering event queue @ 2416562810000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2417562810000. Starting simulation... +switching cpus +info: Entering event queue @ 2417562871000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2418562871000. Starting simulation... +switching cpus +info: Entering event queue @ 2418562872000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2419562872000. Starting simulation... +switching cpus +info: Entering event queue @ 2419562919000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2420562919000. Starting simulation... +switching cpus +info: Entering event queue @ 2420562986000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2421562986000. Starting simulation... +switching cpus +info: Entering event queue @ 2421562987000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2422562987000. Starting simulation... +info: Entering event queue @ 2423297572000. Starting simulation... +switching cpus +info: Entering event queue @ 2423297574000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2424297574000. Starting simulation... +switching cpus +info: Entering event queue @ 2424297699000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2425297699000. Starting simulation... +switching cpus +info: Entering event queue @ 2425297786000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2426297786000. Starting simulation... +switching cpus +info: Entering event queue @ 2426297856000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2427297856000. Starting simulation... +switching cpus +info: Entering event queue @ 2427298009000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2428298009000. Starting simulation... +switching cpus +info: Entering event queue @ 2428298043000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2429298043000. Starting simulation... +switching cpus +info: Entering event queue @ 2429298115000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2430298115000. Starting simulation... +switching cpus +info: Entering event queue @ 2430298116000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2431298116000. Starting simulation... +switching cpus +info: Entering event queue @ 2431298128000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2432298128000. Starting simulation... +switching cpus +info: Entering event queue @ 2432298154000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2433298154000. Starting simulation... +switching cpus +info: Entering event queue @ 2433298155000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2434298155000. Starting simulation... +switching cpus +info: Entering event queue @ 2434298209000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2435298209000. Starting simulation... +switching cpus +info: Entering event queue @ 2435298264000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2436298264000. Starting simulation... +switching cpus +info: Entering event queue @ 2436298295000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2437298295000. Starting simulation... +switching cpus +info: Entering event queue @ 2437298393000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2438298393000. Starting simulation... +switching cpus +info: Entering event queue @ 2438298535000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2439298535000. Starting simulation... +switching cpus +info: Entering event queue @ 2439298588000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2440298588000. Starting simulation... +switching cpus +info: Entering event queue @ 2440298715000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2441298715000. Starting simulation... +switching cpus +info: Entering event queue @ 2441298826000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2442298826000. Starting simulation... +switching cpus +info: Entering event queue @ 2442298827000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2443298827000. Starting simulation... +switching cpus +info: Entering event queue @ 2443298920000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2444298920000. Starting simulation... +switching cpus +info: Entering event queue @ 2444298968000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2445298968000. Starting simulation... +switching cpus +info: Entering event queue @ 2445298969000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2446298969000. Starting simulation... +switching cpus +info: Entering event queue @ 2446299109000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2447299109000. Starting simulation... +switching cpus +info: Entering event queue @ 2447299228000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2448299228000. Starting simulation... +switching cpus +info: Entering event queue @ 2448299344000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2449299344000. Starting simulation... +switching cpus +info: Entering event queue @ 2449299491000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2450299491000. Starting simulation... +switching cpus +info: Entering event queue @ 2450299553000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2451299553000. Starting simulation... +switching cpus +info: Entering event queue @ 2451299683000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2452299683000. Starting simulation... +switching cpus +info: Entering event queue @ 2452299768000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2453299768000. Starting simulation... +switching cpus +info: Entering event queue @ 2453299890000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2454299890000. Starting simulation... +switching cpus +info: Entering event queue @ 2454299959000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2455299959000. Starting simulation... +info: Entering event queue @ 2456033037000. Starting simulation... +switching cpus +info: Entering event queue @ 2456033039000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2457033039000. Starting simulation... +switching cpus +info: Entering event queue @ 2457033167000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2458033167000. Starting simulation... +switching cpus +info: Entering event queue @ 2458033184000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2459033184000. Starting simulation... +switching cpus +info: Entering event queue @ 2459033282000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2460033282000. Starting simulation... +switching cpus +info: Entering event queue @ 2460033316000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2461033316000. Starting simulation... +switching cpus +info: Entering event queue @ 2461033409000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2462033409000. Starting simulation... +switching cpus +info: Entering event queue @ 2462033511000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2463033511000. Starting simulation... +switching cpus +info: Entering event queue @ 2463033638000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2464033638000. Starting simulation... +switching cpus +info: Entering event queue @ 2464033758000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2465033758000. Starting simulation... +switching cpus +info: Entering event queue @ 2465033759000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2466033759000. Starting simulation... +switching cpus +info: Entering event queue @ 2466033904000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2467033904000. Starting simulation... +switching cpus +info: Entering event queue @ 2467033927000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2468033927000. Starting simulation... +switching cpus +info: Entering event queue @ 2468034035000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2469034035000. Starting simulation... +switching cpus +info: Entering event queue @ 2469034153000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2470034153000. Starting simulation... +switching cpus +info: Entering event queue @ 2470034198000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2471034198000. Starting simulation... +switching cpus +info: Entering event queue @ 2471034246000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2472034246000. Starting simulation... +switching cpus +info: Entering event queue @ 2472034313000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2473034313000. Starting simulation... +switching cpus +info: Entering event queue @ 2473034456000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2474034456000. Starting simulation... +switching cpus +info: Entering event queue @ 2474034604000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2475034604000. Starting simulation... +switching cpus +info: Entering event queue @ 2475034749000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2476034749000. Starting simulation... +switching cpus +info: Entering event queue @ 2476034794000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2477034794000. Starting simulation... +switching cpus +info: Entering event queue @ 2477034802000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2478034802000. Starting simulation... +switching cpus +info: Entering event queue @ 2478034803000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2479034803000. Starting simulation... +switching cpus +info: Entering event queue @ 2479034908000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2480034908000. Starting simulation... +switching cpus +info: Entering event queue @ 2480034957000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2481034957000. Starting simulation... +switching cpus +info: Entering event queue @ 2481034958000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2482034958000. Starting simulation... +switching cpus +info: Entering event queue @ 2482035090000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2483035090000. Starting simulation... +switching cpus +info: Entering event queue @ 2483035091000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2484035091000. Starting simulation... +switching cpus +info: Entering event queue @ 2484035144000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2485035144000. Starting simulation... +switching cpus +info: Entering event queue @ 2485035271000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2486035271000. Starting simulation... +info: Entering event queue @ 2486035296500. Starting simulation... +switching cpus +info: Entering event queue @ 2486035328001. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2487035328001. Starting simulation... +switching cpus +info: Entering event queue @ 2487035397000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2488035397000. Starting simulation... +info: Entering event queue @ 2488769554000. Starting simulation... +switching cpus +info: Entering event queue @ 2488769556000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2489769556000. Starting simulation... +switching cpus +info: Entering event queue @ 2489769557000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2490769557000. Starting simulation... +switching cpus +info: Entering event queue @ 2490769609000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2491769609000. Starting simulation... +switching cpus +info: Entering event queue @ 2491769729000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2492769729000. Starting simulation... +switching cpus +info: Entering event queue @ 2492769746000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2493769746000. Starting simulation... +switching cpus +info: Entering event queue @ 2493769816000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2494769816000. Starting simulation... +switching cpus +info: Entering event queue @ 2494769817000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2495769817000. Starting simulation... +switching cpus +info: Entering event queue @ 2495769874000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2496769874000. Starting simulation... +switching cpus +info: Entering event queue @ 2496769981000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2497769981000. Starting simulation... +switching cpus +info: Entering event queue @ 2497769982000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2498769982000. Starting simulation... +switching cpus +info: Entering event queue @ 2498770059000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2499770059000. Starting simulation... +switching cpus +info: Entering event queue @ 2499770067000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2500770067000. Starting simulation... +switching cpus +info: Entering event queue @ 2500770068000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2501770068000. Starting simulation... +switching cpus +info: Entering event queue @ 2501770143000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2502770143000. Starting simulation... +switching cpus +info: Entering event queue @ 2502770205000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2503770205000. Starting simulation... +switching cpus +info: Entering event queue @ 2503770206000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2504770206000. Starting simulation... +switching cpus +info: Entering event queue @ 2504770245000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2505770245000. Starting simulation... +switching cpus +info: Entering event queue @ 2505770337000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2506770337000. Starting simulation... +switching cpus +info: Entering event queue @ 2506770376000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2507770376000. Starting simulation... +switching cpus +info: Entering event queue @ 2507770429000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2508770429000. Starting simulation... +switching cpus +info: Entering event queue @ 2508770532000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2509770532000. Starting simulation... +switching cpus +info: Entering event queue @ 2509770565000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2510770565000. Starting simulation... +switching cpus +info: Entering event queue @ 2510770668000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2511770668000. Starting simulation... +switching cpus +info: Entering event queue @ 2511770737000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2512770737000. Starting simulation... +switching cpus +info: Entering event queue @ 2512770886000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2513770886000. Starting simulation... +switching cpus +info: Entering event queue @ 2513770887000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2514770887000. Starting simulation... +switching cpus +info: Entering event queue @ 2514771013000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2515771013000. Starting simulation... +switching cpus +info: Entering event queue @ 2515771025000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2516771025000. Starting simulation... +switching cpus +info: Entering event queue @ 2516771132000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2517771132000. Starting simulation... +switching cpus +info: Entering event queue @ 2517771133000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2518771133000. Starting simulation... +switching cpus +info: Entering event queue @ 2518771270000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2519771270000. Starting simulation... +switching cpus +info: Entering event queue @ 2519771364000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2520771364000. Starting simulation... +info: Entering event queue @ 2521505845000. Starting simulation... +switching cpus +info: Entering event queue @ 2521505847000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2522505847000. Starting simulation... +switching cpus +info: Entering event queue @ 2522505848000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2523505848000. Starting simulation... +switching cpus +info: Entering event queue @ 2523505849000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2524505849000. Starting simulation... +switching cpus +info: Entering event queue @ 2524505850000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2525505850000. Starting simulation... +switching cpus +info: Entering event queue @ 2525505953000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2526505953000. Starting simulation... +switching cpus +info: Entering event queue @ 2526505954000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2527505954000. Starting simulation... +info: Entering event queue @ 2527505964000. Starting simulation... +switching cpus +info: Entering event queue @ 2527505965500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2528505965500. Starting simulation... +switching cpus +info: Entering event queue @ 2528506085000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2529506085000. Starting simulation... +switching cpus +info: Entering event queue @ 2529506182000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2530506182000. Starting simulation... +switching cpus +info: Entering event queue @ 2530506241000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2531506241000. Starting simulation... +switching cpus +info: Entering event queue @ 2531506368000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2532506368000. Starting simulation... +switching cpus +info: Entering event queue @ 2532506400000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2533506400000. Starting simulation... +switching cpus +info: Entering event queue @ 2533506404000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2534506404000. Starting simulation... +switching cpus +info: Entering event queue @ 2534506527000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2535506527000. Starting simulation... +switching cpus +info: Entering event queue @ 2535506668000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2536506668000. Starting simulation... +switching cpus +info: Entering event queue @ 2536506816000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2537506816000. Starting simulation... +switching cpus +info: Entering event queue @ 2537506817000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2538506817000. Starting simulation... +switching cpus +info: Entering event queue @ 2538506962000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2539506962000. Starting simulation... +switching cpus +info: Entering event queue @ 2539507054000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2540507054000. Starting simulation... +switching cpus +info: Entering event queue @ 2540507055000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2541507055000. Starting simulation... +switching cpus +info: Entering event queue @ 2541507057000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2542507057000. Starting simulation... +switching cpus +info: Entering event queue @ 2542507129000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2543507129000. Starting simulation... +switching cpus +info: Entering event queue @ 2543507190000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2544507190000. Starting simulation... +switching cpus +info: Entering event queue @ 2544507208000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2545507208000. Starting simulation... +switching cpus +info: Entering event queue @ 2545507209000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2546507209000. Starting simulation... +switching cpus +info: Entering event queue @ 2546507292000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2547507292000. Starting simulation... +switching cpus +info: Entering event queue @ 2547507296000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2548507296000. Starting simulation... +switching cpus +info: Entering event queue @ 2548507297000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2549507297000. Starting simulation... +switching cpus +info: Entering event queue @ 2549507392000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2550507392000. Starting simulation... +switching cpus +info: Entering event queue @ 2550507429000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2551507429000. Starting simulation... +switching cpus +info: Entering event queue @ 2551507430000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2552507430000. Starting simulation... +switching cpus +info: Entering event queue @ 2552507449000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2553507449000. Starting simulation... +info: Entering event queue @ 2554241989000. Starting simulation... +switching cpus +info: Entering event queue @ 2554241991000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2555241991000. Starting simulation... +switching cpus +info: Entering event queue @ 2555241999500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2556241999500. Starting simulation... +switching cpus +info: Entering event queue @ 2556242000500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2557242000500. Starting simulation... +switching cpus +info: Entering event queue @ 2557242001500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2558242001500. Starting simulation... +switching cpus +info: Entering event queue @ 2558242077000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2559242077000. Starting simulation... +switching cpus +info: Entering event queue @ 2559242141000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2560242141000. Starting simulation... +switching cpus +info: Entering event queue @ 2560242242000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2561242242000. Starting simulation... +switching cpus +info: Entering event queue @ 2561242255000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2562242255000. Starting simulation... +switching cpus +info: Entering event queue @ 2562242375000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2563242375000. Starting simulation... +switching cpus +info: Entering event queue @ 2563242389000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2564242389000. Starting simulation... +switching cpus +info: Entering event queue @ 2564242391000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2565242391000. Starting simulation... +switching cpus +info: Entering event queue @ 2565242463000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2566242463000. Starting simulation... +switching cpus +info: Entering event queue @ 2566242542000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2567242542000. Starting simulation... +switching cpus +info: Entering event queue @ 2567242688000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2568242688000. Starting simulation... +switching cpus +info: Entering event queue @ 2568242730000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2569242730000. Starting simulation... +switching cpus +info: Entering event queue @ 2569242838000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2570242838000. Starting simulation... +switching cpus +info: Entering event queue @ 2570242940000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2571242940000. Starting simulation... +switching cpus +info: Entering event queue @ 2571242946000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2572242946000. Starting simulation... +switching cpus +info: Entering event queue @ 2572243030000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2573243030000. Starting simulation... +switching cpus +info: Entering event queue @ 2573243031000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2574243031000. Starting simulation... +switching cpus +info: Entering event queue @ 2574243077000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2575243077000. Starting simulation... +switching cpus +info: Entering event queue @ 2575243233000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2576243233000. Starting simulation... +switching cpus +info: Entering event queue @ 2576243261000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2577243261000. Starting simulation... +switching cpus +info: Entering event queue @ 2577243262000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2578243262000. Starting simulation... +switching cpus +info: Entering event queue @ 2578243340000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2579243340000. Starting simulation... +switching cpus +info: Entering event queue @ 2579243341000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2580243341000. Starting simulation... +switching cpus +info: Entering event queue @ 2580243342000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2581243342000. Starting simulation... +switching cpus +info: Entering event queue @ 2581243343000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2582243343000. Starting simulation... +switching cpus +info: Entering event queue @ 2582243344000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2583243344000. Starting simulation... +info: Entering event queue @ 2583243355000. Starting simulation... +switching cpus +info: Entering event queue @ 2583243358500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2584243358500. Starting simulation... +switching cpus +info: Entering event queue @ 2584243360500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2585243360500. Starting simulation... +switching cpus +info: Entering event queue @ 2585243362500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2586243362500. Starting simulation... +info: Entering event queue @ 2586996937000. Starting simulation... +switching cpus +info: Entering event queue @ 2586996939000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2587996939000. Starting simulation... +switching cpus +info: Entering event queue @ 2587996940000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2588996940000. Starting simulation... +switching cpus +info: Entering event queue @ 2588996941000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2589996941000. Starting simulation... +switching cpus +info: Entering event queue @ 2589996942000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2590996942000. Starting simulation... +switching cpus +info: Entering event queue @ 2590996944000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2591996944000. Starting simulation... +switching cpus +info: Entering event queue @ 2591996945000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2592996945000. Starting simulation... +switching cpus +info: Entering event queue @ 2592996946000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2593996946000. Starting simulation... +switching cpus +info: Entering event queue @ 2593996952500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2594996952500. Starting simulation... +switching cpus +info: Entering event queue @ 2594996953500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2595996953500. Starting simulation... +switching cpus +info: Entering event queue @ 2595996958500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2596996958500. Starting simulation... +switching cpus +info: Entering event queue @ 2596996959500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2597996959500. Starting simulation... +switching cpus +info: Entering event queue @ 2597996960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2598996960500. Starting simulation... +switching cpus +info: Entering event queue @ 2598996961500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2599996961500. Starting simulation... +switching cpus +info: Entering event queue @ 2599996963500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2600996963500. Starting simulation... +switching cpus +info: Entering event queue @ 2600996975000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2601996975000. Starting simulation... +switching cpus +info: Entering event queue @ 2601996976000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2602996976000. Starting simulation... +switching cpus +info: Entering event queue @ 2602997129000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2603997129000. Starting simulation... +switching cpus +info: Entering event queue @ 2603997243000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2604997243000. Starting simulation... +switching cpus +info: Entering event queue @ 2604997244500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2605997244500. Starting simulation... +switching cpus +info: Entering event queue @ 2605997245500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2606997245500. Starting simulation... +switching cpus +info: Entering event queue @ 2606997246500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2607997246500. Starting simulation... +info: Entering event queue @ 2607997257000. Starting simulation... +switching cpus +info: Entering event queue @ 2607997260500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2608997260500. Starting simulation... +switching cpus +info: Entering event queue @ 2608997261500. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt new file mode 100644 index 000000000..965d0e9db --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -0,0 +1,1067 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.609477 # Number of seconds simulated +sim_ticks 2609476867000 # Number of ticks simulated +final_tick 2609476867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 293996 # Simulator instruction rate (inst/s) +host_op_rate 374108 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12742678359 # Simulator tick rate (ticks/s) +host_mem_usage 397908 # Number of bytes of host memory used +host_seconds 204.78 # Real time elapsed on the host +sim_insts 60205243 # Number of instructions simulated +sim_ops 76610733 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 349152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4456460 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 356032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4588440 # Number of bytes read from this memory +system.physmem.bytes_read::total 132433668 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 349152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 356032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3672640 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1522768 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1493500 # Number of bytes written to this memory +system.physmem.bytes_written::total 6688908 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11658 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 69665 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 71715 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494028 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57385 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380692 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373375 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811452 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47014554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 133802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1707798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 136438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1758375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50751041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 133802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 136438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270240 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1407424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 583553 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 572337 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2563314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1407424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47014554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 133802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2291351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 136438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2330712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53314355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494028 # Total number of read requests seen +system.physmem.writeReqs 811452 # Total number of write requests seen +system.physmem.cpureqs 213833 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991617792 # Total number of bytes read from memory +system.physmem.bytesWritten 51932928 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132433668 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6688908 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4517 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 968202 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 968429 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967970 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 967933 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 967536 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967538 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 967708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 974536 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 968050 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 968032 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 968173 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 968196 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 968244 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 967963 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50183 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50348 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 49920 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50585 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50546 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50745 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 50919 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50958 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50981 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51015 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51209 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51186 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51259 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 2609472479500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 6673 # Categorize read packet sizes +system.physmem.readPktSize::3 15335424 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 151931 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 754067 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 57385 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4517 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 1117981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 962159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 962420 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 998543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2811240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2816443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5545406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 36112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 58787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 30559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 58397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 35453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 286738639625 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 365542479625 # Sum of mem lat for all requests +system.physmem.totBusLat 61976008000 # Total cycles spent in databus access +system.physmem.totBankLat 16827832000 # Total cycles spent in bank access +system.physmem.avgQLat 18506.43 # Average queueing delay per request +system.physmem.avgBankLat 1086.09 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 23592.52 # Average memory access latency +system.physmem.avgRdBW 380.01 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 19.90 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.75 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.56 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.50 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.14 # Average read queue length over time +system.physmem.avgWrQLen 1.25 # Average write queue length over time +system.physmem.readRowHits 15452119 # Number of row buffer hits during reads +system.physmem.writeRowHits 785190 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes +system.physmem.avgGap 160036.53 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 61820 # number of replacements +system.l2c.tagsinuse 50921.903557 # Cycle average of tags in use +system.l2c.total_refs 1697937 # Total number of references to valid blocks. +system.l2c.sampled_refs 127204 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.348142 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2557805301500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 37911.972595 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000184 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000639 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3578.783807 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2862.372936 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3416.906879 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3151.866517 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.578491 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.054608 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.043676 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.052138 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.048094 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.777007 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 9713 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3454 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 390514 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 186540 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9847 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3624 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 453502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 184024 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1241218 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596393 # number of Writeback hits +system.l2c.Writeback_hits::total 596393 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 9 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 55901 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58662 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114563 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9713 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3454 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 390514 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 242441 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 9847 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3624 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 453502 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 242686 # number of demand (read+write) hits +system.l2c.demand_hits::total 1355781 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9713 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3454 # number of overall hits +system.l2c.overall_hits::cpu0.inst 390514 # number of overall hits +system.l2c.overall_hits::cpu0.data 242441 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 9847 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3624 # number of overall hits +system.l2c.overall_hits::cpu1.inst 453502 # number of overall hits +system.l2c.overall_hits::cpu1.data 242686 # number of overall hits +system.l2c.overall_hits::total 1355781 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5042 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5096 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 5563 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4755 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20459 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1441 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1437 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2878 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 65351 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 67760 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133111 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5042 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 70447 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5563 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 72515 # number of demand (read+write) misses +system.l2c.demand_misses::total 153570 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 5042 # number of overall misses +system.l2c.overall_misses::cpu0.data 70447 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5563 # number of overall misses +system.l2c.overall_misses::cpu1.data 72515 # number of overall misses +system.l2c.overall_misses::total 153570 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 67500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 248651500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 257607500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 276465500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 252538000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1035399000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 157500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 296000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 453500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 2926690000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3113971500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6040661500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 67500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 248651500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3184297500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 276465500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3366509500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 7076060500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 67500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 248651500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3184297500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 276465500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3366509500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 7076060500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9714 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3456 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 395556 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 191636 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 9847 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3624 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 459065 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 188779 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1261677 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 596393 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 596393 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1458 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1446 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2904 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 121252 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 126422 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247674 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9714 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3456 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 395556 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 312888 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 9847 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3624 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 459065 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 315201 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1509351 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9714 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3456 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 395556 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 312888 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 9847 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3624 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 459065 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 315201 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1509351 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000103 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000579 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.012747 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.026592 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.012118 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.025188 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016216 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988340 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.993776 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991047 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.538968 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.535983 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.537444 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000103 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000579 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.012747 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.225151 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.012118 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.230060 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.101746 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000103 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000579 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.012747 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.225151 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.012118 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.230060 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.101746 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 33750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49316.045220 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 50550.922292 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49697.195758 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 53109.989485 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 50608.485263 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 109.299098 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 205.984690 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 157.574705 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44784.165506 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 45955.895809 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 45380.633456 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 49316.045220 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 45201.321561 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 49697.195758 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 46425.008619 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 46077.101647 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 49316.045220 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 45201.321561 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 49697.195758 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 46425.008619 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 46077.101647 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 57385 # number of writebacks +system.l2c.writebacks::total 57385 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 5042 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5096 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5563 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4755 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 20459 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1441 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1437 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2878 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 65351 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 67760 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133111 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 5042 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 70447 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5563 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 72515 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 153570 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 5042 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 70447 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 5563 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 72515 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 153570 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56002 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 42004 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 184664530 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 192314139 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 205852055 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 191753450 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 774682180 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14466412 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14371437 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 28837849 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2097339236 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2255705289 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4353044525 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 42004 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 184664530 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2289653375 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 205852055 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2447458739 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5127726705 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 42004 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 184664530 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2289653375 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 205852055 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2447458739 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5127726705 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 197466551 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84525516564 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82169986021 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166892969136 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4630774338 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 4531933372 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9162707710 # number of WriteReq MSHR uncacheable cycles +system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76004 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76004 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles +system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 197466551 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 89156290902 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 86701919393 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 176055676846 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000103 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000579 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.012747 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.026592 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012118 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025188 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016216 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988340 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.993776 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991047 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.538968 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.535983 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537444 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000103 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000579 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.012747 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.225151 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012118 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.230060 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101746 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000103 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000579 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.012747 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.225151 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012118 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.230060 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101746 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36625.253868 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 37738.253336 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 37003.784828 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40326.698212 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 37865.104844 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10039.147814 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10020.100417 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32093.452832 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33289.629413 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 32702.365131 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36625.253868 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32501.786804 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 37003.784828 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33751.068593 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 33390.158918 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36625.253868 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32501.786804 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 37003.784828 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33751.068593 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 33390.158918 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency +system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency +system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency +system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 7346324 # DTB read hits +system.cpu0.dtb.read_misses 6876 # DTB read misses +system.cpu0.dtb.write_hits 5393725 # DTB write hits +system.cpu0.dtb.write_misses 1788 # DTB write misses +system.cpu0.dtb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 739 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6380 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 236 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7353200 # DTB read accesses +system.cpu0.dtb.write_accesses 5395513 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 12740049 # DTB hits +system.cpu0.dtb.misses 8664 # DTB misses +system.cpu0.dtb.accesses 12748713 # DTB accesses +system.cpu0.itb.inst_hits 30077314 # ITB inst hits +system.cpu0.itb.inst_misses 3618 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 739 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2643 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 30080932 # ITB inst accesses +system.cpu0.itb.hits 30077314 # DTB hits +system.cpu0.itb.misses 3618 # DTB misses +system.cpu0.itb.accesses 30080932 # DTB accesses +system.cpu0.numCycles 2667978103 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 29443364 # Number of instructions committed +system.cpu0.committedOps 37313873 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33552683 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4308 # Number of float alu accesses +system.cpu0.num_func_calls 997498 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3872350 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33552683 # number of integer instructions +system.cpu0.num_fp_insts 4308 # number of float instructions +system.cpu0.num_int_register_reads 192457043 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36187608 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3214 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1096 # number of times the floating registers were written +system.cpu0.num_mem_refs 13317945 # number of memory refs +system.cpu0.num_load_insts 7675788 # Number of load instructions +system.cpu0.num_store_insts 5642157 # Number of store instructions +system.cpu0.num_idle_cycles 1511306252.685236 # Number of idle cycles +system.cpu0.num_busy_cycles 1156671850.314764 # Number of busy cycles +system.cpu0.not_idle_fraction 0.433539 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.566461 # Percentage of idle cycles +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 83014 # number of quiesce instructions executed +system.cpu0.icache.replacements 855749 # number of replacements +system.cpu0.icache.tagsinuse 510.984146 # Cycle average of tags in use +system.cpu0.icache.total_refs 60643040 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 856261 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 70.823078 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 18731806000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 165.100321 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 345.883825 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.322462 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.675554 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998016 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29681003 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30962037 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60643040 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29681003 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30962037 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60643040 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29681003 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30962037 # number of overall hits +system.cpu0.icache.overall_hits::total 60643040 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 396311 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 459950 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 856261 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 396311 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 459950 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 856261 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 396311 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 459950 # number of overall misses +system.cpu0.icache.overall_misses::total 856261 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5359552000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6210691500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11570243500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5359552000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6210691500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11570243500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5359552000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6210691500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11570243500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30077314 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 31421987 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61499301 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30077314 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 31421987 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61499301 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30077314 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 31421987 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61499301 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013176 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014638 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013923 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013176 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014638 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013923 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013176 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014638 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013923 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13523.601414 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13502.970975 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13512.519547 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13523.601414 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13502.970975 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13512.519547 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13523.601414 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13502.970975 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13512.519547 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 396311 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 459950 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 856261 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 396311 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 459950 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 856261 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 396311 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 459950 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 856261 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4566930000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5290791500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9857721500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4566930000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5290791500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9857721500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4566930000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5290791500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9857721500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 288141500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 288141500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 288141500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013176 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014638 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013923 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013176 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014638 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013923 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013176 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014638 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013923 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11523.601414 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11502.970975 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11512.519547 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11523.601414 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11502.970975 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11512.519547 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11523.601414 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11502.970975 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11512.519547 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 627576 # number of replacements +system.cpu0.dcache.tagsinuse 511.914984 # Cycle average of tags in use +system.cpu0.dcache.total_refs 23658480 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 628088 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.667461 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 460735000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 142.165809 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 369.749176 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.277668 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.722166 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.999834 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6448677 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6748535 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13197212 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4778089 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 5196213 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9974302 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 105697 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 130631 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236328 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 111573 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 136161 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247734 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11226766 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 11944748 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 23171514 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11226766 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 11944748 # number of overall hits +system.cpu0.dcache.overall_hits::total 23171514 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 185759 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 183249 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 369008 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 122710 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 127868 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250578 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5877 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5530 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11407 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 308469 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 311117 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 619586 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 308469 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 311117 # number of overall misses +system.cpu0.dcache.overall_misses::total 619586 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2627565000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2598558000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5226123000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3886745500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4117005000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8003750500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81831500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 73520000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 155351500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 6514310500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 6715563000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 13229873500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 6514310500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 6715563000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 13229873500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6634436 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6931784 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13566220 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4900799 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5324081 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10224880 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 111574 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 136161 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 247735 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 111573 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 136161 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247734 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11535235 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12255865 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23791100 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11535235 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12255865 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23791100 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027999 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026436 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027201 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025039 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024017 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.024507 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052674 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.040614 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046045 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026741 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025385 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026043 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026741 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025385 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026043 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14145.021237 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14180.475746 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14162.627911 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31674.236004 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32197.305033 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 31941.154052 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13924.025864 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13294.755877 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13618.962041 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21118.201505 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21585.329635 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 21352.763781 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21118.201505 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21585.329635 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21352.763781 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 596393 # number of writebacks +system.cpu0.dcache.writebacks::total 596393 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 185759 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 183249 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369008 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 122710 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 127868 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250578 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5877 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5530 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11407 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 308469 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 311117 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619586 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 308469 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 311117 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619586 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2256047000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2232060000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4488107000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3641325500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3861269000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7502594500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70077500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62460000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 132537500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5897372500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6093329000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11990701500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5897372500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6093329000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11990701500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92330241000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 89759244500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182089485500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9446181000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9255751500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18701932500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 101776422000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99014996000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200791418000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027999 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026436 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027201 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025039 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024017 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024507 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.052674 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040614 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046045 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026741 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025385 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026043 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026741 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025385 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026043 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12145.021237 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12180.475746 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12162.627911 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29674.236004 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30197.305033 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29941.154052 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11924.025864 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11294.755877 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11618.962041 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19118.201505 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19585.329635 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19352.763781 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19118.201505 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19585.329635 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19352.763781 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency +system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency +system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 7651718 # DTB read hits +system.cpu1.dtb.read_misses 6996 # DTB read misses +system.cpu1.dtb.write_hits 5838563 # DTB write hits +system.cpu1.dtb.write_misses 1808 # DTB write misses +system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 700 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6464 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 130 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 216 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7658714 # DTB read accesses +system.cpu1.dtb.write_accesses 5840371 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 13490281 # DTB hits +system.cpu1.dtb.misses 8804 # DTB misses +system.cpu1.dtb.accesses 13499085 # DTB accesses +system.cpu1.itb.inst_hits 31421987 # ITB inst hits +system.cpu1.itb.inst_misses 3616 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 700 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2808 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 31425603 # ITB inst accesses +system.cpu1.itb.hits 31421987 # DTB hits +system.cpu1.itb.misses 3616 # DTB misses +system.cpu1.itb.accesses 31425603 # DTB accesses +system.cpu1.numCycles 2550975631 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 30761879 # Number of instructions committed +system.cpu1.committedOps 39296860 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 35324832 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5961 # Number of float alu accesses +system.cpu1.num_func_calls 1142639 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4076383 # number of instructions that are conditional controls +system.cpu1.num_int_insts 35324832 # number of integer instructions +system.cpu1.num_fp_insts 5961 # number of float instructions +system.cpu1.num_int_register_reads 202353181 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37998347 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4279 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1684 # number of times the floating registers were written +system.cpu1.num_mem_refs 14079956 # number of memory refs +system.cpu1.num_load_insts 7986446 # Number of load instructions +system.cpu1.num_store_insts 6093510 # Number of store instructions +system.cpu1.num_idle_cycles 3341647478.137703 # Number of idle cycles +system.cpu1.num_busy_cycles -790671847.137703 # Number of busy cycles +system.cpu1.not_idle_fraction -0.309949 # Percentage of non-idle cycles +system.cpu1.idle_fraction 1.309949 # Percentage of idle cycles +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.iocache.replacements 0 # number of replacements +system.iocache.tagsinuse 0 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.avg_refs nan # Average number of references to valid blocks. +system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1128670778319 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1128670778319 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1128670778319 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1128670778319 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal Binary files differnew file mode 100644 index 000000000..8dd192b7e --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal |