diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 5162 |
1 files changed, 2583 insertions, 2579 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index a8e4ce345..9d627bc78 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.464182 # Number of seconds simulated -sim_ticks 47464181819000 # Number of ticks simulated -final_tick 47464181819000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.573912 # Number of seconds simulated +sim_ticks 47573912126000 # Number of ticks simulated +final_tick 47573912126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165089 # Simulator instruction rate (inst/s) -host_op_rate 194182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9130718670 # Simulator tick rate (ticks/s) -host_mem_usage 773696 # Number of bytes of host memory used -host_seconds 5198.30 # Real time elapsed on the host -sim_insts 858179266 # Number of instructions simulated -sim_ops 1009414094 # Number of ops (including micro ops) simulated +host_inst_rate 125865 # Simulator instruction rate (inst/s) +host_op_rate 148024 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6578075559 # Simulator tick rate (ticks/s) +host_mem_usage 723980 # Number of bytes of host memory used +host_seconds 7232.19 # Real time elapsed on the host +sim_insts 910282032 # Number of instructions simulated +sim_ops 1070541696 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 85568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 76544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 6880896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 37557256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10768960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 75264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 68480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3528576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 13557136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 8552832 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 436032 # Number of bytes read from this memory -system.physmem.bytes_read::total 81587544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 6880896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3528576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10409472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 64065088 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 153088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 136640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7678784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 42964232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 17895808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 154176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 129664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3679616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 16152336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 14975872 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 446400 # Number of bytes read from this memory +system.physmem.bytes_read::total 104366616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7678784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3679616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11358400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 83323200 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 64085672 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1196 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 107514 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 586845 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 168265 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1176 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1070 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 55134 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 211843 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 133638 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6813 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1274831 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1001017 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 83343784 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2392 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2135 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 119981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 671329 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 279622 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2409 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2026 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 57494 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 252393 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 233998 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6975 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1630754 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1301925 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1003591 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 144970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 791276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 226886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1586 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 74342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 285629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 180196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1718929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 144970 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 74342 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 219312 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1349757 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1304499 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 161407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 903105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 376169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 339521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 314792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2193778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 161407 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77345 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 238753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1751447 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1350190 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1349757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 144970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 791709 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 226886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 74342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 285629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 180196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3069119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1274831 # Number of read requests accepted -system.physmem.writeReqs 1003591 # Number of write requests accepted -system.physmem.readBursts 1274831 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1003591 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 81546816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 42368 # Total number of bytes read from write queue -system.physmem.bytesWritten 64084800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 81587544 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 64085672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 662 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1751880 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1751447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 161407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 903537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 376169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 339521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 314792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3945658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1630754 # Number of read requests accepted +system.physmem.writeReqs 1304499 # Number of write requests accepted +system.physmem.readBursts 1630754 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1304499 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 104327040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 41216 # Total number of bytes read from write queue +system.physmem.bytesWritten 83343168 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 104366616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 83343784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 644 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 221043 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 69298 # Per bank write bursts -system.physmem.perBankRdBursts::1 80196 # Per bank write bursts -system.physmem.perBankRdBursts::2 71590 # Per bank write bursts -system.physmem.perBankRdBursts::3 80518 # Per bank write bursts -system.physmem.perBankRdBursts::4 76240 # Per bank write bursts -system.physmem.perBankRdBursts::5 80771 # Per bank write bursts -system.physmem.perBankRdBursts::6 77164 # Per bank write bursts -system.physmem.perBankRdBursts::7 81418 # Per bank write bursts -system.physmem.perBankRdBursts::8 74880 # Per bank write bursts -system.physmem.perBankRdBursts::9 125815 # Per bank write bursts -system.physmem.perBankRdBursts::10 65333 # Per bank write bursts -system.physmem.perBankRdBursts::11 79047 # Per bank write bursts -system.physmem.perBankRdBursts::12 75605 # Per bank write bursts -system.physmem.perBankRdBursts::13 79656 # Per bank write bursts -system.physmem.perBankRdBursts::14 77605 # Per bank write bursts -system.physmem.perBankRdBursts::15 79033 # Per bank write bursts -system.physmem.perBankWrBursts::0 58028 # Per bank write bursts -system.physmem.perBankWrBursts::1 64393 # Per bank write bursts -system.physmem.perBankWrBursts::2 59641 # Per bank write bursts -system.physmem.perBankWrBursts::3 64677 # Per bank write bursts -system.physmem.perBankWrBursts::4 61513 # Per bank write bursts -system.physmem.perBankWrBursts::5 65147 # Per bank write bursts -system.physmem.perBankWrBursts::6 63058 # Per bank write bursts -system.physmem.perBankWrBursts::7 64825 # Per bank write bursts -system.physmem.perBankWrBursts::8 60547 # Per bank write bursts -system.physmem.perBankWrBursts::9 63081 # Per bank write bursts -system.physmem.perBankWrBursts::10 56749 # Per bank write bursts -system.physmem.perBankWrBursts::11 64053 # Per bank write bursts -system.physmem.perBankWrBursts::12 61964 # Per bank write bursts -system.physmem.perBankWrBursts::13 65797 # Per bank write bursts -system.physmem.perBankWrBursts::14 62586 # Per bank write bursts -system.physmem.perBankWrBursts::15 65266 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 221732 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 95834 # Per bank write bursts +system.physmem.perBankRdBursts::1 103052 # Per bank write bursts +system.physmem.perBankRdBursts::2 97330 # Per bank write bursts +system.physmem.perBankRdBursts::3 103782 # Per bank write bursts +system.physmem.perBankRdBursts::4 100129 # Per bank write bursts +system.physmem.perBankRdBursts::5 106515 # Per bank write bursts +system.physmem.perBankRdBursts::6 99389 # Per bank write bursts +system.physmem.perBankRdBursts::7 99717 # Per bank write bursts +system.physmem.perBankRdBursts::8 91352 # Per bank write bursts +system.physmem.perBankRdBursts::9 148680 # Per bank write bursts +system.physmem.perBankRdBursts::10 90509 # Per bank write bursts +system.physmem.perBankRdBursts::11 96337 # Per bank write bursts +system.physmem.perBankRdBursts::12 96747 # Per bank write bursts +system.physmem.perBankRdBursts::13 106196 # Per bank write bursts +system.physmem.perBankRdBursts::14 95843 # Per bank write bursts +system.physmem.perBankRdBursts::15 98698 # Per bank write bursts +system.physmem.perBankWrBursts::0 79474 # Per bank write bursts +system.physmem.perBankWrBursts::1 83004 # Per bank write bursts +system.physmem.perBankWrBursts::2 79696 # Per bank write bursts +system.physmem.perBankWrBursts::3 83932 # Per bank write bursts +system.physmem.perBankWrBursts::4 80263 # Per bank write bursts +system.physmem.perBankWrBursts::5 85902 # Per bank write bursts +system.physmem.perBankWrBursts::6 82233 # Per bank write bursts +system.physmem.perBankWrBursts::7 81457 # Per bank write bursts +system.physmem.perBankWrBursts::8 76873 # Per bank write bursts +system.physmem.perBankWrBursts::9 82502 # Per bank write bursts +system.physmem.perBankWrBursts::10 77306 # Per bank write bursts +system.physmem.perBankWrBursts::11 81622 # Per bank write bursts +system.physmem.perBankWrBursts::12 79893 # Per bank write bursts +system.physmem.perBankWrBursts::13 86888 # Per bank write bursts +system.physmem.perBankWrBursts::14 78601 # Per bank write bursts +system.physmem.perBankWrBursts::15 82591 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 59 # Number of times write queue was full causing retry -system.physmem.totGap 47464179840500 # Total gap between requests +system.physmem.numWrRetry 61 # Number of times write queue was full causing retry +system.physmem.totGap 47573910147500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1274801 # Read request sizes (log2) +system.physmem.readPktSize::6 1630724 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1001017 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 816238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 315854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23000 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 19787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 18192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 16305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 14624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 12016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1301925 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 998903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 383381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 53687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 39143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 33585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 31320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 28483 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 22337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 5097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1220 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -188,166 +188,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 15348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 37266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 53574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 55971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 59005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 62838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 63556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 68208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 65188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 65181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 70319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 65705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 58334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 193 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 760858 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 191.403705 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 116.807820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 249.999790 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 448904 59.00% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 151841 19.96% 78.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50675 6.66% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27026 3.55% 89.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 17061 2.24% 91.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11068 1.45% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8074 1.06% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8214 1.08% 95.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 37995 4.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 760858 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 56148 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.692705 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 368.089974 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 56145 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 18448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 20938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 64725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 69469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 74724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 78159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 81831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 83061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 84591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 90322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 87643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 87918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 95292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 88789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 82985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 78170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 169 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1008532 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 186.082044 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 114.846498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 242.592795 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 603416 59.83% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 198742 19.71% 79.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 66381 6.58% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35101 3.48% 89.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23988 2.38% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15328 1.52% 93.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10269 1.02% 94.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9973 0.99% 95.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 45334 4.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1008532 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 74360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.921678 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 319.874978 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 74357 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 56148 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 56148 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.833672 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.227387 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.381246 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 52715 93.89% 93.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1304 2.32% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 213 0.38% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 294 0.52% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 73 0.13% 97.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 309 0.55% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 189 0.34% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 132 0.24% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 76 0.14% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 103 0.18% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 49 0.09% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 61 0.11% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 401 0.71% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 39 0.07% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 42 0.07% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 82 0.15% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 14 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 25 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 56148 # Writes before turning the bus around for reads -system.physmem.totQLat 34002300770 # Total ticks spent queuing -system.physmem.totMemAccLat 57892969520 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6370845000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26685.86 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 74360 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 74360 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.512601 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.043743 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.433062 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 70224 94.44% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1905 2.56% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 313 0.42% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 309 0.42% 97.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 95 0.13% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 310 0.42% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 189 0.25% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 82 0.11% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 85 0.11% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 110 0.15% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 46 0.06% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 59 0.08% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 410 0.55% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 26 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 24 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 107 0.14% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 28 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 74360 # Writes before turning the bus around for reads +system.physmem.totQLat 52515283986 # Total ticks spent queuing +system.physmem.totMemAccLat 83079846486 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8150550000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32215.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45435.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 50965.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.19 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.75 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.75 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.67 # Average write queue length when enqueuing -system.physmem.readRowHits 1026298 # Number of row buffer hits during reads -system.physmem.writeRowHits 488335 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 48.77 # Row buffer hit rate for writes -system.physmem.avgGap 20832040.70 # Average gap between requests -system.physmem.pageHitRate 66.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2867901120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1564827000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4814050800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3248307360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3100129378320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1185321114675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27438751602000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31736697181275 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.645246 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45646225461150 # Time in different power states -system.physmem_0.memoryStateTime::REF 1584933220000 # Time in different power states +system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing +system.physmem.readRowHits 1305984 # Number of row buffer hits during reads +system.physmem.writeRowHits 617830 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.44 # Row buffer hit rate for writes +system.physmem.avgGap 16207771.58 # Average gap between requests +system.physmem.pageHitRate 65.61 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3848576760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2099917875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6284834400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4250627280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3107296514400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1215004983300 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27478552093500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31817337547515 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.798037 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45712218150079 # Time in different power states +system.physmem_0.memoryStateTime::REF 1588597400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 233019608850 # Time in different power states +system.physmem_0.memoryStateTime::ACT 273094361171 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2884185360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1573712250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5124397200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3240278640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3100129378320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1191686941080 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27433167543750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31737806436600 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.668617 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45636858751692 # Time in different power states -system.physmem_1.memoryStateTime::REF 1584933220000 # Time in different power states +system.physmem_1.actEnergy 3775925160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2060276625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6429961200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4187868480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3107296514400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1217449094850 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27476408136000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31817607776715 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.803717 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45708592383178 # Time in different power states +system.physmem_1.memoryStateTime::REF 1588597400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 242386318308 # Time in different power states +system.physmem_1.memoryStateTime::ACT 276721037822 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -378,18 +374,18 @@ system.realview.nvmem.bw_total::total 28 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 135703894 # Number of BP lookups -system.cpu0.branchPred.condPredicted 95425291 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6312333 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 100672877 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 73270894 # Number of BTB hits +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 141076080 # Number of BP lookups +system.cpu0.branchPred.condPredicted 100250771 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6354710 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 105662880 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 77608899 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.781166 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16275299 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1070570 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.449540 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 16417680 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1072595 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -420,62 +416,63 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 277006 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 277006 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8797 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76685 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 277006 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 277006 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 277006 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 85482 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 21392.901430 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 19388.852647 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 17614.753194 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 84631 99.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 172 0.20% 99.21% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 584 0.68% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 16 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 33 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 27 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 302583 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 302583 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11677 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91984 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 302583 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 302583 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 302583 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 103661 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22488.718033 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 20252.846239 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 20697.815033 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 102356 98.74% 98.74% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 167 0.16% 98.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 962 0.93% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 38 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 45 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 22 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 45 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 85482 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 103661 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples -910187592 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 -910187592 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total -910187592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 76685 89.71% 89.71% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 8797 10.29% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 85482 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 277006 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 91984 88.74% 88.74% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11677 11.26% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 103661 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302583 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 277006 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85482 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302583 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 103661 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85482 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 362488 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 103661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 406244 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 88941283 # DTB read hits -system.cpu0.dtb.read_misses 229899 # DTB read misses -system.cpu0.dtb.write_hits 77314134 # DTB write hits -system.cpu0.dtb.write_misses 47107 # DTB write misses +system.cpu0.dtb.read_hits 91224751 # DTB read hits +system.cpu0.dtb.read_misses 252123 # DTB read misses +system.cpu0.dtb.write_hits 79969156 # DTB write hits +system.cpu0.dtb.write_misses 50460 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37002 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 982 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8335 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 39295 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 989 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 11229 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10385 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 89171182 # DTB read accesses -system.cpu0.dtb.write_accesses 77361241 # DTB write accesses +system.cpu0.dtb.perms_faults 11007 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91476874 # DTB read accesses +system.cpu0.dtb.write_accesses 80019616 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 166255417 # DTB hits -system.cpu0.dtb.misses 277006 # DTB misses -system.cpu0.dtb.accesses 166532423 # DTB accesses +system.cpu0.dtb.hits 171193907 # DTB hits +system.cpu0.dtb.misses 302583 # DTB misses +system.cpu0.dtb.accesses 171496490 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -505,192 +502,187 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 67964 # Table walker walks requested -system.cpu0.itb.walker.walksLong 67964 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 522 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55569 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 67964 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 67964 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 67964 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 56091 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 23783.423366 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21371.413212 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 19530.956784 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 52347 93.33% 93.33% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 2944 5.25% 98.57% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 5 0.01% 98.58% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.58% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 475 0.85% 99.43% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 248 0.44% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 15 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 9 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 29 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 56091 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 69790 # Table walker walks requested +system.cpu0.itb.walker.walksLong 69790 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 704 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58261 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 69790 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 69790 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 69790 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 58965 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25666.514034 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 22346.910344 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 25122.368024 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 57570 97.63% 97.63% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 8 0.01% 97.65% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 1255 2.13% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 40 0.07% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 50 0.08% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 25 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 12 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 58965 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -911302092 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -911302092 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -911302092 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 55569 99.07% 99.07% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 522 0.93% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 56091 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 58261 98.81% 98.81% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 704 1.19% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 58965 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 67964 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 67964 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 69790 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 69790 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56091 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56091 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 124055 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 243132835 # ITB inst hits -system.cpu0.itb.inst_misses 67964 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58965 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58965 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 128755 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 253370493 # ITB inst hits +system.cpu0.itb.inst_misses 69790 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26811 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 28357 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 210881 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 216294 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 243200799 # ITB inst accesses -system.cpu0.itb.hits 243132835 # DTB hits -system.cpu0.itb.misses 67964 # DTB misses -system.cpu0.itb.accesses 243200799 # DTB accesses -system.cpu0.numCycles 1024570142 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 253440283 # ITB inst accesses +system.cpu0.itb.hits 253370493 # DTB hits +system.cpu0.itb.misses 69790 # DTB misses +system.cpu0.itb.accesses 253440283 # DTB accesses +system.cpu0.numCycles 1081338531 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 453671847 # Number of instructions committed -system.cpu0.committedOps 532972040 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 44332709 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 5117 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93904749601 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.258395 # CPI: cycles per instruction -system.cpu0.ipc 0.442792 # IPC: instructions per cycle +system.cpu0.committedInsts 467223626 # Number of instructions committed +system.cpu0.committedOps 548903732 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 48040966 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 5433 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 94067362325 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.314392 # CPI: cycles per instruction +system.cpu0.ipc 0.432079 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6224 # number of quiesce instructions executed -system.cpu0.tickCycles 727182617 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 297387525 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5606815 # number of replacements -system.cpu0.dcache.tags.tagsinuse 475.898466 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 157812679 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5607327 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.144012 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 5510 # number of quiesce instructions executed +system.cpu0.tickCycles 755200178 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 326138353 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5943709 # number of replacements +system.cpu0.dcache.tags.tagsinuse 508.631098 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 162232873 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5944219 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.292546 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7690193000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.898466 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929489 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.929489 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 335393662 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 335393662 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 81544003 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 81544003 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 71771704 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 71771704 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 253031 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 253031 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 130003 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 130003 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1818235 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1818235 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1799115 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1799115 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153315707 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153315707 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153568738 # number of overall hits -system.cpu0.dcache.overall_hits::total 153568738 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3470214 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3470214 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2296821 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2296821 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 622517 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 622517 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 787681 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 787681 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 168627 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 168627 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 185724 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 185724 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5767035 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5767035 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6389552 # number of overall misses -system.cpu0.dcache.overall_misses::total 6389552 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57404903000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 57404903000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 53218814500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 53218814500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 70624877500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 70624877500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2615349000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2615349000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4471340500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4471340500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4645500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4645500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 110623717500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 110623717500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 110623717500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 110623717500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 85014217 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 85014217 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74068525 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74068525 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 875548 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 875548 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 917684 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 917684 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1986862 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1986862 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1984839 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1984839 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 159082742 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 159082742 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 159958290 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 159958290 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040819 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.040819 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031009 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.031009 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.711003 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.711003 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.858336 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.858336 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084871 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084871 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.093571 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.093571 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036252 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.036252 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039945 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.039945 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16542.179531 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16542.179531 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23170.640855 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23170.640855 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 89661.776150 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 89661.776150 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15509.669270 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15509.669270 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24075.189529 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24075.189529 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.631098 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993420 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.993420 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 345517845 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 345517845 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 83485003 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 83485003 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 74196086 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 74196086 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 250296 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 250296 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 125849 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 125849 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1837182 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1837182 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1810329 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1810329 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 157681089 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 157681089 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 157931385 # number of overall hits +system.cpu0.dcache.overall_hits::total 157931385 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3676950 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3676950 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2497111 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2497111 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 700297 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 700297 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 789920 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 789920 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172643 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 172643 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197460 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 197460 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 6174061 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6174061 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6874358 # number of overall misses +system.cpu0.dcache.overall_misses::total 6874358 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 65602264000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 65602264000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59773944000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 59773944000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 75379073500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 75379073500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2981608500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2981608500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4714245500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4714245500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5404500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5404500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 125376208000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 125376208000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 125376208000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 125376208000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 87161953 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 87161953 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 76693197 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 76693197 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 950593 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 950593 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 915769 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 915769 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2009825 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2009825 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2007789 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2007789 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 163855150 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 163855150 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 164805743 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 164805743 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.042185 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.042185 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032560 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.032560 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.736695 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.736695 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.862576 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.862576 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085900 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085900 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098347 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098347 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037680 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.037680 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041712 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.041712 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17841.489278 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 17841.489278 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23937.239474 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23937.239474 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 95426.212148 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 95426.212148 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17270.370070 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17270.370070 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23874.432797 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23874.432797 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19182.078399 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19182.078399 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17313.219691 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17313.219691 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20306.927321 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20306.927321 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18238.242466 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18238.242466 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -699,161 +691,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3758761 # number of writebacks -system.cpu0.dcache.writebacks::total 3758761 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 423304 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 423304 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 954060 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 954060 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 67 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 67 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43006 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43006 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 59 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1377364 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1377364 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1377364 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1377364 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3046910 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3046910 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1342761 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1342761 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 616851 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 616851 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 787614 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 787614 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125621 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125621 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 185665 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 185665 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4389671 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4389671 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5006522 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5006522 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14625 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14625 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15482 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15482 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30107 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30107 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45015119500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45015119500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30226463500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30226463500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15766385500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15766385500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 69831148500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 69831148500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1724289500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1724289500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4281874000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4281874000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4478500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4478500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 75241583000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 75241583000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 91007968500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 91007968500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2444404000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2444404000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2533371000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2533371000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4977775000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4977775000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035840 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035840 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018129 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018129 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.704531 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.704531 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.858263 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.858263 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063226 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063226 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093542 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093542 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027594 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027594 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031299 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031299 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14774.023355 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14774.023355 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22510.680233 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22510.680233 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25559.471412 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25559.471412 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 88661.639458 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 88661.639458 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13726.124613 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13726.124613 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23062.365012 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23062.365012 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3994886 # number of writebacks +system.cpu0.dcache.writebacks::total 3994886 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 471328 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 471328 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1040644 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1040644 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 61 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 61 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43748 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43748 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 50 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 50 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1511972 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1511972 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1511972 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1511972 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3205622 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3205622 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1456467 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1456467 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 694705 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 694705 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 789859 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 789859 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128895 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128895 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197410 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 197410 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4662089 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4662089 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5356794 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5356794 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14687 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14687 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15563 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15563 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30250 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30250 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 51339121000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 51339121000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 33967610000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33967610000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18528677500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18528677500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 74583001500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 74583001500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1907396500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1907396500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4514361000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4514361000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5031000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5031000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 85306731000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 85306731000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103835408500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 103835408500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2448224000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2448224000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2535196500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2535196500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4983420500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4983420500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036778 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036778 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018991 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018991 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.730812 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.730812 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.862509 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.862509 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064132 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064132 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098322 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098322 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028453 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028453 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032504 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032504 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16015.338365 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16015.338365 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 23321.922158 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 23321.922158 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26671.288533 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26671.288533 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 94425.715856 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 94425.715856 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14798.064316 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14798.064316 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22867.944886 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22867.944886 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17140.597325 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17140.597325 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18177.882470 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18177.882470 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167138.735043 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167138.735043 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163633.316109 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163633.316109 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165336.134454 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165336.134454 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18297.962780 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18297.962780 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19383.871864 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19383.871864 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166693.266154 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166693.266154 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162898.959070 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162898.959070 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 164741.173554 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 164741.173554 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 9688574 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.890007 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 233226662 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9689086 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.071069 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 9691826 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.890260 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 243455405 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9692338 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 25.118336 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 41394292000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890007 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999785 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999785 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890260 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999786 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999786 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 495520584 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 495520584 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 233226662 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 233226662 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 233226662 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 233226662 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 233226662 # number of overall hits -system.cpu0.icache.overall_hits::total 233226662 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9689087 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9689087 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9689087 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9689087 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9689087 # number of overall misses -system.cpu0.icache.overall_misses::total 9689087 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 100299166000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 100299166000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 100299166000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 100299166000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 100299166000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 100299166000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 242915749 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 242915749 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 242915749 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 242915749 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 242915749 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 242915749 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039887 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.039887 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039887 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.039887 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039887 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.039887 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10351.766477 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10351.766477 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10351.766477 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10351.766477 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10351.766477 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10351.766477 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 515987824 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 515987824 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 243455405 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 243455405 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 243455405 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 243455405 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 243455405 # number of overall hits +system.cpu0.icache.overall_hits::total 243455405 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9692338 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9692338 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9692338 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9692338 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9692338 # number of overall misses +system.cpu0.icache.overall_misses::total 9692338 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 102847685000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 102847685000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 102847685000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 102847685000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 102847685000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 102847685000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 253147743 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 253147743 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 253147743 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 253147743 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 253147743 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 253147743 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038287 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.038287 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038287 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.038287 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038287 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.038287 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10611.235906 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10611.235906 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10611.235906 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10611.235906 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10611.235906 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10611.235906 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -862,252 +854,256 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9689087 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9689087 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9689087 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9689087 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9689087 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9689087 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9692338 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9692338 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9692338 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9692338 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9692338 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9692338 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95454623000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 95454623000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 95454623000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 95454623000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 95454623000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 95454623000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 98001516000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 98001516000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 98001516000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 98001516000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 98001516000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 98001516000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7413401000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7413401000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039887 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.039887 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.039887 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9851.766529 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9851.766529 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9851.766529 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038287 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038287 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038287 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.038287 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038287 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.038287 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10111.235906 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10111.235906 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10111.235906 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10111.235906 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10111.235906 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10111.235906 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141723.240743 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141723.240743 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7463777 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7463951 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 154 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7930582 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7930908 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 287 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1020305 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2664787 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15957.113648 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 26864509 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2680682 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.021520 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1050332 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2927796 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16250.045097 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 27328553 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2943246 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 9.285175 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 38485430000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6872.215886 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 83.268968 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 86.677569 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4373.710312 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3617.876682 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 923.364231 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.419447 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005082 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005290 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.266950 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.220818 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056358 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.973945 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1328 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 58 # 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mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079737 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257800 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257800 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.729915 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.729915 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.249324 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.132046 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.249324 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.215996 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.215996 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.084825 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.266802 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.266802 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.750042 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.750042 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022130 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049197 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.254979 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.139080 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022130 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049197 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.254979 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.175963 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33854.016150 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49505.517456 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49505.517456 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35031.209739 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35031.209739 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19034.642232 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19034.642232 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 2006500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2006500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56469.039844 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56469.039844 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29917.465826 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33190.748353 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33190.748353 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 110987.907308 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 110987.907308 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37902.087304 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34804.523098 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37902.087304 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49505.517456 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38473.617152 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187852 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44339.119667 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 70126.299396 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35057.911511 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35057.911511 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18692.313416 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18692.313416 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 571562.375000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 571562.375000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60685.103586 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60685.103586 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31211.654222 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36995.024259 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36995.024259 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 115692.637341 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 115692.637341 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41665.193013 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37753.359129 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41665.193013 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46158.314401 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159132.888889 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139275.218872 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 156131.927400 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 156131.927400 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158689.861783 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139196.474416 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155397.770353 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155397.770353 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157589.696748 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 142441.783149 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 156996.148760 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 142250.542037 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 31422927 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16035788 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2283 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 525852 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 525836 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 16 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 867706 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14437095 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15482 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15482 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 5117037 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 13614128 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 885080 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 435794 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 332763 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 479351 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 73 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1199260 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1131949 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9689087 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4838943 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 791881 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 786200 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29170184 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18058991 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 372221 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1095581 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 48696977 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 623449216 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 561436611 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1353296 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3982960 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1190222083 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6103291 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 37789516 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.022593 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.148604 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 32152230 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16420555 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 569005 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 568969 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 36 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 939547 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14756064 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 15563 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 15563 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 5525670 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 13869690 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1023479 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 455350 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 356742 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 509038 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1302016 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1231079 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9692338 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5147566 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 792720 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 788675 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29179671 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19139148 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 387023 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1234112 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 49939954 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 623657344 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 598500446 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1429032 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4559656 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1228146478 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6651761 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 39123003 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.023394 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.151159 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 36935768 97.74% 97.74% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 853732 2.26% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 16 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 38207781 97.66% 97.66% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 915186 2.34% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 36 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 37789516 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 19757899995 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 39123003 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 20385491499 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 181829197 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 189810874 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14614802569 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14619906616 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7994552968 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8517245437 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 203085447 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 208413461 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 597764892 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 664225858 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 123013748 # Number of BP lookups -system.cpu1.branchPred.condPredicted 87245709 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5806283 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 91467062 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 66791634 # Number of BTB hits +system.cpu1.branchPred.lookups 135994038 # Number of BP lookups +system.cpu1.branchPred.condPredicted 97681271 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5923294 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 101767942 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 74881085 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.022608 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 14491018 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 994593 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.580229 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15572056 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1048784 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1385,62 +1383,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 261280 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 261280 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8108 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 72332 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 261280 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 261280 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 261280 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 80440 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 21205.221283 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 19053.776737 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 17699.176778 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 79639 99.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 177 0.22% 99.22% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 525 0.65% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 29 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 26 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 80440 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 278179 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 278179 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9856 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80934 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 278179 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 278179 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 278179 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 90790 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 21983.114880 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 19433.562361 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 21494.492882 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 89574 98.66% 98.66% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 162 0.18% 98.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 899 0.99% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.02% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 47 0.05% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 21 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 36 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 16 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 90790 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1613488760 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1613488760 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1613488760 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 72332 89.92% 89.92% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8108 10.08% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 80440 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261280 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 80934 89.14% 89.14% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9856 10.86% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 90790 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 278179 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261280 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 80440 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 278179 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90790 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 80440 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 341720 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90790 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 368969 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 79147380 # DTB read hits -system.cpu1.dtb.read_misses 216729 # DTB read misses -system.cpu1.dtb.write_hits 70165250 # DTB write hits -system.cpu1.dtb.write_misses 44551 # DTB write misses +system.cpu1.dtb.read_hits 86408994 # DTB read hits +system.cpu1.dtb.read_misses 229031 # DTB read misses +system.cpu1.dtb.write_hits 76265809 # DTB write hits +system.cpu1.dtb.write_misses 49148 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 35978 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1622 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8536 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36480 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1565 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7972 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11275 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 79364109 # DTB read accesses -system.cpu1.dtb.write_accesses 70209801 # DTB write accesses +system.cpu1.dtb.perms_faults 11612 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 86638025 # DTB read accesses +system.cpu1.dtb.write_accesses 76314957 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 149312630 # DTB hits -system.cpu1.dtb.misses 261280 # DTB misses -system.cpu1.dtb.accesses 149573910 # DTB accesses +system.cpu1.dtb.hits 162674803 # DTB hits +system.cpu1.dtb.misses 278179 # DTB misses +system.cpu1.dtb.accesses 162952982 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1470,187 +1468,189 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 64423 # Table walker walks requested -system.cpu1.itb.walker.walksLong 64423 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 649 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55396 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 64423 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 64423 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 64423 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 56045 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 23900.053528 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21358.293391 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 20280.389435 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 55251 98.58% 98.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 6 0.01% 98.59% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 707 1.26% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 21 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 35 0.06% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 56045 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 61280 # Table walker walks requested +system.cpu1.itb.walker.walksLong 61280 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 546 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52744 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 61280 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 61280 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 61280 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 53290 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25110.649278 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 21594.032296 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 25562.060343 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 52075 97.72% 97.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 7 0.01% 97.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1075 2.02% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 37 0.07% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 53 0.10% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 27 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 12 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 53290 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1612594260 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1612594260 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1612594260 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 55396 98.84% 98.84% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 649 1.16% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 56045 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 52744 98.98% 98.98% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 546 1.02% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 53290 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64423 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64423 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61280 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61280 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56045 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56045 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 120468 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 219650463 # ITB inst hits -system.cpu1.itb.inst_misses 64423 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53290 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53290 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 114570 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 242169117 # ITB inst hits +system.cpu1.itb.inst_misses 61280 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25468 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25722 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 193837 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 205735 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 219714886 # ITB inst accesses -system.cpu1.itb.hits 219650463 # DTB hits -system.cpu1.itb.misses 64423 # DTB misses -system.cpu1.itb.accesses 219714886 # DTB accesses -system.cpu1.numCycles 870330668 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 242230397 # ITB inst accesses +system.cpu1.itb.hits 242169117 # DTB hits +system.cpu1.itb.misses 61280 # DTB misses +system.cpu1.itb.accesses 242230397 # DTB accesses +system.cpu1.numCycles 953928196 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 404507419 # Number of instructions committed -system.cpu1.committedOps 476442054 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 42651509 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4585 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 94059012808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.151581 # CPI: cycles per instruction -system.cpu1.ipc 0.464774 # IPC: instructions per cycle +system.cpu1.committedInsts 443058406 # Number of instructions committed +system.cpu1.committedOps 521637964 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 48259182 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4720 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 94194636881 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.153053 # CPI: cycles per instruction +system.cpu1.ipc 0.464457 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 15419 # number of quiesce instructions executed -system.cpu1.tickCycles 657243105 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 213087563 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 4754677 # number of replacements -system.cpu1.dcache.tags.tagsinuse 457.418304 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 141978837 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4755187 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.857677 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 13665 # number of quiesce instructions executed +system.cpu1.tickCycles 720990302 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 232937894 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5271409 # number of replacements +system.cpu1.dcache.tags.tagsinuse 430.049497 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 154587010 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5271921 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.322710 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8389845325000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.418304 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893395 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.893395 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 300818421 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 300818421 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 72673299 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 72673299 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 65442912 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 65442912 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235828 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 235828 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 186972 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 186972 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1517500 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1517500 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1485570 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1485570 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 138116211 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 138116211 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 138352039 # number of overall hits -system.cpu1.dcache.overall_hits::total 138352039 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3009807 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3009807 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2062772 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2062772 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 570106 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 570106 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 466745 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 466745 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 151961 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 151961 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 182125 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 182125 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5072579 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5072579 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5642685 # number of overall misses -system.cpu1.dcache.overall_misses::total 5642685 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 47626322500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 47626322500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 41378134500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 41378134500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 19926390000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 19926390000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2395499000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2395499000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4359715500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4359715500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5890500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5890500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 89004457000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 89004457000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 89004457000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 89004457000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 75683106 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 75683106 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 67505684 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 67505684 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 805934 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 805934 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 653717 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 653717 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1669461 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1669461 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1667695 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1667695 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 143188790 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 143188790 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 143994724 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 143994724 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039769 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.039769 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030557 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030557 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.707385 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.707385 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.713986 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.713986 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091024 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091024 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109208 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109208 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035426 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035426 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039187 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.039187 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15823.713115 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15823.713115 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20059.480398 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20059.480398 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42692.240945 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42692.240945 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15763.906529 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15763.906529 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23938.039808 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23938.039808 # average StoreCondReq miss latency +system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.049497 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.839940 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.839940 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 327906694 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 327906694 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 79069141 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 79069141 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 70951579 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 70951579 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 254478 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 254478 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 200049 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 200049 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1835496 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1835496 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1797284 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1797284 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 150020720 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 150020720 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 150275198 # number of overall hits +system.cpu1.dcache.overall_hits::total 150275198 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3348164 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3348164 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2321727 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2321727 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 675333 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 675333 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 453842 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 453842 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 163069 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 163069 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199393 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 199393 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5669891 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5669891 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6345224 # number of overall misses +system.cpu1.dcache.overall_misses::total 6345224 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55281073500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 55281073500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 48428743000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 48428743000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20617335000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 20617335000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2629405000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2629405000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4686368500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4686368500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4186500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4186500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 103709816500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 103709816500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 103709816500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 103709816500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 82417305 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 82417305 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 73273306 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 73273306 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 929811 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 929811 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 653891 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 653891 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1998565 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1998565 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1996677 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1996677 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 155690611 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 155690611 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 156620422 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 156620422 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040625 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.040625 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031686 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.031686 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.726312 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.726312 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.694064 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.694064 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081593 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081593 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099862 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099862 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036418 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.036418 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040513 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.040513 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16510.861923 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16510.861923 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20858.930873 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20858.930873 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45428.442057 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45428.442057 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16124.493313 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16124.493313 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23503.174635 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23503.174635 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17546.194352 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17546.194352 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15773.422936 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15773.422936 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18291.324560 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18291.324560 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16344.547726 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16344.547726 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1659,161 +1659,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3093987 # number of writebacks -system.cpu1.dcache.writebacks::total 3093987 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 330751 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 330751 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 852033 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 852033 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 101 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 101 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39295 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39295 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 47 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 47 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1182784 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1182784 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1182784 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1182784 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2679056 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2679056 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1210739 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1210739 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 569730 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 569730 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 466644 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 466644 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 112666 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 112666 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 182078 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 182078 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 3889795 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 3889795 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4459525 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4459525 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23510 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23510 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22572 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22572 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 46082 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 46082 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38219808000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38219808000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24026284000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24026284000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13466616000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13466616000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19450050500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19450050500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1560972500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1560972500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4174804000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174804000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5498500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5498500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62246092000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 62246092000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75712708000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 75712708000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4058237000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4058237000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3938068000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3938068000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7996305000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7996305000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035398 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017935 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017935 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.706919 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.706919 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.713832 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.713832 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067486 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067486 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109179 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109179 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027165 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027165 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030970 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030970 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14266.147479 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14266.147479 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19844.313267 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19844.313267 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23636.838502 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23636.838502 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41680.704134 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41680.704134 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13854.867484 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13854.867484 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22928.656949 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22928.656949 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3447609 # number of writebacks +system.cpu1.dcache.writebacks::total 3447609 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 379178 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 379178 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 964484 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 964484 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 92 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 92 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41281 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41281 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 68 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 68 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1343662 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1343662 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1343662 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1343662 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2968986 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2968986 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1357243 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1357243 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 675071 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 675071 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 453750 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 453750 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 121788 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 121788 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199325 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 199325 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4326229 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4326229 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5001300 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5001300 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23522 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23522 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22517 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22517 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 46039 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 46039 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44110385000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44110385000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27847514500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27847514500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16178845000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16178845000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20154706000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20154706000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1764852000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1764852000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4482506000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4482506000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3997500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3997500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 71957899500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 71957899500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 88136744500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 88136744500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4055697500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4055697500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3925636000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3925636000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7981333500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7981333500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036024 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036024 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018523 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018523 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.726030 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.726030 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.693923 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.693923 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060938 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060938 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099828 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099828 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027787 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027787 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031933 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031933 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14857.053890 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14857.053890 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20517.707220 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20517.707220 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23966.138377 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23966.138377 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44418.084848 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44418.084848 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14491.181397 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14491.181397 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22488.428446 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22488.428446 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16002.409381 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16002.409381 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16977.751666 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16977.751666 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172617.481923 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172617.481923 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174466.950204 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174466.950204 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173523.393082 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173523.393082 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16632.938178 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16632.938178 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17622.766981 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17622.766981 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172421.456509 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172421.456509 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174340.986810 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174340.986810 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173360.270640 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173360.270640 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 8864427 # number of replacements -system.cpu1.icache.tags.tagsinuse 506.853262 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 210585390 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8864939 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 23.754861 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 9020173 # number of replacements +system.cpu1.icache.tags.tagsinuse 506.865133 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 232936753 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9020685 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.822513 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8389731746000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.853262 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989948 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.989948 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.865133 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989971 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.989971 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 447765626 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 447765626 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 210585390 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 210585390 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 210585390 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 210585390 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 210585390 # number of overall hits -system.cpu1.icache.overall_hits::total 210585390 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8864949 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8864949 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8864949 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8864949 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8864949 # number of overall misses -system.cpu1.icache.overall_misses::total 8864949 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 93186086500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 93186086500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 93186086500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 93186086500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 93186086500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 93186086500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 219450339 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 219450339 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 219450339 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 219450339 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 219450339 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 219450339 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.040396 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.040396 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.040396 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.040396 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.040396 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.040396 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10511.745358 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10511.745358 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10511.745358 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10511.745358 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10511.745358 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10511.745358 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 492935590 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 492935590 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 232936753 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 232936753 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 232936753 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 232936753 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 232936753 # number of overall hits +system.cpu1.icache.overall_hits::total 232936753 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 9020695 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 9020695 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 9020695 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 9020695 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 9020695 # number of overall misses +system.cpu1.icache.overall_misses::total 9020695 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 95573427500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 95573427500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 95573427500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 95573427500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 95573427500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 95573427500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 241957448 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 241957448 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 241957448 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 241957448 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 241957448 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 241957448 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037282 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.037282 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037282 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.037282 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037282 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.037282 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10594.907321 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10594.907321 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10594.907321 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10594.907321 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10594.907321 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10594.907321 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1822,255 +1822,257 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8864949 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8864949 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8864949 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8864949 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8864949 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 8864949 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9020695 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 9020695 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 9020695 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 9020695 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 9020695 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 9020695 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 88753612500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 88753612500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 88753612500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 88753612500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 88753612500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 88753612500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91063080500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 91063080500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91063080500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 91063080500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91063080500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 91063080500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12520000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12520000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12520000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 12520000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.040396 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.040396 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.040396 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10011.745414 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10011.745414 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10011.745414 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037282 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037282 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037282 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.037282 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037282 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.037282 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10094.907377 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10094.907377 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10094.907377 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10094.907377 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10094.907377 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10094.907377 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136086.956522 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136086.956522 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6449392 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6450426 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 905 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7367099 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7368207 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 970 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 802102 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2183837 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13560.981052 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 24336260 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2199514 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.064381 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9986977778000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 3995.301083 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.705175 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.813454 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5399.423450 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3183.311357 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 849.426534 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.243854 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004132 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004017 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.329555 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.194294 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051845 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.827697 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1064 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14535 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 92 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 248 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 600 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 111 # Occupied blocks per task id +system.cpu1.l2cache.prefetcher.pfSpanPage 915185 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2451047 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13486.856931 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 25401363 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2467204 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 10.295607 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9750772511500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5534.671535 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 72.865878 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 75.759865 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3715.594887 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3131.532678 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 956.432088 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.337810 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004447 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004624 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.226782 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.191134 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.058376 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.823172 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1547 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14551 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 27 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 141 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 670 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 709 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 39 # 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mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087133 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.254587 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181559 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33051.111476 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43272.670972 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43272.670972 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 33917.573139 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 33917.573139 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18746.017615 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18746.017615 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 709285.571429 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 709285.571429 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 42515.089416 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 42515.089416 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30006.524096 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29665.921682 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29665.921682 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 60396.177826 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 60396.177826 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32246.600645 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31362.703847 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32246.600645 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43272.670972 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34326.521513 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191657 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 45405.487361 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62763.794851 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 33876.592015 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 33876.592015 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18404.479084 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18404.479084 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3584500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3584500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47001.856084 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47001.856084 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30210.657025 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31801.599439 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31801.599439 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 61599.092773 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 61599.092773 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34713.726625 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33100.996437 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34713.726625 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40912.032789 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164615.057422 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164472.671807 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166966.440723 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166966.440723 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164418.990732 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164277.441348 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166840.276236 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166840.276236 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 165766.817846 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 165691.742106 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 165603.205978 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 165528.386551 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 27994147 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14282234 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2462 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 511124 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 511112 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 12 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 774549 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13093104 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 22572 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 22572 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 4024053 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 12566811 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 824857 # Transaction distribution +system.cpu1.toL2Bus.snoop_filter.tot_requests 29416501 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15028447 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2391 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 554511 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 554502 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 9 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 803941 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13684916 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 22517 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 22517 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 4553047 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 13043260 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 982334 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 394282 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 330789 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 437890 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1101707 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1029116 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8864949 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4459910 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 472941 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 464971 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26592839 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15453192 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 351687 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1018625 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 43416343 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 567362560 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 485060327 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1274328 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3680592 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1057377807 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5633237 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 33839951 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.023781 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.152368 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeReq 414162 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 358438 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 473685 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1229561 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1158646 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9020695 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4893253 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 460729 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 452056 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27060072 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17084009 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332493 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1088108 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 45564682 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 577330304 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 542008212 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1195776 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3926416 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1124460708 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6177589 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 35784390 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.024790 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.155485 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 33035226 97.62% 97.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 804713 2.38% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 12 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 34897315 97.52% 97.52% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 887066 2.48% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 9 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 33839951 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 17356578996 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 35784390 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 18416469994 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 182990836 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 187934075 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13300024061 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13533732383 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7030302930 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7841048470 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 192411968 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 183047447 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 558633834 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 597345920 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40378 # Transaction distribution -system.iobus.trans_dist::ReadResp 40378 # Transaction distribution -system.iobus.trans_dist::WriteReq 136939 # Transaction distribution -system.iobus.trans_dist::WriteResp 136939 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40341 # Transaction distribution +system.iobus.trans_dist::ReadResp 40341 # Transaction distribution +system.iobus.trans_dist::WriteReq 136603 # Transaction distribution +system.iobus.trans_dist::WriteResp 136603 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47670 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2321,18 +2327,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122772 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231782 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231782 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122552 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354634 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47690 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2342,18 +2348,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155810 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339040 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36227000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36193000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2373,7 +2379,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2381,71 +2387,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 567439447 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 566159223 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92820000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92680000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148222000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147952000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115886 # number of replacements -system.iocache.tags.tagsinuse 11.252205 # Cycle average of tags in use +system.iocache.tags.replacements 115609 # number of replacements +system.iocache.tags.tagsinuse 11.261931 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115902 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115625 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9146784544000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.402122 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.850083 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.462633 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.240630 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.703263 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9146785142000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.823570 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.438361 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.238973 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.464898 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.703871 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043376 # Number of tag accesses -system.iocache.tags.data_accesses 1043376 # Number of data accesses +system.iocache.tags.tag_accesses 1041009 # Number of tag accesses +system.iocache.tags.data_accesses 1041009 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8907 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8944 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8900 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8937 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8907 # number of demand (read+write) misses -system.iocache.demand_misses::total 8947 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8900 # number of demand (read+write) misses +system.iocache.demand_misses::total 8940 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8907 # number of overall misses -system.iocache.overall_misses::total 8947 # number of overall misses +system.iocache.overall_misses::realview.ide 8900 # number of overall misses +system.iocache.overall_misses::total 8940 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1688317981 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1693512981 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1696302972 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1701497972 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13959998466 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13959998466 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13913628251 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13913628251 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1688317981 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1693881981 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1696302972 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1701866972 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1688317981 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1693881981 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1696302972 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1701866972 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8907 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8944 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8900 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8937 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8907 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8947 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8900 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8940 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8907 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8947 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8900 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8940 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2460,54 +2466,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 189549.565623 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 189346.263529 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 190595.839551 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 190388.046548 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130486.787426 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130486.787426 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130365.304803 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130365.304803 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 189549.565623 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 189324.017101 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 190595.839551 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 190365.433110 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 189549.565623 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 189324.017101 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34260 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 190595.839551 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 190365.433110 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34247 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3572 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3593 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.591265 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.531589 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106949 # number of writebacks -system.iocache.writebacks::total 106949 # number of writebacks +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8907 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8944 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8900 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8937 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8907 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8947 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8900 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8940 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8907 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8947 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8900 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8940 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1242967981 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1246312981 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1251302972 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1254647972 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8610798466 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8610798466 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8577228251 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8577228251 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1242967981 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1246531981 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1251302972 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1254866972 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1242967981 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1246531981 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1251302972 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1254866972 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2522,619 +2528,617 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139549.565623 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 139346.263529 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140595.839551 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 140388.046548 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80486.787426 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80486.787426 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80365.304803 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80365.304803 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 139549.565623 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 139324.017101 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 140595.839551 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 140365.433110 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 139549.565623 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 139324.017101 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 140595.839551 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 140365.433110 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1172651 # number of replacements -system.l2c.tags.tagsinuse 63896.612844 # Cycle average of tags in use -system.l2c.tags.total_refs 5899189 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1234288 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.779427 # Average number of references to valid blocks. +system.l2c.tags.replacements 1566664 # number of replacements +system.l2c.tags.tagsinuse 63931.901156 # Cycle average of tags in use +system.l2c.tags.total_refs 6426547 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1627093 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.949711 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 19626.342189 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 209.741305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 250.506537 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6148.160419 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 12486.088901 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 12942.693356 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 77.886538 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 86.786571 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4894.205028 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3546.886464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3627.315534 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.299474 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003200 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003822 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.093813 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.190523 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.197490 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001188 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001324 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.074680 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.054121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.055348 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.974985 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 12177 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 211 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49249 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 56 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1468 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 3502 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 7139 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1696 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 11834 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 35465 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.185806 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003220 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.751480 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 69068672 # Number of tag accesses -system.l2c.tags.data_accesses 69068672 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2213157 # number of Writeback hits -system.l2c.Writeback_hits::total 2213157 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 26227 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 30963 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 57190 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5791 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6000 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11791 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 170699 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 173368 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 344067 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6059 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4018 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 717194 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 567434 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 309455 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6450 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4624 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 697524 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 530409 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 314319 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3157486 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6059 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4018 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 717194 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738133 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 309455 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6450 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4624 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 697524 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 703777 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 314319 # number of demand (read+write) hits -system.l2c.demand_hits::total 3501553 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6059 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4018 # number of overall hits -system.l2c.overall_hits::cpu0.inst 717194 # number of overall hits -system.l2c.overall_hits::cpu0.data 738133 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 309455 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6450 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4624 # number of overall hits -system.l2c.overall_hits::cpu1.inst 697524 # number of overall hits -system.l2c.overall_hits::cpu1.data 703777 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 314319 # number of overall hits -system.l2c.overall_hits::total 3501553 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 46094 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 42278 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 88372 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 9356 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 8640 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 17996 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 470394 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 130669 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 601063 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1338 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1196 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 55388 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 120389 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 168332 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1176 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1070 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 55224 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 85443 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 133806 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 623362 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1338 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1196 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 55388 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 590783 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 168332 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1176 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1070 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 55224 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 216112 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 133806 # number of demand (read+write) misses -system.l2c.demand_misses::total 1224425 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1338 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1196 # number of overall misses -system.l2c.overall_misses::cpu0.inst 55388 # number of overall misses -system.l2c.overall_misses::cpu0.data 590783 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 168332 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1176 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1070 # number of overall misses -system.l2c.overall_misses::cpu1.inst 55224 # number of overall misses -system.l2c.overall_misses::cpu1.data 216112 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 133806 # number of overall misses -system.l2c.overall_misses::total 1224425 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 737888500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 668601000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1406489500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 133423500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 126121000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 259544500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 68021517000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 17893316000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 85914833000 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 182621000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 165049500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7432164500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 16649727500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 27728020736 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 164644500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 152256000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 7382488500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 11836491000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 21662909721 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 93356372957 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 182621000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 165049500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 7432164500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 84671244500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27728020736 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 164644500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 152256000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 7382488500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 29729807000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 21662909721 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 179271205957 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 182621000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 165049500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 7432164500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 84671244500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27728020736 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 164644500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 152256000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 7382488500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 29729807000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 21662909721 # number of overall miss cycles -system.l2c.overall_miss_latency::total 179271205957 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 2213157 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2213157 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 72321 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 73241 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 145562 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 15147 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 14640 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29787 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 641093 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 304037 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 945130 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7397 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5214 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 772582 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 687823 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 477787 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7626 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5694 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 752748 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 615852 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 448125 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 3780848 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 7397 # 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miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.577245 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.607109 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.617680 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590164 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.604156 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.733738 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.429780 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.635958 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.180884 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.229382 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.071692 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5130.513561 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 11368.638005 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11382.688685 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 175.831777 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 202.455245 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3752.541531 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4974.040380 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9212.662336 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.264592 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002795 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003190 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.078285 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.173472 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.173686 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002683 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003089 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.057259 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.075898 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.140574 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.975523 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 9887 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 204 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50338 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 102 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 389 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9395 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 202 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1895 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5328 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 42935 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.150864 # 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number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4133 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 754192 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 775227 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 292319 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6682 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4427 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 728293 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 783529 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 315465 # number of demand (read+write) hits +system.l2c.demand_hits::total 3670690 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6423 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4133 # number of overall hits +system.l2c.overall_hits::cpu0.inst 754192 # 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mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.174987 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.138705 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.164773 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.444538 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.234910 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.259003 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.444538 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.234910 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.259003 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73490.367618 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73686.823052 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73584.353755 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76477.928602 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76548.726968 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76511.919371 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 134605.409508 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 126936.197568 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 132938.149578 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128290.295779 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128534.399803 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 139782.944355 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133318.770588 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127567.975992 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 136421.829164 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133318.770588 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127567.975992 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 136421.829164 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.624401 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.573317 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.598337 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.600000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.594433 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.597295 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.760978 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.452138 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.661157 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.271356 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.340619 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.082342 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.207900 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.488955 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.264900 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.313962 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.073042 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.154087 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426047 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.216232 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.271356 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.340619 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.082342 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.465531 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.488955 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.264900 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.313962 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.073042 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.246563 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426047 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.300824 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.271356 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.340619 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.082342 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.465531 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.488955 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.264900 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.313962 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.073042 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.246563 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426047 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.300824 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73580.712214 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73562.888904 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73571.998826 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76479.682642 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76568.010076 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76522.396324 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135274.794522 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 128373.621440 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 133749.410282 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124676.223818 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130896.398879 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125219.539809 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131281.027775 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 148108.950330 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124676.223818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 134230.283373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125219.539809 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 129626.836307 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 142108.606976 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124676.223818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 134230.283373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125219.539809 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 129626.836307 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 142108.606976 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 141131.350427 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 140688.023422 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146626.786626 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 126109.958690 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 139130.829350 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149965.776183 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145557.654911 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146431.271259 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 126000.342133 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138396.453126 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149839.721100 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145162.946429 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 140102.617332 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139509.057851 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148262.369792 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 131865.259589 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148098.366531 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 131670.738530 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 90534 # Transaction distribution -system.membus.trans_dist::ReadResp 722459 # Transaction distribution -system.membus.trans_dist::WriteReq 38054 # Transaction distribution -system.membus.trans_dist::WriteResp 38054 # Transaction distribution -system.membus.trans_dist::Writeback 1001017 # Transaction distribution -system.membus.trans_dist::CleanEvict 217536 # Transaction distribution -system.membus.trans_dist::UpgradeReq 423474 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 287804 # Transaction distribution -system.membus.trans_dist::UpgradeResp 114083 # Transaction distribution +system.membus.trans_dist::ReadReq 90608 # Transaction distribution +system.membus.trans_dist::ReadResp 1019089 # Transaction distribution +system.membus.trans_dist::WriteReq 38080 # Transaction distribution +system.membus.trans_dist::WriteResp 38080 # Transaction distribution +system.membus.trans_dist::Writeback 1301925 # Transaction distribution +system.membus.trans_dist::CleanEvict 271570 # Transaction distribution +system.membus.trans_dist::UpgradeReq 429176 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 310200 # Transaction distribution +system.membus.trans_dist::UpgradeResp 115027 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 614073 # Transaction distribution -system.membus.trans_dist::ReadExResp 593351 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 631925 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106984 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122772 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 674063 # Transaction distribution +system.membus.trans_dist::ReadExResp 652544 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 928481 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122552 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24382 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4492959 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4640165 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 343288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4983453 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155810 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24802 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5589312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5736718 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342877 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342877 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6079595 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155682 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48764 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 138392448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 138598346 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7280768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7280768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 145879114 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 620798 # Total snoops (count) -system.membus.snoop_fanout::samples 3413791 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49604 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 180435584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 180642194 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7274816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7274816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 187917010 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 648574 # Total snoops (count) +system.membus.snoop_fanout::samples 4152999 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3413791 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4152999 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3413791 # Request fanout histogram -system.membus.reqLayer0.occupancy 110035999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4152999 # Request fanout histogram +system.membus.reqLayer0.occupancy 109607499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20235499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20503498 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7135371847 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9125026082 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7009823140 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8873044520 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 230763823 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 230408874 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3145,11 +3149,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -3188,52 +3192,52 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 11297780 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5747695 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2144395 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 127398 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 116260 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11138 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 90536 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4706613 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38054 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38054 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3214229 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1520051 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 472952 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 299595 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 772547 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1095800 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1095800 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4623306 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8277775 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6810974 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15088749 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 253701939 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194091607 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 447793546 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2987756 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 12830892 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.357421 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.481048 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 12411375 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6308416 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2241470 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 182770 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 168316 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 14454 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 90610 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5207811 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38080 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38080 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3858986 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1729776 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 481704 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 322377 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 804081 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1151274 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1151274 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 5124442 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9065091 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7602046 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 16667137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 281816078 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 221579908 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 503395986 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3440017 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 14338060 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.337750 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.475069 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 8255998 64.34% 64.34% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4563756 35.57% 99.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11138 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9509841 66.33% 66.33% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4813765 33.57% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 14454 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 12830892 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8297238000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 14338060 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9248164097 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2658855 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2627637 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4939762812 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5363594791 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4158976314 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4586237114 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |