diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 5160 |
1 files changed, 2571 insertions, 2589 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index d3ad4a453..0c25a081b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,170 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.482330 # Number of seconds simulated -sim_ticks 47482329862000 # Number of ticks simulated -final_tick 47482329862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.411962 # Number of seconds simulated +sim_ticks 47411962285000 # Number of ticks simulated +final_tick 47411962285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176341 # Simulator instruction rate (inst/s) -host_op_rate 207374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9393535208 # Simulator tick rate (ticks/s) -host_mem_usage 769764 # Number of bytes of host memory used -host_seconds 5054.79 # Real time elapsed on the host -sim_insts 891365561 # Number of instructions simulated -sim_ops 1048233259 # Number of ops (including micro ops) simulated +host_inst_rate 170497 # Simulator instruction rate (inst/s) +host_op_rate 200546 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9509503550 # Simulator tick rate (ticks/s) +host_mem_usage 769500 # Number of bytes of host memory used +host_seconds 4985.75 # Real time elapsed on the host +sim_insts 850056300 # Number of instructions simulated +sim_ops 999871495 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 124416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 101184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 8041216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 40378184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 15310528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 143616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 132928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3236032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 17140560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 13345792 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 446144 # Number of bytes read from this memory -system.physmem.bytes_read::total 98400600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 8041216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3236032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11277248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78262528 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 75328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 71168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7498816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 38111304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10728384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 51264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 47808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2878784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12174608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 7747264 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 431104 # Number of bytes read from this memory +system.physmem.bytes_read::total 79815832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7498816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2878784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10377600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 62807296 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 78283112 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1581 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 125644 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 630922 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 239227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2244 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 50563 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 267834 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 208528 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6971 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1537535 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1222852 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 62827880 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 117169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 595502 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 167631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 801 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 747 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 190241 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 121051 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6736 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1247148 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 981364 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1225426 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 169352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 850383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 322447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2800 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 68152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 360988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 281069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2072363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 169352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 68152 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 237504 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1648245 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 983938 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 158163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 803833 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 226280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 60719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 256783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 163403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1683453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 158163 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 60719 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 218881 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1324714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1648679 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1648245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 169352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 850817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 322447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 68152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 360988 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 281069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3721041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1537535 # Number of read requests accepted -system.physmem.writeReqs 1225426 # Number of write requests accepted -system.physmem.readBursts 1537535 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1225426 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 98362112 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 40128 # Total number of bytes read from write queue -system.physmem.bytesWritten 78282112 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 98400600 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 78283112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 627 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1325148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1324714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 158163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 804267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 226280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 60719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 256784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 163403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3008602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1247148 # Number of read requests accepted +system.physmem.writeReqs 983938 # Number of write requests accepted +system.physmem.readBursts 1247148 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 983938 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 79775360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 42112 # Total number of bytes read from write queue +system.physmem.bytesWritten 62826240 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 79815832 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 62827880 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 658 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 220170 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 94941 # Per bank write bursts -system.physmem.perBankRdBursts::1 98803 # Per bank write bursts -system.physmem.perBankRdBursts::2 90365 # Per bank write bursts -system.physmem.perBankRdBursts::3 103122 # Per bank write bursts -system.physmem.perBankRdBursts::4 90513 # Per bank write bursts -system.physmem.perBankRdBursts::5 102407 # Per bank write bursts -system.physmem.perBankRdBursts::6 86370 # Per bank write bursts -system.physmem.perBankRdBursts::7 97727 # Per bank write bursts -system.physmem.perBankRdBursts::8 90531 # Per bank write bursts -system.physmem.perBankRdBursts::9 141203 # Per bank write bursts -system.physmem.perBankRdBursts::10 86748 # Per bank write bursts -system.physmem.perBankRdBursts::11 95428 # Per bank write bursts -system.physmem.perBankRdBursts::12 92596 # Per bank write bursts -system.physmem.perBankRdBursts::13 93840 # Per bank write bursts -system.physmem.perBankRdBursts::14 85305 # Per bank write bursts -system.physmem.perBankRdBursts::15 87009 # Per bank write bursts -system.physmem.perBankWrBursts::0 77173 # Per bank write bursts -system.physmem.perBankWrBursts::1 80360 # Per bank write bursts -system.physmem.perBankWrBursts::2 74652 # Per bank write bursts -system.physmem.perBankWrBursts::3 83758 # Per bank write bursts -system.physmem.perBankWrBursts::4 75004 # Per bank write bursts -system.physmem.perBankWrBursts::5 81344 # Per bank write bursts -system.physmem.perBankWrBursts::6 71841 # Per bank write bursts -system.physmem.perBankWrBursts::7 79366 # Per bank write bursts -system.physmem.perBankWrBursts::8 74851 # Per bank write bursts -system.physmem.perBankWrBursts::9 75375 # Per bank write bursts -system.physmem.perBankWrBursts::10 73319 # Per bank write bursts -system.physmem.perBankWrBursts::11 78054 # Per bank write bursts -system.physmem.perBankWrBursts::12 76445 # Per bank write bursts -system.physmem.perBankWrBursts::13 77751 # Per bank write bursts -system.physmem.perBankWrBursts::14 70793 # Per bank write bursts -system.physmem.perBankWrBursts::15 73072 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 218244 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 71187 # Per bank write bursts +system.physmem.perBankRdBursts::1 77028 # Per bank write bursts +system.physmem.perBankRdBursts::2 72273 # Per bank write bursts +system.physmem.perBankRdBursts::3 78219 # Per bank write bursts +system.physmem.perBankRdBursts::4 70385 # Per bank write bursts +system.physmem.perBankRdBursts::5 81119 # Per bank write bursts +system.physmem.perBankRdBursts::6 72267 # Per bank write bursts +system.physmem.perBankRdBursts::7 76746 # Per bank write bursts +system.physmem.perBankRdBursts::8 71370 # Per bank write bursts +system.physmem.perBankRdBursts::9 123762 # Per bank write bursts +system.physmem.perBankRdBursts::10 72044 # Per bank write bursts +system.physmem.perBankRdBursts::11 80747 # Per bank write bursts +system.physmem.perBankRdBursts::12 73100 # Per bank write bursts +system.physmem.perBankRdBursts::13 79351 # Per bank write bursts +system.physmem.perBankRdBursts::14 74612 # Per bank write bursts +system.physmem.perBankRdBursts::15 72280 # Per bank write bursts +system.physmem.perBankWrBursts::0 58860 # Per bank write bursts +system.physmem.perBankWrBursts::1 62909 # Per bank write bursts +system.physmem.perBankWrBursts::2 59749 # Per bank write bursts +system.physmem.perBankWrBursts::3 64358 # Per bank write bursts +system.physmem.perBankWrBursts::4 59245 # Per bank write bursts +system.physmem.perBankWrBursts::5 66477 # Per bank write bursts +system.physmem.perBankWrBursts::6 59553 # Per bank write bursts +system.physmem.perBankWrBursts::7 62082 # Per bank write bursts +system.physmem.perBankWrBursts::8 58790 # Per bank write bursts +system.physmem.perBankWrBursts::9 60994 # Per bank write bursts +system.physmem.perBankWrBursts::10 60508 # Per bank write bursts +system.physmem.perBankWrBursts::11 63849 # Per bank write bursts +system.physmem.perBankWrBursts::12 60193 # Per bank write bursts +system.physmem.perBankWrBursts::13 63756 # Per bank write bursts +system.physmem.perBankWrBursts::14 60310 # Per bank write bursts +system.physmem.perBankWrBursts::15 60027 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 43 # Number of times write queue was full causing retry -system.physmem.totGap 47482327991500 # Total gap between requests +system.physmem.numWrRetry 30 # Number of times write queue was full causing retry +system.physmem.totGap 47411960356500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1537505 # Read request sizes (log2) +system.physmem.readPktSize::6 1247118 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1222852 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 944383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 373776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 49487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 29546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 27146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 25089 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 22356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 19759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 863 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 981364 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 795503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 313068 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 17861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 16010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 13834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 11987 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -188,164 +188,150 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 20135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 57274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 64486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 68059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 69963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 74225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 75616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 79113 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 122 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 940608 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 187.797442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 115.260175 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 246.189901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 561167 59.66% 59.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 186793 19.86% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 62478 6.64% 86.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 31194 3.32% 89.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 21090 2.24% 91.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13303 1.41% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10059 1.07% 94.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 10062 1.07% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 44462 4.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 940608 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 69828 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.009810 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 322.555489 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 69825 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 14920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 38389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 48185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 52683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 54849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 56160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 63775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 64447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 63620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 68672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 57038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 86 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 737647 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 193.317834 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 117.156586 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 253.851861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 435526 59.04% 59.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 146539 19.87% 78.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49058 6.65% 85.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 25178 3.41% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15871 2.15% 91.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10341 1.40% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7959 1.08% 93.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8404 1.14% 94.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 38771 5.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 737647 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 55115 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.615186 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 363.032286 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 55112 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 69828 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 69828 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.516727 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.040521 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.611414 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 66194 94.80% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1213 1.74% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 484 0.69% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 227 0.33% 97.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 283 0.41% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 499 0.71% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 107 0.15% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 41 0.06% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 40 0.06% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 28 0.04% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 48 0.07% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 19 0.03% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 437 0.63% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 59 0.08% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 38 0.05% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 18 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 30 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 69828 # Writes before turning the bus around for reads -system.physmem.totQLat 47438420321 # Total ticks spent queuing -system.physmem.totMemAccLat 76255445321 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7684540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30866.14 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 55115 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 55115 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.811122 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.212895 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.489514 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 52725 95.66% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 682 1.24% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 764 1.39% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 154 0.28% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 76 0.14% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 61 0.11% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 472 0.86% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 111 0.20% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 10 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 8 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 31 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 7 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 3 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 55115 # Writes before turning the bus around for reads +system.physmem.totQLat 32865022462 # Total ticks spent queuing +system.physmem.totMemAccLat 56236709962 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6232450000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26366.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 49616.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.07 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.07 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45116.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.68 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.33 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.49 # Average write queue length when enqueuing -system.physmem.readRowHits 1237162 # Number of row buffer hits during reads -system.physmem.writeRowHits 582295 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.61 # Row buffer hit rate for writes -system.physmem.avgGap 17185305.18 # Average gap between requests -system.physmem.pageHitRate 65.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3664415160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1999432875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5961079800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4040267040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3101314831680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1200459376170 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27436362274500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31753801677225 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.749891 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45642197013620 # Time in different power states -system.physmem_0.memoryStateTime::REF 1585539280000 # Time in different power states +system.physmem.avgWrQLen 23.59 # Average write queue length when enqueuing +system.physmem.readRowHits 1009662 # Number of row buffer hits during reads +system.physmem.writeRowHits 480836 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 48.98 # Row buffer hit rate for writes +system.physmem.avgGap 21250619.81 # Average gap between requests +system.physmem.pageHitRate 66.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2808479520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1532404500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4673861400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3196149840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3096718466400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1173181763970 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27418066728000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31700177853630 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.611477 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45611956984095 # Time in different power states +system.physmem_0.memoryStateTime::REF 1583189400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 254592941380 # Time in different power states +system.physmem_0.memoryStateTime::ACT 216810169905 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3446581320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1880575125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6026748000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3885796800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3101314831680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1189099091205 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27446327436750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31751981060880 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.711548 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45658799171891 # Time in different power states -system.physmem_1.memoryStateTime::REF 1585539280000 # Time in different power states +system.physmem_1.actEnergy 2768124240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1510385250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5048596800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3165006960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3096718466400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1175060323800 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27416418868500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31700689771950 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.622274 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45609169557313 # Time in different power states +system.physmem_1.memoryStateTime::REF 1583189400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 237989586859 # Time in different power states +system.physmem_1.memoryStateTime::ACT 219597434187 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -376,18 +362,18 @@ system.realview.nvmem.bw_total::total 28 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 132987745 # Number of BP lookups -system.cpu0.branchPred.condPredicted 94268605 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6098049 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 100013530 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 72636793 # Number of BTB hits +system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 130279608 # Number of BP lookups +system.cpu0.branchPred.condPredicted 91518189 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6235368 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 97695080 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 70156250 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.626967 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15695407 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1093856 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.811446 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15568853 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1041049 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -418,66 +404,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 275636 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 275636 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8285 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76005 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 275636 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 275636 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 275636 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 84290 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 20584.826195 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18820.617576 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14196.942212 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 79742 94.60% 94.60% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3631 4.31% 98.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 417 0.49% 99.41% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 355 0.42% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 30 0.04% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 13 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 32 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 8 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 18 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 24 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 84290 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 272738 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 272738 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8357 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 77299 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 272738 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 272738 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 272738 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 85656 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 20319.907537 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18687.643521 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 12933.686898 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 84887 99.10% 99.10% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 657 0.77% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 28 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 42 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 27 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 85656 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 669754704 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 669754704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 669754704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 76005 90.17% 90.17% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 8285 9.83% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 84290 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 275636 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 77299 90.24% 90.24% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8357 9.76% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 85656 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 272738 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 275636 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 84290 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 272738 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85656 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 84290 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 359926 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85656 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 358394 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 84907220 # DTB read hits -system.cpu0.dtb.read_misses 227423 # DTB read misses -system.cpu0.dtb.write_hits 75575788 # DTB write hits -system.cpu0.dtb.write_misses 48213 # DTB write misses +system.cpu0.dtb.read_hits 83911764 # DTB read hits +system.cpu0.dtb.read_misses 226051 # DTB read misses +system.cpu0.dtb.write_hits 74892635 # DTB write hits +system.cpu0.dtb.write_misses 46687 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35105 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1851 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8962 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 35474 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1932 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8858 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10953 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 85134643 # DTB read accesses -system.cpu0.dtb.write_accesses 75624001 # DTB write accesses +system.cpu0.dtb.perms_faults 11487 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 84137815 # DTB read accesses +system.cpu0.dtb.write_accesses 74939322 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 160483008 # DTB hits -system.cpu0.dtb.misses 275636 # DTB misses -system.cpu0.dtb.accesses 160758644 # DTB accesses +system.cpu0.dtb.hits 158804399 # DTB hits +system.cpu0.dtb.misses 272738 # DTB misses +system.cpu0.dtb.accesses 159077137 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,193 +488,190 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 64906 # Table walker walks requested -system.cpu0.itb.walker.walksLong 64906 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 453 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52493 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 64906 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 64906 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 64906 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 52946 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 23323.187776 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21129.664435 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 16367.746814 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 48035 90.72% 90.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3919 7.40% 98.13% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 305 0.58% 98.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 573 1.08% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 22 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 23 0.04% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 32 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 10 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 11 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 52946 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 68078 # Table walker walks requested +system.cpu0.itb.walker.walksLong 68078 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 722 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61066 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 68078 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 68078 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 68078 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 61788 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 22737.489480 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21008.732396 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 13692.086470 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 57025 92.29% 92.29% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3907 6.32% 98.61% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 284 0.46% 99.07% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 503 0.81% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 9 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 25 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 61788 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 669040204 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 669040204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 669040204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 52493 99.14% 99.14% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 453 0.86% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 52946 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 61066 98.83% 98.83% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 722 1.17% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 61788 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64906 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64906 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 68078 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 68078 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52946 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52946 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 117852 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 238223958 # ITB inst hits -system.cpu0.itb.inst_misses 64906 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61788 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61788 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 129866 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 232943519 # ITB inst hits +system.cpu0.itb.inst_misses 68078 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24846 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 25164 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 205008 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 198596 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 238288864 # ITB inst accesses -system.cpu0.itb.hits 238223958 # DTB hits -system.cpu0.itb.misses 64906 # DTB misses -system.cpu0.itb.accesses 238288864 # DTB accesses -system.cpu0.numCycles 971262699 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 233011597 # ITB inst accesses +system.cpu0.itb.hits 232943519 # DTB hits +system.cpu0.itb.misses 68078 # DTB misses +system.cpu0.itb.accesses 233011597 # DTB accesses +system.cpu0.numCycles 944358949 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 437915417 # Number of instructions committed -system.cpu0.committedOps 515248827 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 45685554 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4508 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93994129820 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.217923 # CPI: cycles per instruction -system.cpu0.ipc 0.450872 # IPC: instructions per cycle +system.cpu0.committedInsts 433389926 # Number of instructions committed +system.cpu0.committedOps 509312382 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 43329563 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4813 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93880363578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.179005 # CPI: cycles per instruction +system.cpu0.ipc 0.458925 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13434 # number of quiesce instructions executed -system.cpu0.tickCycles 710739035 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 260523664 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5570429 # number of replacements -system.cpu0.dcache.tags.tagsinuse 501.849943 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 152007137 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5570934 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.285754 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4974167000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.849943 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980176 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.980176 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 323765599 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 323765599 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77611950 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77611950 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69963904 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69963904 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 263445 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 263445 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 169638 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 169638 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1758419 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1758419 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1721710 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1721710 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 147575854 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 147575854 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147839299 # number of overall hits -system.cpu0.dcache.overall_hits::total 147839299 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3380647 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3380647 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2384184 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2384184 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670394 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 670394 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 781336 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 781336 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 154783 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 154783 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189820 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 189820 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5764831 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5764831 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6435225 # number of overall misses -system.cpu0.dcache.overall_misses::total 6435225 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 51653726500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 51653726500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 46144722000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 46144722000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 52344211500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 52344211500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2307846500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2307846500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3989603000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3989603000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3214000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3214000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 97798448500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 97798448500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 97798448500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 97798448500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 80992597 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 80992597 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 72348088 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 72348088 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 933839 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 933839 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 950974 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 950974 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1913202 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1913202 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1911530 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1911530 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 153340685 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 153340685 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 154274524 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 154274524 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041740 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.041740 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032954 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.032954 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.717890 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.717890 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.821617 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.821617 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080903 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.080903 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099303 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099303 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037595 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.037595 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041713 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.041713 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15279.242849 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15279.242849 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19354.513746 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19354.513746 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 66993.216107 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 66993.216107 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14910.206547 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14910.206547 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21017.822147 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21017.822147 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 13422 # number of quiesce instructions executed +system.cpu0.tickCycles 695520331 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 248838618 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5405789 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.914885 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 150600436 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5406301 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.856465 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4974406000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.914885 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978349 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.978349 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 320300004 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 320300004 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 77010804 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77010804 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69515704 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69515704 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 254236 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 254236 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 165535 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 165535 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1598340 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1598340 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1577518 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1577518 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 146526508 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 146526508 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 146780744 # number of overall hits +system.cpu0.dcache.overall_hits::total 146780744 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3243116 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3243116 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2266198 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2266198 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 618205 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 618205 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 821296 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 821296 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 155401 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 155401 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 174722 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 174722 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5509314 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5509314 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6127519 # number of overall misses +system.cpu0.dcache.overall_misses::total 6127519 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 48375468500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 48375468500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 42499797000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 42499797000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 51670537000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 51670537000 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2317304500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2317304500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3678685500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3678685500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2406500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2406500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 90875265500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 90875265500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 90875265500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 90875265500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 80253920 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 80253920 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 71781902 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 71781902 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 872441 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 872441 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 986831 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 986831 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1753741 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1753741 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1752240 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1752240 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 152035822 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 152035822 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 152908263 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 152908263 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040411 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.040411 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031571 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.031571 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.708592 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.708592 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.832256 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.832256 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088611 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088611 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099714 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099714 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036237 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.036237 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040073 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.040073 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14916.354672 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14916.354672 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18753.788063 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18753.788063 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 62913.416113 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 62913.416113 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14911.773412 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14911.773412 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21054.506588 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21054.506588 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16964.668782 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16964.668782 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15197.362718 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15197.362718 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16494.842280 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16494.842280 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14830.678697 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14830.678697 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -702,161 +680,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3773399 # number of writebacks -system.cpu0.dcache.writebacks::total 3773399 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 430069 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 430069 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 999795 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 999795 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 103 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 103 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40774 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 40774 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 43 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1429864 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1429864 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1429864 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1429864 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2950578 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2950578 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1384389 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1384389 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664773 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 664773 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 781233 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 781233 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 114009 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 114009 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189777 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 189777 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4334967 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4334967 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4999740 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4999740 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32882 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32882 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32815 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32815 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65697 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65697 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40501320500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40501320500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25594559000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25594559000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15267286500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15267286500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 51557242500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 51557242500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1530630500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1530630500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3798446000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3798446000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2841500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2841500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 66095879500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 66095879500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81363166000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 81363166000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5911844500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5911844500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5682739500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5682739500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11594584000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11594584000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036430 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036430 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019135 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019135 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.711871 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.711871 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.821508 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.821508 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059591 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059591 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099280 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099280 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028270 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028270 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032408 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032408 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13726.571709 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13726.571709 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18487.982063 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18487.982063 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22966.165142 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22966.165142 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 65994.706445 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 65994.706445 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13425.523424 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13425.523424 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20015.312709 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20015.312709 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3720174 # number of writebacks +system.cpu0.dcache.writebacks::total 3720174 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 395501 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 395501 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 949612 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 949612 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 96 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 96 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41791 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41791 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 77 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 77 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1345113 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1345113 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1345113 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1345113 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2847615 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2847615 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1316586 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1316586 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 612491 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 612491 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 821200 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 821200 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113610 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113610 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 174645 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 174645 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4164201 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4164201 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4776692 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4776692 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 30167 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 30167 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29885 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29885 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60052 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60052 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38218904500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 38218904500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23577025500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23577025500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13456556000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13456556000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 50843266000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 50843266000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1513106500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1513106500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3501575000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3501575000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2054500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2054500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61795930000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61795930000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75252486000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 75252486000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5426212000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5426212000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5134567500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5134567500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10560779500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10560779500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035483 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035483 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018341 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018341 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.702043 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.702043 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.832159 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.832159 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064782 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064782 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099670 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099670 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027390 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027390 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031239 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031239 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13421.373500 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13421.373500 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17907.698775 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17907.698775 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21970.210175 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21970.210175 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 61913.377983 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 61913.377983 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13318.427075 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.427075 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20049.672192 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20049.672192 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15247.147095 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15247.147095 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16273.479421 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16273.479421 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179789.687367 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179789.687367 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173175.057139 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173175.057139 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 176485.745163 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176485.745163 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14839.804803 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14839.804803 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15754.100537 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15754.100537 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179872.443398 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179872.443398 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171810.858290 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171810.858290 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 175860.579165 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 175860.579165 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 9510825 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.926606 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 228501569 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9511337 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.024127 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 29799763000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.926606 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999857 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 9471710 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.926461 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 223265309 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9472222 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 23.570532 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 29829927000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.926461 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999856 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999856 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 431 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 485537176 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 485537176 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 228501569 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 228501569 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 228501569 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 228501569 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 228501569 # number of overall hits -system.cpu0.icache.overall_hits::total 228501569 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9511346 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9511346 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9511346 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9511346 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9511346 # number of overall misses -system.cpu0.icache.overall_misses::total 9511346 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94734195000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 94734195000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 94734195000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 94734195000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 94734195000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 94734195000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 238012915 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 238012915 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 238012915 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 238012915 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 238012915 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 238012915 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039961 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.039961 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039961 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.039961 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039961 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.039961 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9960.124992 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9960.124992 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9960.124992 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9960.124992 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9960.124992 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9960.124992 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 474947313 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 474947313 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 223265309 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 223265309 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 223265309 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 223265309 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 223265309 # number of overall hits +system.cpu0.icache.overall_hits::total 223265309 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9472232 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9472232 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9472232 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9472232 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9472232 # number of overall misses +system.cpu0.icache.overall_misses::total 9472232 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93317915500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 93317915500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 93317915500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 93317915500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 93317915500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 93317915500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 232737541 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 232737541 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 232737541 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 232737541 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 232737541 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 232737541 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040699 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.040699 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040699 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.040699 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040699 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.040699 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9851.734575 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9851.734575 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9851.734575 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9851.734575 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9851.734575 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9851.734575 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -865,252 +843,256 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9511346 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9511346 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9511346 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9511346 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9511346 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9511346 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9472232 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9472232 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9472232 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9472232 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9472232 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9472232 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 52292 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 52292 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89978522000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 89978522000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89978522000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 89978522000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89978522000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 89978522000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 88581800000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 88581800000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88581800000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 88581800000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 88581800000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 88581800000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4777780500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4777780500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039961 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.039961 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.039961 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9460.124992 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9460.124992 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9460.124992 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040699 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040699 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040699 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.040699 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040699 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.040699 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9351.734628 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9351.734628 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9351.734628 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9351.734628 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9351.734628 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9351.734628 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7512189 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7515615 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2942 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7001248 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7002240 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 870 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 975521 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2798117 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16231.650842 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 26314432 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2814109 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.350893 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 27335773000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6405.405319 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.558250 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 59.359829 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5460.175756 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3311.396146 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 928.755541 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.390955 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004062 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003623 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.333263 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.202112 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056687 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.990701 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1465 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 86 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14441 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # 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number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33953780489 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 33953780489 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 49014503000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 49014503000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 429581500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 328472000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23641079500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 47419005488 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 71818138488 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 429581500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 328472000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23641079500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 47419005488 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 71818138488 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 493153 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164673 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 657826 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3773399 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3773399 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 239769 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 239769 # 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number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 4885428 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 15054599 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024729 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053518 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.031935 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.544140 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.544140 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.814010 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.814010 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.prefetcher.pfSpanPage 934040 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2602937 # 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mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081749 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273400 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.273400 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755630 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755630 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263984 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.138710 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263984 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.233020 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.233020 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079539 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079539 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.261370 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261370 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.712968 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.712968 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021721 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045551 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079539 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.254675 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.132553 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021721 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045551 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079539 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.254675 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187286 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30086.717448 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48894.087088 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20301.303730 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20301.303730 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15251.634537 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15251.634537 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 794166 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 794166 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39966.645809 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39966.645809 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24404.302768 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27220.014094 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27220.014094 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 77198.341917 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77198.341917 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29889.876681 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27849.318172 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29889.876681 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33307.659423 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177598 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26111.712492 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37010.854497 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 37010.854497 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20276.645096 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20276.645096 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15402.680134 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15402.680134 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 858000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 858000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38499.621214 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38499.621214 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23701.224158 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23701.224158 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26628.258994 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26628.258994 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 76028.640923 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 76028.640923 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23701.224158 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29193.102099 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27056.580674 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23701.224158 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29193.102099 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37010.854497 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 29581.343345 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171784.395718 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117501.338437 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165674.249581 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165674.249581 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171868.034607 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 115744.642792 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164309.988288 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164309.988288 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168732.438315 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130899.147378 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168106.757477 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128663.671402 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 870203 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14200168 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32815 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 7469298 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 14383795 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1113522 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 480939 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348630 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 494804 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 46 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1552927 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1165328 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9511346 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6196752 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 886361 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 779633 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28635865 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18059535 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 358708 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1078688 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 48132796 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 612072768 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 561022439 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1317384 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3945224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1178357815 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 11561310 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 42854991 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.281176 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.449573 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 876246 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14005082 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38305 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 29885 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 6885213 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 13979886 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 878417 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 473566 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 319318 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 460407 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 105 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1465787 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1113779 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9472232 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5781099 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 926693 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 819709 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28518742 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17480007 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 376075 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1070420 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 47445244 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 609569408 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 544120273 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1382192 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3906208 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1158978081 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 10243316 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 41099849 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.261354 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.439372 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 30805196 71.88% 71.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 12049795 28.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 30358253 73.86% 73.86% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 10741596 26.14% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 42854991 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 19582200977 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 41099849 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 19306972981 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 188679986 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 182073987 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14347273859 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14288744572 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7985002182 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7674112954 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 194043982 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 203313475 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 585561447 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 582176435 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 137760504 # Number of BP lookups -system.cpu1.branchPred.condPredicted 98367064 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6188278 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 103396299 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 75843064 # Number of BTB hits +system.cpu1.branchPred.lookups 125904408 # Number of BP lookups +system.cpu1.branchPred.condPredicted 89122664 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5902634 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 94266188 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 68486701 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.351817 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 15930905 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1003913 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.652456 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15015861 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1004863 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1378,62 +1364,65 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 290439 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 290439 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10797 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87034 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 290439 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 290439 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 290439 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 97831 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20885.603745 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 19076.396548 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15781.781984 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 96557 98.70% 98.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.10% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 36 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 66 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 60 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 20 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 97831 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1532721648 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1532721648 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1532721648 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 87034 88.96% 88.96% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10797 11.04% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 97831 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 290439 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 261999 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 261999 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7478 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 69980 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 261999 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 261999 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 261999 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 77458 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19301.763536 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17918.383858 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 10994.886931 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 74315 95.94% 95.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2659 3.43% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 247 0.32% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 165 0.21% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 17 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 5 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 16 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 10 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 77458 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1501931648 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1501931648 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1501931648 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 69980 90.35% 90.35% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 7478 9.65% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 77458 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261999 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 290439 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97831 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261999 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 77458 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97831 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 388270 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 77458 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 339457 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 89204123 # DTB read hits -system.cpu1.dtb.read_misses 242859 # DTB read misses -system.cpu1.dtb.write_hits 77378465 # DTB write hits -system.cpu1.dtb.write_misses 47580 # DTB write misses +system.cpu1.dtb.read_hits 82663207 # DTB read hits +system.cpu1.dtb.read_misses 218762 # DTB read misses +system.cpu1.dtb.write_hits 71167787 # DTB write hits +system.cpu1.dtb.write_misses 43237 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 40087 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1034 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8257 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 35788 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 902 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6887 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11467 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 89446982 # DTB read accesses -system.cpu1.dtb.write_accesses 77426045 # DTB write accesses +system.cpu1.dtb.perms_faults 9904 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 82881969 # DTB read accesses +system.cpu1.dtb.write_accesses 71211024 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 166582588 # DTB hits -system.cpu1.dtb.misses 290439 # DTB misses -system.cpu1.dtb.accesses 166873027 # DTB accesses +system.cpu1.dtb.hits 153830994 # DTB hits +system.cpu1.dtb.misses 261999 # DTB misses +system.cpu1.dtb.accesses 154092993 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1463,192 +1452,191 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 66791 # Table walker walks requested -system.cpu1.itb.walker.walksLong 66791 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 712 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57147 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 66791 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 66791 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 66791 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 57859 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 23479.562384 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21074.499694 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18067.183609 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 53326 92.17% 92.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 3146 5.44% 97.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 488 0.84% 98.45% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 735 1.27% 99.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.05% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 27 0.05% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 52 0.09% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 8 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 9 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 8 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 59152 # Table walker walks requested +system.cpu1.itb.walker.walksLong 59152 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 461 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 48561 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 59152 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 59152 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 59152 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 49022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21340.612378 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19735.982166 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 12453.289543 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 45897 93.63% 93.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2624 5.35% 98.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 160 0.33% 99.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 295 0.60% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 9 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 10 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 57859 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1533304148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1533304148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1533304148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 57147 98.77% 98.77% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 712 1.23% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 57859 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 49022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1502514148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1502514148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1502514148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 48561 99.06% 99.06% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 461 0.94% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 49022 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 66791 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 66791 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59152 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59152 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57859 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 57859 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 124650 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 246625416 # ITB inst hits -system.cpu1.itb.inst_misses 66791 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49022 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49022 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 108174 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 225695696 # ITB inst hits +system.cpu1.itb.inst_misses 59152 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 29073 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25916 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 217204 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 201769 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 246692207 # ITB inst accesses -system.cpu1.itb.hits 246625416 # DTB hits -system.cpu1.itb.misses 66791 # DTB misses -system.cpu1.itb.accesses 246692207 # DTB accesses -system.cpu1.numCycles 916577474 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 225754848 # ITB inst accesses +system.cpu1.itb.hits 225695696 # DTB hits +system.cpu1.itb.misses 59152 # DTB misses +system.cpu1.itb.accesses 225754848 # DTB accesses +system.cpu1.numCycles 837975509 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 453450144 # Number of instructions committed -system.cpu1.committedOps 532984432 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 47678042 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5221 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 94048897478 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.021341 # CPI: cycles per instruction -system.cpu1.ipc 0.494721 # IPC: instructions per cycle +system.cpu1.committedInsts 416666374 # Number of instructions committed +system.cpu1.committedOps 490559113 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 42698463 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4659 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93986622085 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.011143 # CPI: cycles per instruction +system.cpu1.ipc 0.497230 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5293 # number of quiesce instructions executed -system.cpu1.tickCycles 728135326 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 188442148 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5347951 # number of replacements -system.cpu1.dcache.tags.tagsinuse 430.817141 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 158458993 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5348463 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.627015 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8387659413500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.817141 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.841440 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.841440 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 5009 # number of quiesce instructions executed +system.cpu1.tickCycles 670350336 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 167625173 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 4806043 # number of replacements +system.cpu1.dcache.tags.tagsinuse 444.186980 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 146495712 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4806555 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.478318 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8387638822500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 444.186980 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.867553 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.867553 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 335833986 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 335833986 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 81837847 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 81837847 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 72225758 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 72225758 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 239509 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 239509 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 145455 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 145455 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1785819 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1785819 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1759762 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1759762 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 154063605 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 154063605 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 154303114 # number of overall hits -system.cpu1.dcache.overall_hits::total 154303114 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3469404 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3469404 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2254005 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2254005 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 641263 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 641263 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 468533 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 468533 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 172541 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 172541 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 196757 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 196757 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5723409 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5723409 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6364672 # number of overall misses -system.cpu1.dcache.overall_misses::total 6364672 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 51425230000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 51425230000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 38096829500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 38096829500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16555952500 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 16555952500 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2623224000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2623224000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4131954500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4131954500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2147500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2147500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 89522059500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 89522059500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 89522059500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 89522059500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 85307251 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 85307251 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 74479763 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 74479763 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 880772 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 880772 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 613988 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 613988 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1958360 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1958360 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1956519 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1956519 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 159787014 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 159787014 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 160667786 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 160667786 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040670 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.040670 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030263 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030263 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.728069 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.728069 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.763098 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.763098 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088105 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088105 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100565 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100565 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035819 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035819 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039614 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.039614 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14822.496890 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14822.496890 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16901.838949 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16901.838949 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35335.723418 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35335.723418 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15203.482071 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15203.482071 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21000.292239 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21000.292239 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 309963007 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 309963007 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 75874550 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 75874550 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 66435000 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 66435000 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 232604 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 232604 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 157450 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 157450 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1693988 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1693988 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1671438 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1671438 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 142309550 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 142309550 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 142542154 # number of overall hits +system.cpu1.dcache.overall_hits::total 142542154 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3161753 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3161753 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1996683 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1996683 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 552089 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 552089 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 421817 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 421817 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158395 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 158395 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 179133 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 179133 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5158436 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5158436 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5710525 # number of overall misses +system.cpu1.dcache.overall_misses::total 5710525 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43703345000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 43703345000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 33230827500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 33230827500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 13699084500 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 13699084500 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2222797000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2222797000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3749543500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3749543500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3215500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3215500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 76934172500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 76934172500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 76934172500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 76934172500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 79036303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 79036303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 68431683 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 68431683 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 784693 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 784693 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 579267 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 579267 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1852383 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1852383 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1850571 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1850571 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 147467986 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 147467986 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 148252679 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 148252679 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040004 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.040004 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029178 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029178 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.703573 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.703573 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.728191 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.728191 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.085509 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.085509 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096799 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096799 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034980 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034980 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.038519 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.038519 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13822.504478 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13822.504478 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16643.016192 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16643.016192 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 32476.368899 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 32476.368899 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14033.252312 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14033.252312 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20931.617848 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20931.617848 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15641.387764 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15641.387764 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14065.463153 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14065.463153 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14914.243872 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14914.243872 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13472.346676 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13472.346676 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1657,161 +1645,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3440440 # number of writebacks -system.cpu1.dcache.writebacks::total 3440440 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 392659 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 392659 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 925831 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 925831 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 46 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 46 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41204 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41204 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 43 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1318490 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1318490 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1318490 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1318490 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3076745 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3076745 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1328174 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1328174 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 640972 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 640972 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 468487 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 468487 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 131337 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 131337 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 196714 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 196714 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4404919 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4404919 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5045891 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5045891 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5366 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5366 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5280 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5280 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10646 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10646 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41480566500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41480566500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21714665000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21714665000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12811841000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12811841000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16084660000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16084660000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1751023000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1751023000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3933903500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3933903500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1830000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63195231500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 63195231500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 76007072500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 76007072500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 593786000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 593786000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 651165500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 651165500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1244951500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1244951500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036067 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036067 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017833 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017833 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.727739 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.727739 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.763023 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.763023 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067065 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067065 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100543 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100543 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027567 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027567 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031406 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031406 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13481.964381 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13481.964381 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16349.262220 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16349.262220 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19988.144568 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19988.144568 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 34333.204550 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 34333.204550 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13332.290215 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13332.290215 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19998.086054 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19998.086054 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3028608 # number of writebacks +system.cpu1.dcache.writebacks::total 3028608 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 352163 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 352163 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 814004 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 814004 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 37997 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 37997 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 57 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 57 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1166167 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1166167 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1166167 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1166167 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2809590 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2809590 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1182679 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1182679 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 551754 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 551754 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 421759 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 421759 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120398 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120398 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 179076 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 179076 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 3992269 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 3992269 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4544023 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4544023 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8249 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8249 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 8420 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 8420 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 16669 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 16669 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 35216853500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 35216853500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 19067594000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 19067594000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11091696000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 11091696000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 13273963000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 13273963000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1514299000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1514299000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3568894000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3568894000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2841500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2841500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 54284447500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 54284447500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 65376143500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 65376143500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1096081500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1096081500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1226588000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1226588000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2322669500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2322669500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035548 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035548 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017283 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017283 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.703146 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.703146 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.728091 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.728091 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064996 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064996 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096768 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096768 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027072 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027072 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030651 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030651 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12534.516958 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12534.516958 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16122.374710 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16122.374710 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20102.610946 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20102.610946 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 31472.862464 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 31472.862464 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.443147 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12577.443147 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19929.493623 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19929.493623 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14346.513863 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14346.513863 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15063.161788 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15063.161788 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110657.100261 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110657.100261 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123326.799242 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 123326.799242 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116940.775878 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116940.775878 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13597.392235 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13597.392235 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14387.282701 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14387.282701 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 132874.469633 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 132874.469633 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145675.534442 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 145675.534442 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 139340.662307 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 139340.662307 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 9156821 # number of replacements -system.cpu1.icache.tags.tagsinuse 506.982135 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 237244674 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9157333 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.907617 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8375787773000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.982135 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990199 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990199 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 8962341 # number of replacements +system.cpu1.icache.tags.tagsinuse 506.974355 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 216525917 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8962853 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 24.158147 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8375817756000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.974355 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990184 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990184 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 501961349 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 501961349 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 237244674 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 237244674 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 237244674 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 237244674 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 237244674 # number of overall hits -system.cpu1.icache.overall_hits::total 237244674 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 9157334 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 9157334 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 9157334 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 9157334 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 9157334 # number of overall misses -system.cpu1.icache.overall_misses::total 9157334 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 90409615500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 90409615500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 90409615500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 90409615500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 90409615500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 90409615500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 246402008 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 246402008 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 246402008 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 246402008 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 246402008 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 246402008 # 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average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9872.918854 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 459940393 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 459940393 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 216525917 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 216525917 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 216525917 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 216525917 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 216525917 # number of overall hits +system.cpu1.icache.overall_hits::total 216525917 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8962853 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8962853 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8962853 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 8962853 # 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average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9759.773534 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9759.773534 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9759.773534 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9759.773534 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1820,257 +1808,254 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9157334 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9157334 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9157334 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 9157334 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 9157334 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 9157334 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8962853 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 8962853 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 8962853 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 8962853 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 8962853 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 8962853 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85830949000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 85830949000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85830949000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 85830949000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85830949000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 85830949000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8848000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8848000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8848000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8848000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037164 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.037164 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037164 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.037164 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9372.918908 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9372.918908 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9372.918908 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9372.918908 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95139.784946 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95139.784946 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95139.784946 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 82993989000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 82993989000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 82993989000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 82993989000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 82993989000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 82993989000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8742000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8742000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8742000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8742000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039749 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039749 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039749 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.039749 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039749 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.039749 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9259.773534 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9259.773534 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9259.773534 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9259.773534 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9259.773534 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9259.773534 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94000 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94000 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7355033 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7356454 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 1193 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6768411 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6768469 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 54 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 921370 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2420449 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13525.501015 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 25921683 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2436577 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 10.638565 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9890893366500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5242.566110 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 80.941753 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.247702 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3561.549924 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3753.026790 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 801.168735 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.319981 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004940 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005264 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.217380 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229067 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048899 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.825531 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1192 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14878 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 534 # 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mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245384 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.223033 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.223033 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.081982 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081982 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255225 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255225 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.600626 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.600626 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022925 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050459 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.081982 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.248089 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132643 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022925 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050459 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.081982 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.248089 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.185012 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33000.974564 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42844.691183 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20281.638720 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20281.638720 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.862293 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15343.862293 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 376499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 376499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33349.967224 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33349.967224 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22153.141840 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25787.655901 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25787.655901 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45475.391737 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45475.391737 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27206.226770 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25299.806196 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27206.226770 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29868.845908 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102654.211703 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102389.906576 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 115826.041667 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 115826.041667 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109186.924667 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 108995.995903 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.176468 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22829.961111 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30634.755737 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30634.755737 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20238.984356 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20238.984356 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15250.222823 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15250.222823 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 398416.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 398416.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29763.899302 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29763.899302 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 21893.896751 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 21893.896751 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 22795.864026 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22795.864026 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 39429.951241 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 39429.951241 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21893.896751 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24184.423623 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23267.710276 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21893.896751 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24184.423623 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30634.755737 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25097.274457 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86000 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 124871.863256 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 124438.503956 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 138175.178147 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 138175.178147 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86000 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 131591.757154 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 131338.802052 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 927149 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13939785 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5280 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 7136333 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 14143122 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1073027 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 445884 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 351130 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 465721 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1873672 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1132302 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9157334 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6348630 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 574099 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 467371 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27470555 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17217135 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368278 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1176846 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 46232814 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 586075264 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 544882505 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1351280 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4317584 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1136626633 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 12009621 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 42070384 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.298426 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.457567 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 832335 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13281124 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38305 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 8420 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 6193652 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 13562835 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 802874 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 426908 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 320139 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 432313 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1723284 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 998712 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8962853 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5808138 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 527324 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 420340 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26886674 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15523980 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 318688 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1026227 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 43755569 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 573628544 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 486175782 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1136136 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3690912 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1064631374 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 10738560 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 39200977 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.285389 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.451600 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 29515487 70.16% 70.16% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 12554897 29.84% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 28013450 71.46% 71.46% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 11187527 28.54% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 42070384 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 18619089977 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 39200977 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 17410316483 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 181245984 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 171564976 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13738184900 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13446378573 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7905383000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7120820957 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 199375485 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 176677986 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 637173449 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 564893937 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40322 # Transaction distribution -system.iobus.trans_dist::ReadResp 40322 # Transaction distribution -system.iobus.trans_dist::WriteReq 136608 # Transaction distribution -system.iobus.trans_dist::WriteResp 136608 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47696 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40371 # Transaction distribution +system.iobus.trans_dist::ReadResp 40371 # Transaction distribution +system.iobus.trans_dist::WriteReq 136979 # Transaction distribution +system.iobus.trans_dist::WriteResp 136979 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47802 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2318,18 +2299,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122578 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231202 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231202 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231676 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231676 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353860 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47716 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47822 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2339,18 +2320,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155708 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496618 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36211000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513101 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36314000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2370,7 +2351,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 22142000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2378,71 +2359,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 569805082 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 570865133 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92701000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92952000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147898000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148116000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115582 # number of replacements -system.iocache.tags.tagsinuse 11.293791 # Cycle average of tags in use +system.iocache.tags.replacements 115819 # number of replacements +system.iocache.tags.tagsinuse 11.287255 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115598 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115835 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9174209621000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.830929 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.462862 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239433 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466429 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705862 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9174218723000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.836610 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.450645 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239788 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465665 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705453 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040766 # Number of tag accesses -system.iocache.tags.data_accesses 1040766 # Number of data accesses +system.iocache.tags.tag_accesses 1042899 # Number of tag accesses +system.iocache.tags.data_accesses 1042899 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8873 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8910 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8854 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8891 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8873 # number of demand (read+write) misses -system.iocache.demand_misses::total 8913 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8854 # number of demand (read+write) misses +system.iocache.demand_misses::total 8894 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8873 # number of overall misses -system.iocache.overall_misses::total 8913 # number of overall misses +system.iocache.overall_misses::realview.ide 8854 # number of overall misses +system.iocache.overall_misses::total 8894 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1631093968 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1636288968 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1658968057 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1664163057 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12624582114 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12624582114 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12654105076 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12654105076 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1631093968 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1636657968 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1658968057 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1664532057 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1631093968 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1636657968 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1658968057 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1664532057 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8873 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8854 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8891 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8873 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8913 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8854 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8894 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8873 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8913 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8854 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8894 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2457,54 +2438,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183826.661558 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183646.348822 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 187369.331037 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 187173.890114 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118287.442040 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118287.442040 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118280.351043 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118280.351043 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 183826.661558 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183625.936048 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 187369.331037 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 187152.243872 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 183826.661558 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183625.936048 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31363 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 187369.331037 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 187152.243872 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32802 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3550 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3449 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.834648 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.510583 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106950 # number of writebacks +system.iocache.writebacks::total 106950 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8873 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8854 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8891 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8873 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8913 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8854 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8873 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8913 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8854 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8894 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1187443968 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1190788968 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1216268057 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1219613057 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7288182114 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7288182114 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7304905076 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7304905076 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1187443968 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1191007968 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1216268057 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1219832057 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1187443968 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1191007968 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1216268057 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1219832057 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2519,613 +2500,614 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133826.661558 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133646.348822 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137369.331037 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 137173.890114 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68287.442040 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68287.442040 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68280.351043 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68280.351043 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 133826.661558 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 133625.936048 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 137369.331037 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 137152.243872 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 133826.661558 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 133625.936048 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 137369.331037 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 137152.243872 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1460315 # number of replacements -system.l2c.tags.tagsinuse 63815.106569 # Cycle average of tags in use -system.l2c.tags.total_refs 6243583 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1520944 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.105071 # Average number of references to valid blocks. +system.l2c.tags.replacements 1146599 # number of replacements +system.l2c.tags.tagsinuse 63894.227459 # Cycle average of tags in use +system.l2c.tags.total_refs 5787888 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1208030 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.791179 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17020.262251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 105.114677 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 114.825043 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4617.432955 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6910.402402 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7514.168760 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 272.316465 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 336.862323 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3976.770964 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9922.626808 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13024.323921 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.259709 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001604 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001752 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070456 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.105444 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.114657 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004155 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.005140 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.060681 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.151407 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.198735 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.973741 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9634 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 233 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50762 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 214 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 450 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 8970 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 232 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2000 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4985 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 43502 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.147003 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003555 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.774567 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 74931302 # Number of tag accesses -system.l2c.tags.data_accesses 74931302 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2473005 # number of Writeback hits -system.l2c.Writeback_hits::total 2473005 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 29717 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 30251 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 59968 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5861 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6611 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12472 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 174264 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 168948 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 343212 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6955 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5054 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 704009 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 596815 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 296922 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6236 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4142 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 738933 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 577563 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 321187 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3257816 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6955 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5054 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 704009 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 771079 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 296922 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6236 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4142 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 738933 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 746511 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 321187 # number of demand (read+write) hits -system.l2c.demand_hits::total 3601028 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6955 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5054 # number of overall hits -system.l2c.overall_hits::cpu0.inst 704009 # number of overall hits -system.l2c.overall_hits::cpu0.data 771079 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 296922 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6236 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4142 # number of overall hits -system.l2c.overall_hits::cpu1.inst 738933 # number of overall hits -system.l2c.overall_hits::cpu1.data 746511 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 321187 # number of overall hits -system.l2c.overall_hits::total 3601028 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 43094 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 44585 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 87679 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 8745 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 9538 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 18283 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 499472 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 152688 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 652160 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1944 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1581 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 73537 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 135426 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 239395 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2244 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2077 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 50651 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 119141 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 208595 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 834591 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1944 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1581 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 73537 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 634898 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 239395 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2244 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2077 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 50651 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 271829 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 208595 # number of demand (read+write) misses -system.l2c.demand_misses::total 1486751 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1944 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1581 # number of overall misses -system.l2c.overall_misses::cpu0.inst 73537 # number of overall misses -system.l2c.overall_misses::cpu0.data 634898 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 239395 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2244 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2077 # number of overall misses -system.l2c.overall_misses::cpu1.inst 50651 # number of overall misses -system.l2c.overall_misses::cpu1.data 271829 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 208595 # number of overall misses -system.l2c.overall_misses::total 1486751 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 260324500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 277994500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 538319000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 55253500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 54480000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 109733500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 46824185500 # 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number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 10504090000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 25273313307 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 89739250464 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 176295500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 146583500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 6133823500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 59168136500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 30575603157 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 201877500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 184505000 # 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number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4199208000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 23680637500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 25273313307 # number of overall miss cycles -system.l2c.overall_miss_latency::total 149739983464 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 2473005 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2473005 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 72811 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 74836 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 147647 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 14606 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 16149 # 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number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6219 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 789584 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1018340 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 529782 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 5087779 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.591861 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.595769 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.593842 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.598727 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590625 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.594472 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5124.698853 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.313147 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002470 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002871 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.107565 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.172875 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.153686 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001400 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001721 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.074723 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.066293 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.078197 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.974949 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10689 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 178 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50564 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 577 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 2554 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 7550 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 172 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1822 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 12846 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 35586 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.163101 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.002716 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.771545 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 67839853 # Number of tag accesses +system.l2c.tags.data_accesses 67839853 # Number of data accesses +system.l2c.Writeback_hits::writebacks 2183647 # number of Writeback hits +system.l2c.Writeback_hits::total 2183647 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 31153 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 25605 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 56758 # 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mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20756.292378 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20754.499630 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20755.371854 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20795.376121 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20809.866828 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20802.436003 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83943.195795 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74223.474071 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 82020.434196 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72295.516891 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78472.966724 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72080.078821 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 76710.913302 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86023.056630 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72295.516891 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82838.998772 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72080.078821 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75193.955857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86023.056630 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153783.741865 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84684.936614 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96859.005197 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148672.360201 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 98824.053030 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141763.341646 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153867.338482 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 106897.235358 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96814.419762 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147308.265016 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 121174.524941 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141563.686203 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151230.657412 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91698.703495 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 110147.934372 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 150603.202225 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 114109.977800 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 110091.472766 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 90631 # Transaction distribution -system.membus.trans_dist::ReadResp 933772 # Transaction distribution -system.membus.trans_dist::WriteReq 38095 # Transaction distribution -system.membus.trans_dist::WriteResp 38095 # Transaction distribution -system.membus.trans_dist::Writeback 1222852 # Transaction distribution -system.membus.trans_dist::CleanEvict 259291 # Transaction distribution -system.membus.trans_dist::UpgradeReq 429274 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 300804 # Transaction distribution -system.membus.trans_dist::UpgradeResp 113465 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 664837 # Transaction distribution -system.membus.trans_dist::ReadExResp 644660 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 843141 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122578 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 90799 # Transaction distribution +system.membus.trans_dist::ReadResp 698902 # Transaction distribution +system.membus.trans_dist::WriteReq 38305 # Transaction distribution +system.membus.trans_dist::WriteResp 38305 # Transaction distribution +system.membus.trans_dist::Writeback 981364 # Transaction distribution +system.membus.trans_dist::CleanEvict 209019 # Transaction distribution +system.membus.trans_dist::UpgradeReq 434160 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 274076 # Transaction distribution +system.membus.trans_dist::UpgradeResp 111283 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 609626 # Transaction distribution +system.membus.trans_dist::ReadExResp 589528 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 608103 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106984 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122944 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24884 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5299387 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5446901 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5789694 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155708 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25274 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4403229 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4551499 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343039 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 343039 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4894538 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155959 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 169409152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 169615952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7274560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7274560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 176890512 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 639479 # Total snoops (count) -system.membus.snoop_fanout::samples 3957833 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50548 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 135367808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 135575639 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7275904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7275904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 142851543 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 619953 # Total snoops (count) +system.membus.snoop_fanout::samples 3354848 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3957833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3354848 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3957833 # Request fanout histogram -system.membus.reqLayer0.occupancy 109447997 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3354848 # Request fanout histogram +system.membus.reqLayer0.occupancy 109588500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20601500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21072500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8645644788 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6982752656 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8381282870 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6858580357 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 229327995 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229669194 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3169,46 +3151,46 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 90633 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5042509 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38095 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3695900 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1651242 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 481742 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 313276 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 795018 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 104 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1145784 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1145784 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4959107 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8783138 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7404481 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16187619 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 270950615 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 216626041 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 487576656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3318184 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 13892424 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.121763 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.327012 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 90801 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4609563 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38305 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38305 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3165042 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1502795 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 483481 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 285744 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 769225 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 105 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 105 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1092976 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1092976 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4526002 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8264892 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6572319 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 14837211 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254099969 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185036822 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 439136791 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2966852 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 12598332 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.109406 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.312147 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 12200843 87.82% 87.82% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1691581 12.18% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 11220005 89.06% 89.06% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1378327 10.94% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13892424 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8859040198 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 12598332 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8167142441 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2520000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2478499 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5187778836 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4888169243 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4493465928 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4052371405 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |