diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 5404 |
1 files changed, 2739 insertions, 2665 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index e615eccd3..3367a33d1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.454492 # Number of seconds simulated -sim_ticks 47454492026000 # Number of ticks simulated -final_tick 47454492026000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.535940 # Number of seconds simulated +sim_ticks 47535940136000 # Number of ticks simulated +final_tick 47535940136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 326065 # Simulator instruction rate (inst/s) -host_op_rate 383423 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16260643539 # Simulator tick rate (ticks/s) -host_mem_usage 772552 # Number of bytes of host memory used -host_seconds 2918.37 # Real time elapsed on the host -sim_insts 951575519 # Number of instructions simulated -sim_ops 1118968402 # Number of ops (including micro ops) simulated +host_inst_rate 225035 # Simulator instruction rate (inst/s) +host_op_rate 264677 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11911388135 # Simulator tick rate (ticks/s) +host_mem_usage 769700 # Number of bytes of host memory used +host_seconds 3990.80 # Real time elapsed on the host +sim_insts 898069628 # Number of instructions simulated +sim_ops 1056270581 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 233088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 210624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7916672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 17537736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 18153728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 166400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 132160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3894272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 12497872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 21171968 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 432064 # Number of bytes read from this memory -system.physmem.bytes_read::total 82346584 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7916672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3894272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11810944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 92922304 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 89728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 8161024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14243656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 14782784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 150400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 127744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3048640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9523856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12507584 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 413056 # Number of bytes read from this memory +system.physmem.bytes_read::total 63147416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 8161024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3048640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11209664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75703424 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 92942888 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3642 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3291 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 123698 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 274040 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 283652 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 60848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 195292 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 330812 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6751 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1286691 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1451911 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 75724008 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1402 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 127516 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 222570 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 230981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2350 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1996 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 47635 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 148823 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 195431 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6454 # Number of read requests responded to by this memory +system.physmem.num_reads::total 986704 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1182866 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1454485 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4912 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 4438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 166827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 369570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 382550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 82063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 263365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 446153 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1735275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 166827 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 82063 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 248890 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1958135 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1185440 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 171681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 299640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 310981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 200351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 263118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8689 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1328414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 171681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64133 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 235815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1592551 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1958569 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1958135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4912 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 4438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 166827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 370003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 382550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 82063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 263365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 446153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9105 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3693844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1286691 # Number of read requests accepted -system.physmem.writeReqs 1454485 # Number of write requests accepted -system.physmem.readBursts 1286691 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1454485 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 82317440 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 30784 # Total number of bytes read from write queue -system.physmem.bytesWritten 92941888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 82346584 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 92942888 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 481 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1592984 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1592551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 171681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 300073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 310981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 200351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 263118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8689 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2921398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 986704 # Number of read requests accepted +system.physmem.writeReqs 1185440 # Number of write requests accepted +system.physmem.readBursts 986704 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1185440 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 63115328 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 33728 # Total number of bytes read from write queue +system.physmem.bytesWritten 75722560 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 63147416 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 75724008 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 527 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2258 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 68545 # Per bank write bursts -system.physmem.perBankRdBursts::1 77862 # Per bank write bursts -system.physmem.perBankRdBursts::2 76461 # Per bank write bursts -system.physmem.perBankRdBursts::3 81936 # Per bank write bursts -system.physmem.perBankRdBursts::4 74664 # Per bank write bursts -system.physmem.perBankRdBursts::5 81822 # Per bank write bursts -system.physmem.perBankRdBursts::6 81067 # Per bank write bursts -system.physmem.perBankRdBursts::7 83827 # Per bank write bursts -system.physmem.perBankRdBursts::8 73756 # Per bank write bursts -system.physmem.perBankRdBursts::9 133954 # Per bank write bursts -system.physmem.perBankRdBursts::10 75964 # Per bank write bursts -system.physmem.perBankRdBursts::11 77586 # Per bank write bursts -system.physmem.perBankRdBursts::12 69247 # Per bank write bursts -system.physmem.perBankRdBursts::13 78127 # Per bank write bursts -system.physmem.perBankRdBursts::14 73347 # Per bank write bursts -system.physmem.perBankRdBursts::15 78045 # Per bank write bursts -system.physmem.perBankWrBursts::0 83788 # Per bank write bursts -system.physmem.perBankWrBursts::1 90226 # Per bank write bursts -system.physmem.perBankWrBursts::2 90168 # Per bank write bursts -system.physmem.perBankWrBursts::3 95983 # Per bank write bursts -system.physmem.perBankWrBursts::4 89513 # Per bank write bursts -system.physmem.perBankWrBursts::5 93413 # Per bank write bursts -system.physmem.perBankWrBursts::6 92742 # Per bank write bursts -system.physmem.perBankWrBursts::7 93553 # Per bank write bursts -system.physmem.perBankWrBursts::8 87937 # Per bank write bursts -system.physmem.perBankWrBursts::9 94416 # Per bank write bursts -system.physmem.perBankWrBursts::10 91588 # Per bank write bursts -system.physmem.perBankWrBursts::11 94818 # Per bank write bursts -system.physmem.perBankWrBursts::12 85405 # Per bank write bursts -system.physmem.perBankWrBursts::13 92349 # Per bank write bursts -system.physmem.perBankWrBursts::14 86484 # Per bank write bursts -system.physmem.perBankWrBursts::15 89834 # Per bank write bursts +system.physmem.perBankRdBursts::0 63842 # Per bank write bursts +system.physmem.perBankRdBursts::1 66317 # Per bank write bursts +system.physmem.perBankRdBursts::2 58522 # Per bank write bursts +system.physmem.perBankRdBursts::3 64863 # Per bank write bursts +system.physmem.perBankRdBursts::4 59095 # Per bank write bursts +system.physmem.perBankRdBursts::5 67998 # Per bank write bursts +system.physmem.perBankRdBursts::6 58322 # Per bank write bursts +system.physmem.perBankRdBursts::7 56006 # Per bank write bursts +system.physmem.perBankRdBursts::8 52486 # Per bank write bursts +system.physmem.perBankRdBursts::9 111449 # Per bank write bursts +system.physmem.perBankRdBursts::10 50777 # Per bank write bursts +system.physmem.perBankRdBursts::11 58061 # Per bank write bursts +system.physmem.perBankRdBursts::12 51458 # Per bank write bursts +system.physmem.perBankRdBursts::13 52890 # Per bank write bursts +system.physmem.perBankRdBursts::14 54883 # Per bank write bursts +system.physmem.perBankRdBursts::15 59208 # Per bank write bursts +system.physmem.perBankWrBursts::0 77123 # Per bank write bursts +system.physmem.perBankWrBursts::1 81948 # Per bank write bursts +system.physmem.perBankWrBursts::2 74623 # Per bank write bursts +system.physmem.perBankWrBursts::3 80009 # Per bank write bursts +system.physmem.perBankWrBursts::4 75007 # Per bank write bursts +system.physmem.perBankWrBursts::5 80611 # Per bank write bursts +system.physmem.perBankWrBursts::6 72005 # Per bank write bursts +system.physmem.perBankWrBursts::7 72012 # Per bank write bursts +system.physmem.perBankWrBursts::8 68266 # Per bank write bursts +system.physmem.perBankWrBursts::9 73887 # Per bank write bursts +system.physmem.perBankWrBursts::10 67546 # Per bank write bursts +system.physmem.perBankWrBursts::11 72517 # Per bank write bursts +system.physmem.perBankWrBursts::12 68786 # Per bank write bursts +system.physmem.perBankWrBursts::13 69993 # Per bank write bursts +system.physmem.perBankWrBursts::14 72865 # Per bank write bursts +system.physmem.perBankWrBursts::15 75967 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 36 # Number of times write queue was full causing retry -system.physmem.totGap 47454489913500 # Total gap between requests +system.physmem.numWrRetry 44 # Number of times write queue was full causing retry +system.physmem.totGap 47535938023500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1286661 # Read request sizes (log2) +system.physmem.readPktSize::6 986674 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1451911 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 827173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 164897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 63225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 47515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 40751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 37481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 26328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 5741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2483 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1354 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 527 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 427 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1182866 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 668450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 115815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 26396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 23877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 21311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,167 +188,166 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 34612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 41901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 58265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 63048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 69768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 73771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 78937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 85048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 89045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 90562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 92833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 96249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 94408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 95986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 105469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 93952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 86808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 83066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 37996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 51637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 64761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 68893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 71932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 72504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 73761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 76926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 74288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 75236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 82718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 73770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 68266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 65794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 174 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 99 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1224605 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 143.114986 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 97.246112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 190.672457 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 830563 67.82% 67.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 233051 19.03% 86.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 57759 4.72% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27718 2.26% 93.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20623 1.68% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13112 1.07% 96.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7173 0.59% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5754 0.47% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 28852 2.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1224605 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 77530 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.589449 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 141.842916 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 77527 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::58 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 135 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 984595 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 141.009629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 96.339121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 189.114371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 670707 68.12% 68.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 190612 19.36% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44448 4.51% 91.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20648 2.10% 94.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14900 1.51% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9763 0.99% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5507 0.56% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4424 0.45% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23586 2.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 984595 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61315 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.083617 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 159.391032 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61313 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 77530 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 77530 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.731033 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.088703 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.268543 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 64617 83.34% 83.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 6035 7.78% 91.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 3056 3.94% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1620 2.09% 97.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 474 0.61% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 277 0.36% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 269 0.35% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 83 0.11% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 290 0.37% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 69 0.09% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 30 0.04% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 52 0.07% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 249 0.32% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 33 0.04% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 40 0.05% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 110 0.14% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 167 0.22% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 77530 # Writes before turning the bus around for reads -system.physmem.totQLat 47048753044 # Total ticks spent queuing -system.physmem.totMemAccLat 71165190544 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6431050000 # Total ticks spent in databus transfers -system.physmem.avgQLat 36579.37 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 61315 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61315 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.296502 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.510563 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.190386 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 48917 79.78% 79.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 5503 8.97% 88.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 3053 4.98% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1653 2.70% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 478 0.78% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 276 0.45% 97.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 266 0.43% 98.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 90 0.15% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 261 0.43% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 71 0.12% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 38 0.06% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 55 0.09% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 246 0.40% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 32 0.05% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 47 0.08% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 108 0.18% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 156 0.25% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 24 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 11 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 6 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 8 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61315 # Writes before turning the bus around for reads +system.physmem.totQLat 31916274746 # Total ticks spent queuing +system.physmem.totMemAccLat 50407093496 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4930885000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32363.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 55329.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.74 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.96 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51113.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.33 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.33 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.33 # Average write queue length when enqueuing -system.physmem.readRowHits 962295 # Number of row buffer hits during reads -system.physmem.writeRowHits 551527 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.98 # Row buffer hit rate for writes -system.physmem.avgGap 17311726.76 # Average gap between requests -system.physmem.pageHitRate 55.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4656869280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2540950500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4884235200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4726421280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1219171959180 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27403246221750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31738723386870 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.824424 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45587152483743 # Time in different power states -system.physmem_0.memoryStateTime::REF 1584609520000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing +system.physmem.readRowHits 734466 # Number of row buffer hits during reads +system.physmem.writeRowHits 450279 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.06 # Row buffer hit rate for writes +system.physmem.avgGap 21884340.09 # Average gap between requests +system.physmem.pageHitRate 54.61 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3920933520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2139398250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3860672400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3974430240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1203845511330 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27465556979250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31788114192270 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.717535 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45690953287273 # Time in different power states +system.physmem_0.memoryStateTime::REF 1587329380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 282729931257 # Time in different power states +system.physmem_0.memoryStateTime::ACT 257656491727 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4601144520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2510545125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5148202800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4683944880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1221460881390 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27401238395250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31739139843645 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.833200 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45583769039323 # Time in different power states -system.physmem_1.memoryStateTime::REF 1584609520000 # Time in different power states +system.physmem_1.actEnergy 3522604680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1922056125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3831445800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3692478960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1196085851100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27472363698750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31786234402695 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.677991 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45702273449121 # Time in different power states +system.physmem_1.memoryStateTime::REF 1587329380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 286113375677 # Time in different power states +system.physmem_1.memoryStateTime::ACT 246336261879 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -382,15 +381,19 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 147959066 # Number of BP lookups -system.cpu0.branchPred.condPredicted 105493690 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6448516 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 111296242 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 81329533 # Number of BTB hits +system.cpu0.branchPred.lookups 146462396 # Number of BP lookups +system.cpu0.branchPred.condPredicted 102364881 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6839955 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 108739004 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75372629 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.074824 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17161750 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1109253 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 69.315173 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17612403 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1195732 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 3915449 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2665463 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1249986 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 447212 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -421,64 +424,62 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 300034 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 300034 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11904 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91094 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 300034 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 300034 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 300034 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 102998 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 24703.863182 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21663.255890 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 26203.116698 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 100872 97.94% 97.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 180 0.17% 98.11% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1639 1.59% 99.70% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 73 0.07% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 76 0.07% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 46 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 69 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 28 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 102998 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 302048 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 302048 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10564 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84260 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 302048 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 302048 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 302048 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 94824 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22896.634818 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21259.302446 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 17613.215135 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 93928 99.06% 99.06% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 167 0.18% 99.23% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 600 0.63% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 32 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 34 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 94824 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 91094 88.44% 88.44% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11904 11.56% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 102998 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 300034 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 84260 88.86% 88.86% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10564 11.14% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 94824 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302048 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 300034 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 102998 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302048 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94824 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 102998 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 403032 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94824 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 396872 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 94891169 # DTB read hits -system.cpu0.dtb.read_misses 247198 # DTB read misses -system.cpu0.dtb.write_hits 84318368 # DTB write hits -system.cpu0.dtb.write_misses 52836 # DTB write misses -system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 94909868 # DTB read hits +system.cpu0.dtb.read_misses 253021 # DTB read misses +system.cpu0.dtb.write_hits 83284387 # DTB write hits +system.cpu0.dtb.write_misses 49027 # DTB write misses +system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 40307 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1747 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9392 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 38313 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2113 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 10577 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 12141 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 95138367 # DTB read accesses -system.cpu0.dtb.write_accesses 84371204 # DTB write accesses +system.cpu0.dtb.perms_faults 10792 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 95162889 # DTB read accesses +system.cpu0.dtb.write_accesses 83333414 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 179209537 # DTB hits -system.cpu0.dtb.misses 300034 # DTB misses -system.cpu0.dtb.accesses 179509571 # DTB accesses +system.cpu0.dtb.hits 178194255 # DTB hits +system.cpu0.dtb.misses 302048 # DTB misses +system.cpu0.dtb.accesses 178496303 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -508,187 +509,228 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 71231 # Table walker walks requested -system.cpu0.itb.walker.walksLong 71231 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 667 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60897 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 71231 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 71231 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 71231 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 61564 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 29116.975830 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24576.932577 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 30900.488305 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 59287 96.30% 96.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 14 0.02% 96.32% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 2011 3.27% 99.59% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 94 0.15% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 85 0.14% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 46 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 61564 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 66529 # Table walker walks requested +system.cpu0.itb.walker.walksLong 66529 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 603 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54822 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 66529 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 66529 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 66529 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 55425 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25786.567433 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23469.117152 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 20785.804114 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 51379 92.70% 92.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3140 5.67% 98.37% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 12 0.02% 98.39% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.39% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 536 0.97% 99.36% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 270 0.49% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 8 0.01% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 15 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 29 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 55425 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 60897 98.92% 98.92% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 667 1.08% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 61564 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 54822 98.91% 98.91% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 603 1.09% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 55425 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 71231 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 71231 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66529 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66529 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61564 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61564 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 132795 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 264582301 # ITB inst hits -system.cpu0.itb.inst_misses 71231 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55425 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55425 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 121954 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 260612167 # ITB inst hits +system.cpu0.itb.inst_misses 66529 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28772 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 27578 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 223649 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 178681 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 264653532 # ITB inst accesses -system.cpu0.itb.hits 264582301 # DTB hits -system.cpu0.itb.misses 71231 # DTB misses -system.cpu0.itb.accesses 264653532 # DTB accesses -system.cpu0.numCycles 1106984671 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 260678696 # ITB inst accesses +system.cpu0.itb.hits 260612167 # DTB hits +system.cpu0.itb.misses 66529 # DTB misses +system.cpu0.itb.accesses 260678696 # DTB accesses +system.cpu0.numCycles 1099930824 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 488099503 # Number of instructions committed -system.cpu0.committedOps 574418730 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 50785821 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 5453 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93802885102 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.267949 # CPI: cycles per instruction -system.cpu0.ipc 0.440927 # IPC: instructions per cycle +system.cpu0.committedInsts 487305462 # Number of instructions committed +system.cpu0.committedOps 572197777 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 47186623 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4440 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93972724601 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.257169 # CPI: cycles per instruction +system.cpu0.ipc 0.443033 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 396450876 69.29% 69.29% # Class of committed instruction +system.cpu0.op_class_0::IntMult 1302433 0.23% 69.51% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 64217 0.01% 69.52% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 76920 0.01% 69.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.op_class_0::MemRead 91382938 15.97% 85.51% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 82920392 14.49% 100.00% # Class of committed instruction +system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.op_class_0::total 572197777 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5643 # number of quiesce instructions executed -system.cpu0.tickCycles 789747765 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 317236906 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 6140209 # number of replacements -system.cpu0.dcache.tags.tagsinuse 501.783411 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 169967706 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6140721 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.678787 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 13277 # number of quiesce instructions executed +system.cpu0.tickCycles 780613530 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 319317294 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5972011 # number of replacements +system.cpu0.dcache.tags.tagsinuse 508.033077 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 169168179 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5972523 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.324408 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.783411 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980046 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.980046 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.033077 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992252 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.992252 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 388 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 361643482 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 361643482 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 86800691 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 86800691 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 78258675 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 78258675 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268918 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 268918 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 127943 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 127943 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1971519 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1971519 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1943002 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1943002 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165059366 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 165059366 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165328284 # number of overall hits -system.cpu0.dcache.overall_hits::total 165328284 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3776237 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3776237 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2642039 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2642039 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 748095 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 748095 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 774634 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 774634 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 182353 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 182353 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 209431 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 209431 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6418276 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6418276 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 7166371 # number of overall misses -system.cpu0.dcache.overall_misses::total 7166371 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 71342778500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 71342778500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67996340500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 67996340500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46419090000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 46419090000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3111811500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3111811500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5902963500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5902963500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7077000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7077000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 139339119000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 139339119000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 139339119000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 139339119000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 90576928 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 90576928 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 80900714 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 80900714 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1017013 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1017013 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 902577 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 902577 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2153872 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2153872 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2152433 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2152433 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 171477642 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 171477642 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 172494655 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 172494655 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041691 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.041691 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032658 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.032658 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.735581 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.735581 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.858247 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.858247 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084663 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084663 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097300 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097300 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037429 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.037429 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041545 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.041545 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18892.558518 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 18892.558518 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25736.312182 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25736.312182 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59923.899545 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59923.899545 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17064.767237 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17064.767237 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28185.719879 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28185.719879 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 359361260 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 359361260 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 87043361 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 87043361 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 77242749 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 77242749 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 305030 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 305030 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 287060 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 287060 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877481 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1877481 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1849167 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1849167 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 164286110 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 164286110 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 164591140 # number of overall hits +system.cpu0.dcache.overall_hits::total 164591140 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3693348 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3693348 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2460225 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2460225 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 661742 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 661742 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 847892 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 847892 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173543 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 173543 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200600 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 200600 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 6153573 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6153573 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6815315 # number of overall misses +system.cpu0.dcache.overall_misses::total 6815315 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 64125292500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 64125292500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62047058000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 62047058000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 51167444000 # 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number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 126172350500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 90736709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 90736709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 79702974 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 79702974 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 966772 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 966772 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1134952 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1134952 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2051024 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2051024 # 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number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -697,161 +739,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6140232 # number of writebacks -system.cpu0.dcache.writebacks::total 6140232 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 470815 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 470815 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1099674 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1099674 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 78 # 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mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.858161 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.858161 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063505 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063505 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097275 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097275 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028271 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028271 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032432 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032432 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16949.253530 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16949.253530 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25410.207701 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25410.207701 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27069.479384 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27069.479384 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58921.065746 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58921.065746 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14943.468026 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14943.468026 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27172.479917 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27172.479917 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5972043 # number of writebacks +system.cpu0.dcache.writebacks::total 5972043 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444932 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 444932 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1012331 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1012331 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 90 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 90 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46565 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46565 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 65 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457263 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1457263 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457263 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1457263 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3248416 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3248416 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1447894 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1447894 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 660170 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 660170 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 847802 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 847802 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126978 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126978 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200535 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 200535 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4696310 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4696310 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5356480 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5356480 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31552 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31552 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31148 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31148 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62700 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62700 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50756784000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50756784000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36350818500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36350818500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16579433500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16579433500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 50311370000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 50311370000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1783759500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1783759500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5494928000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5494928000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5416500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5416500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 87107602500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 87107602500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103687036000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 103687036000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6041391000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6041391000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5837295500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5837295500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11878686500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11878686500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035800 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035800 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018166 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018166 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.682860 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.682860 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746994 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746994 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061910 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097833 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097833 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027554 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027554 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031250 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031250 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15625.087427 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15625.087427 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25105.994292 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25105.994292 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25113.885060 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25113.885060 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59343.301856 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59343.301856 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14047.783868 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14047.783868 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27401.341412 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27401.341412 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19641.178645 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19641.178645 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20632.452619 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20632.452619 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175019.156834 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 175019.156834 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171956.278167 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171956.278167 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 173443.838130 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173443.838130 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18548.094674 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18548.094674 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19357.308531 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19357.308531 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191474.106237 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191474.106237 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187405.146398 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187405.146398 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189452.735247 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189452.735247 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 9845680 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.897003 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 254505668 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9846192 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 25.848132 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 33055106000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897003 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 10516028 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.897153 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 249911266 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 10516540 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 23.763640 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 33054279000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897153 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999799 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 538549912 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 538549912 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 254505668 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 254505668 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 254505668 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 254505668 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 254505668 # number of overall hits -system.cpu0.icache.overall_hits::total 254505668 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9846192 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9846192 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9846192 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9846192 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9846192 # number of overall misses -system.cpu0.icache.overall_misses::total 9846192 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 104168962000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 104168962000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 104168962000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 104168962000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 104168962000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 104168962000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 264351860 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 264351860 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 264351860 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 264351860 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 264351860 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 264351860 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037247 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.037247 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037247 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.037247 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037247 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.037247 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10579.619207 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10579.619207 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10579.619207 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10579.619207 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10579.619207 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10579.619207 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 531372181 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 531372181 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 249911266 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 249911266 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 249911266 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 249911266 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 249911266 # number of overall hits +system.cpu0.icache.overall_hits::total 249911266 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 10516550 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 10516550 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 10516550 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 10516550 # 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average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10410.384965 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10410.384965 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10410.384965 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10410.384965 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -860,258 +902,256 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 9845680 # number of writebacks -system.cpu0.icache.writebacks::total 9845680 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9846192 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9846192 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9846192 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9846192 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9846192 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9846192 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 10516028 # number of writebacks +system.cpu0.icache.writebacks::total 10516028 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10516550 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 10516550 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 10516550 # 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number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037247 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.037247 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.037247 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10079.619207 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10079.619207 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10079.619207 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040382 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040382 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040382 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.040382 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040382 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.040382 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9910.385012 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9910.385012 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9910.385012 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9910.385012 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9910.385012 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9910.385012 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8550248 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8550537 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 256 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8036343 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8037705 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 1205 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1111887 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 3055162 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16188.315469 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 24712613 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3070855 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 8.047470 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1038823 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2850300 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16126.746563 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 26039957 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2866458 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 9.084367 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 8707838500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15276.749771 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 63.374129 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 61.193370 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 786.998198 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.932419 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003868 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003735 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.048035 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.988056 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1100 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14511 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 849 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 47 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 34 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 880 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5451 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7600 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.067139 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.885681 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 539634613 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 539634613 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 571667 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 182910 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 754577 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4024953 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4024953 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 11958375 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 11958375 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 880 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 880 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 964239 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 964239 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9075218 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 9075218 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3054625 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 3054625 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 195729 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 195729 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 571667 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 182910 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 9075218 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4018864 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 13848659 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 571667 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 182910 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 9075218 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4018864 # number of overall hits -system.cpu0.l2cache.overall_hits::total 13848659 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 14134 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10093 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 24227 # number of ReadReq misses -system.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses -system.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 274802 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 274802 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 209364 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 209364 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 311346 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 311346 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 770973 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 770973 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1133829 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1133829 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 576566 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 576566 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 14134 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10093 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 770973 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1445175 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2240375 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 14134 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10093 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 770973 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1445175 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2240375 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 807748500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 660476500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1468225000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3585176500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 3585176500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2077487000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2077487000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 6654497 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 6654497 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 20598931500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 20598931500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 29674847500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 29674847500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 51821822989 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 51821822989 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 441045000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 441045000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 807748500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 660476500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 29674847500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 72420754489 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 103563826989 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 807748500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 660476500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 29674847500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 72420754489 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 103563826989 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 585801 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 193003 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 778804 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4024954 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 4024954 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 11958375 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 11958375 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 275682 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 275682 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 209367 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 209367 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1275585 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1275585 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9846191 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 9846191 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4188454 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 4188454 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 772295 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 772295 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 585801 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 193003 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 9846191 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5464039 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 16089034 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 585801 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 193003 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 9846191 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5464039 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 16089034 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024128 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052295 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.031108 # miss rate for ReadReq accesses -system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses -system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.996808 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.996808 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999986 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999986 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 15278.163009 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 75.302883 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 76.950246 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 696.330425 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.932505 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004596 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004697 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.042501 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984298 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1240 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14860 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 522 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 622 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 73 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 43 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1092 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5314 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7823 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 536 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.075684 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.906982 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 554897291 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 554897291 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 569819 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 172472 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 742291 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 3893367 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 3893367 # 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mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.031104 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses -system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11392447500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 18388602500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026408 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996808 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996808 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999986 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999986 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998585 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998585 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236376 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236376 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078301 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270406 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270406 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.746562 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.746562 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.138559 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.224517 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.224517 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071267 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254730 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254730 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728290 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728290 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.125137 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.053996 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61741.289726 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29925.451776 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29925.451776 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19653.868363 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19653.868363 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 557499.727273 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 557499.727273 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57548.640546 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57548.640546 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32489.756980 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39651.911728 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39651.911728 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68676.397845 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 68676.397845 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39758.098096 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46034.137306 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.174585 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35899.796364 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56710.263890 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29958.038116 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29958.038116 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19875.340328 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19875.340328 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 994400 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 994400 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58388.867967 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58388.867967 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33267.758218 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35913.269977 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35913.269977 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70950.838813 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70950.838813 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37874.691491 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43209.493938 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167006.529232 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141191.713035 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164452.679019 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164452.679019 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183468.464757 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152454.084735 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179904.022730 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179904.022730 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165693.017191 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145649.104605 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181697.727273 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159888.378301 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 32897508 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16815136 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2403341 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2402836 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 505 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 933618 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 15066373 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15977 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15976 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5804347 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 11960956 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 3276888 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1153411 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 478642 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 376774 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 550943 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1307095 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1283776 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9846192 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5335526 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 825564 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 772295 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29642681 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19817496 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 405752 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1239273 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 51105202 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1263627520 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 749575419 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1544024 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4686408 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 2019433371 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 8071764 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 25329170 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.108588 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.311185 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 33857668 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 17264460 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3128 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2263959 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2263472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 487 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 924227 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 15578589 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31149 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31148 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5528357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 12594701 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 3060195 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1058289 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 483217 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361321 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 533499 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1230571 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1205955 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10516550 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5115631 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 898497 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 845557 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 31653744 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19358528 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 379556 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1223236 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 52615064 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1349432640 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 724409976 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1445984 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4653440 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 2079942040 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7567377 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 25314697 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.102016 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.302732 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 22579237 89.14% 89.14% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2749428 10.85% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 505 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 22732690 89.80% 89.80% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2581520 10.20% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 487 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 25329170 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 32745453976 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 25314697 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 33752723480 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 192728655 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 205163062 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14851397186 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 15856801952 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8851946898 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8551593856 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 212824349 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 198848419 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 653582276 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 641675758 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 143060728 # Number of BP lookups -system.cpu1.branchPred.condPredicted 103431257 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6108949 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 108043566 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 80039888 # Number of BTB hits +system.cpu1.branchPred.lookups 127453033 # Number of BP lookups +system.cpu1.branchPred.condPredicted 91217282 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5663830 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 96224557 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 67852361 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 74.081124 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 15973583 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1078136 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 70.514600 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 14431851 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 916644 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3338859 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2197659 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1141200 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 412569 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1385,63 +1434,64 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 316205 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 316205 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13111 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 102055 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 316205 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 316205 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 316205 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 115166 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23006.933470 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21361.362420 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 17841.956140 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 114056 99.04% 99.04% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 145 0.13% 99.16% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 815 0.71% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 40 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 32 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 115166 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1788277352 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1788277352 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1788277352 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 102056 88.62% 88.62% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 13111 11.38% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 115167 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 316205 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 261031 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 261031 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9619 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80662 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 261031 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 261031 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 261031 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 90281 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23808.564371 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21471.713865 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 22312.583155 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 88920 98.49% 98.49% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 187 0.21% 98.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 992 1.10% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 43 0.05% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 45 0.05% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 26 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 33 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 21 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 90281 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1786242352 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1786242352 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1786242352 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 80662 89.35% 89.35% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9619 10.65% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 90281 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261031 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 316205 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 115167 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261031 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90281 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 115167 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 431372 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90281 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 351312 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 90416501 # DTB read hits -system.cpu1.dtb.read_misses 263668 # DTB read misses -system.cpu1.dtb.write_hits 78865175 # DTB write hits -system.cpu1.dtb.write_misses 52537 # DTB write misses -system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 80497438 # DTB read hits +system.cpu1.dtb.read_misses 213464 # DTB read misses +system.cpu1.dtb.write_hits 70911031 # DTB write hits +system.cpu1.dtb.write_misses 47567 # DTB write misses +system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 39779 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1900 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9673 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 37751 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1110 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7072 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11862 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 90680169 # DTB read accesses -system.cpu1.dtb.write_accesses 78917712 # DTB write accesses +system.cpu1.dtb.perms_faults 11967 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 80710902 # DTB read accesses +system.cpu1.dtb.write_accesses 70958598 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 169281676 # DTB hits -system.cpu1.dtb.misses 316205 # DTB misses -system.cpu1.dtb.accesses 169597881 # DTB accesses +system.cpu1.dtb.hits 151408469 # DTB hits +system.cpu1.dtb.misses 261031 # DTB misses +system.cpu1.dtb.accesses 151669500 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1471,187 +1521,222 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 61623 # Table walker walks requested -system.cpu1.itb.walker.walksLong 61623 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 682 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 51951 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 61623 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 61623 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 61623 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 52633 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26809.463644 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23734.871548 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 24762.364644 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 51446 97.74% 97.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 9 0.02% 97.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1035 1.97% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 54 0.10% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 44 0.08% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 33 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 52633 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1787261852 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1787261852 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1787261852 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 51951 98.70% 98.70% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 682 1.30% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 52633 # Table walker page sizes translated +system.cpu1.itb.walker.walks 64962 # Table walker walks requested +system.cpu1.itb.walker.walksLong 64962 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 549 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55482 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 64962 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 64962 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 64962 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 56031 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27185.022577 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24059.100661 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 24848.225124 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 54737 97.69% 97.69% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1140 2.03% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 44 0.08% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 63 0.11% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 56031 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1785244852 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1785244852 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1785244852 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 55482 99.02% 99.02% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 549 0.98% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 56031 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61623 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61623 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64962 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64962 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 52633 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 52633 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 114256 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 255703249 # ITB inst hits -system.cpu1.itb.inst_misses 61623 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56031 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56031 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 120993 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 225980528 # ITB inst hits +system.cpu1.itb.inst_misses 64962 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 28254 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26783 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 225386 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 166792 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 255764872 # ITB inst accesses -system.cpu1.itb.hits 255703249 # DTB hits -system.cpu1.itb.misses 61623 # DTB misses -system.cpu1.itb.accesses 255764872 # DTB accesses -system.cpu1.numCycles 1013399126 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 226045490 # ITB inst accesses +system.cpu1.itb.hits 225980528 # DTB hits +system.cpu1.itb.misses 64962 # DTB misses +system.cpu1.itb.accesses 226045490 # DTB accesses +system.cpu1.numCycles 884296043 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 463476016 # Number of instructions committed -system.cpu1.committedOps 544549672 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 51973590 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4681 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93896343891 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.186519 # CPI: cycles per instruction -system.cpu1.ipc 0.457348 # IPC: instructions per cycle +system.cpu1.committedInsts 410764166 # Number of instructions committed +system.cpu1.committedOps 484072804 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 46607969 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5245 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 94188329171 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.152807 # CPI: cycles per instruction +system.cpu1.ipc 0.464510 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 334821764 69.17% 69.17% # Class of committed instruction +system.cpu1.op_class_0::IntMult 956339 0.20% 69.37% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 55233 0.01% 69.38% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 37353 0.01% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.38% # Class of committed instruction +system.cpu1.op_class_0::MemRead 77588616 16.03% 85.41% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 70613457 14.59% 100.00% # Class of committed instruction +system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.op_class_0::total 484072804 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13591 # number of quiesce instructions executed -system.cpu1.tickCycles 759435347 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 253963779 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5640902 # number of replacements -system.cpu1.dcache.tags.tagsinuse 433.747661 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 160682361 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5641413 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.482645 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8381463375500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 433.747661 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.847163 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.847163 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 341448433 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 341448433 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 82699161 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 82699161 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 73240702 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 73240702 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 257576 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 257576 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 197387 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 197387 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1901357 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1901357 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1855769 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1855769 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 155939863 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 155939863 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 156197439 # number of overall hits -system.cpu1.dcache.overall_hits::total 156197439 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3585243 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3585243 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2523734 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2523734 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 738365 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 738365 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 486988 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 486988 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162310 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 162310 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 206438 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 206438 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 6108977 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 6108977 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6847342 # number of overall misses -system.cpu1.dcache.overall_misses::total 6847342 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 60530715500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 60530715500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 58663605500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 58663605500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 22007902000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 22007902000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2738446000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2738446000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5741911000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5741911000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 7112000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 7112000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 119194321000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 119194321000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 119194321000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 119194321000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 86284404 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 86284404 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 75764436 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 75764436 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 995941 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 995941 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 684375 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 684375 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2063667 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2063667 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2062207 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2062207 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 162048840 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 162048840 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 163044781 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 163044781 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041551 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.041551 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033310 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.033310 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.741374 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.741374 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.711581 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.711581 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078651 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078651 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100105 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100105 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037698 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.037698 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041997 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.041997 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16883.295079 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16883.295079 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23244.765692 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 23244.765692 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45191.877418 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45191.877418 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16871.702298 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16871.702298 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27814.215406 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27814.215406 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5362 # number of quiesce instructions executed +system.cpu1.tickCycles 676945147 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 207350896 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5011869 # number of replacements +system.cpu1.dcache.tags.tagsinuse 436.764256 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 143763031 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5012381 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.681585 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8498279834500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 436.764256 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.853055 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.853055 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 305397096 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 305397096 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 73662807 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 73662807 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 66040616 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 66040616 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 200864 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 200864 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 33950 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 33950 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1678906 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1678906 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1638259 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1638259 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 139703423 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 139703423 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 139904287 # number of overall hits +system.cpu1.dcache.overall_hits::total 139904287 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3193197 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3193197 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2277873 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2277873 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 648992 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 648992 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 409957 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 409957 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159945 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 159945 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199493 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 199493 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5471070 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5471070 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6120062 # number of overall misses +system.cpu1.dcache.overall_misses::total 6120062 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52208022500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 52208022500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51224639500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 51224639500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 14899741000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 14899741000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2555092000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2555092000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5532212500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5532212500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5344000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5344000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 103432662000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 103432662000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 103432662000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 103432662000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 76856004 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 76856004 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 68318489 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 68318489 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 849856 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 849856 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 443907 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 443907 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1838851 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1838851 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837752 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1837752 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 145174493 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 145174493 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 146024349 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 146024349 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041548 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.041548 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033342 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.033342 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.763649 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.763649 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.923520 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.923520 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086981 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086981 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108553 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108553 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037686 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.037686 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041911 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.041911 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16349.765611 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16349.765611 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22487.926017 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22487.926017 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36344.643463 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36344.643463 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.816343 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.816343 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27731.361501 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27731.361501 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19511.338969 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19511.338969 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17407.385377 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17407.385377 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18905.380849 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18905.380849 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16900.590550 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16900.590550 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1660,161 +1745,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 5640935 # number of writebacks -system.cpu1.dcache.writebacks::total 5640935 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 429416 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 429416 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1043359 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1043359 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42170 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42170 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 72 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 72 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1472775 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1472775 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1472775 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1472775 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3155827 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3155827 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1480375 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1480375 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 738082 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 738082 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 486914 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 486914 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120140 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120140 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 206366 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 206366 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4636202 # 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number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 47412877500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 34746994000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 34746994000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 19660408500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 19660408500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 21514132500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 21514132500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1774236500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1774236500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5529988500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5529988500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6729000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6729000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82159871500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 82159871500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101820280000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 101820280000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4292810500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4292810500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4172773000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4172773000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8465583500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8465583500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036575 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036575 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019539 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019539 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.741090 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.741090 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.711473 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.711473 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058217 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058217 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100070 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100070 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028610 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028610 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032962 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032962 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.915284 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15023.915284 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23471.751414 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23471.751414 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 26637.160234 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 26637.160234 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44184.666081 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44184.666081 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14768.074746 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14768.074746 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26796.994175 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26796.994175 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5011891 # number of writebacks +system.cpu1.dcache.writebacks::total 5011891 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 367321 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 367321 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 943211 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 943211 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40165 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40165 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 85 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 85 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310532 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1310532 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310532 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1310532 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2825876 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2825876 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1334662 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1334662 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 648629 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 648629 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 409899 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 409899 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119780 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119780 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199408 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 199408 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4160538 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4160538 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4809167 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4809167 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7337 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7337 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7641 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14978 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14978 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41329046000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41329046000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30034339000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30034339000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15914789000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15914789000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14484285500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14484285500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1714801500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1714801500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5327664500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5327664500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4914500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4914500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 71363385000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 71363385000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87278174000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 87278174000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 919733500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 919733500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1094820000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1094820000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2014553500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2014553500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036768 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036768 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019536 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019536 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.763222 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.763222 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.923389 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.923389 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065139 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065139 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108506 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108506 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028659 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028659 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032934 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032934 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14625.215685 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14625.215685 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22503.329682 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22503.329682 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24536.042946 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24536.042946 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35336.230388 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35336.230388 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14316.258975 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14316.258975 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26717.406022 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26717.406022 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17721.374414 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17721.374414 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18945.831668 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18945.831668 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184700.563635 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184700.563635 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187658.436769 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187658.436769 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186146.785259 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186146.785259 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17152.441583 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17152.441583 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18148.293457 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18148.293457 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125355.526782 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125355.526782 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143282.292894 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 143282.292894 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134500.834557 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134500.834557 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 9253909 # number of replacements -system.cpu1.icache.tags.tagsinuse 506.772073 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 246217857 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9254421 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 26.605431 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8381293063000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.772073 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989789 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.989789 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 8449872 # number of replacements +system.cpu1.icache.tags.tagsinuse 506.781387 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 217357255 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8450384 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.721583 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8379180185000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.781387 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989807 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.989807 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 365 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 520199009 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 520199009 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 246217857 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 246217857 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 246217857 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 246217857 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 246217857 # number of overall hits -system.cpu1.icache.overall_hits::total 246217857 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 9254432 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 9254432 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 9254432 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 9254432 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 9254432 # number of overall misses -system.cpu1.icache.overall_misses::total 9254432 # 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average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10569.994463 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10569.994463 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 460065662 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 460065662 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 217357255 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 217357255 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 217357255 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 217357255 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 217357255 # number of overall hits +system.cpu1.icache.overall_hits::total 217357255 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8450384 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8450384 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8450384 # 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number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 225807639 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 225807639 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 225807639 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 225807639 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037423 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.037423 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037423 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.037423 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037423 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.037423 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10439.359501 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10439.359501 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10439.359501 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10439.359501 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10439.359501 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10439.359501 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1823,498 +1908,494 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 9253909 # number of writebacks -system.cpu1.icache.writebacks::total 9253909 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9254432 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9254432 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9254432 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 9254432 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 9254432 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 9254432 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 8449872 # number of writebacks +system.cpu1.icache.writebacks::total 8449872 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8450384 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 8450384 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 8450384 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 8450384 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 8450384 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 8450384 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 93192079500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 93192079500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 93192079500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 93192079500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 93192079500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 93192079500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13081000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13081000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13081000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 13081000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.036225 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.036225 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.036225 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10069.994517 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10069.994517 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10069.994517 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140655.913978 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140655.913978 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 83991404500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 83991404500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 83991404500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 83991404500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 83991404500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 83991404500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13018000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13018000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13018000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 13018000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037423 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037423 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037423 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.037423 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037423 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.037423 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9939.359501 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9939.359501 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9939.359501 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9939.359501 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9939.359501 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9939.359501 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 139978.494624 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 139978.494624 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7972481 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7973767 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 1132 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7137751 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7137894 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 127 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 946401 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2682833 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13443.137658 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 23351564 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2698948 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.652099 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10051011039000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12664.163497 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 64.427658 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 52.788670 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 661.757834 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.772959 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003932 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003222 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.040390 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.820504 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1261 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14808 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 338 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 798 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 120 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id +system.cpu1.l2cache.prefetcher.pfSpanPage 851890 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2314380 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13359.571881 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 21237271 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2330274 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 9.113637 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 10056444277000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 12441.859609 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 52.856295 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.323629 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 805.532348 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.759391 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003226 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003621 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.049166 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.815404 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1023 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14801 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 326 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 596 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 38 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 29 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1053 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5404 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7290 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 973 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076965 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903809 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 504035480 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 504035480 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 619167 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 157082 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 776249 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3580112 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3580112 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 11312106 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 11312106 # 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number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 8504758 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3898988 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 13179995 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 619167 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 157082 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 8504758 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3898988 # number of overall hits -system.cpu1.l2cache.overall_hits::total 13179995 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13008 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8398 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 21406 # number of ReadReq misses -system.cpu1.l2cache.WritebackDirty_misses::writebacks 3 # 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number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 60822460488 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 89896830988 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 644553000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 465440500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 27964377000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 60822460488 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 89896830988 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 632175 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165480 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 797655 # 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number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3827966500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3827966500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4485998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4485998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11549115998 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11549115998 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20322130500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20322130500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 30349496491 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 30349496491 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 11223039500 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 11223039500 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 522984500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 414677500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20322130500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 41898612489 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 63158404989 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 522984500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 414677500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20322130500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 41898612489 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 38779162359 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 101937567348 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12274000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 860931500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 873205500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1037437000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1037437000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12274000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1898368500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1910642500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.031430 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996768 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996768 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997472 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997472 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207689 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207689 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081006 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.269659 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.269659 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.654937 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.654937 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255033 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.137917 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255033 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.237116 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.237116 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.080624 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080624 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.268190 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.268190 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.603347 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.603347 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.080624 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.260882 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139346 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.080624 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.260882 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.195584 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 45855.781359 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 73136.413477 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 73136.413477 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30690.875696 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30690.875696 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19278.434926 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19278.434926 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 681611 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 681611 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 52889.128769 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 52889.128769 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31302.166565 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34082.743167 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34082.743167 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55618.562661 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55618.562661 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 37697.368599 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35508.934910 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 37697.368599 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 73136.413477 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 46603.070327 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176697.508820 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176521.984144 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 180156.075733 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 180156.075733 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178388.539514 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178295.209673 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.194834 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42980.473047 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50482.920781 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30794.884700 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30794.884700 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19197.135951 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19197.135951 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 897199.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 897199.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44069.998428 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44069.998428 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29828.373467 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31486.407700 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31486.407700 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45586.717224 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45586.717224 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32740.287687 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37793.329747 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117341.079460 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117524.293405 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 135772.411988 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 135772.411988 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126743.790893 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126776.093159 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 30687781 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15695228 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2622 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 2305562 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2305078 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 484 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 905031 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 14265709 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 22236 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 22236 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4974934 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 11314728 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 3212624 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1143576 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 456570 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 371810 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 515155 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 96 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1270102 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1247161 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9254432 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5086529 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 540215 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 484636 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27762958 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18273152 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 349398 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1329953 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 47715461 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1184539712 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 703787179 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1323840 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 5057400 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1894708131 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 7537959 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 23658040 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.112405 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.315929 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 27757324 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14199775 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1809 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096264 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095922 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 342 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 778911 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 12918528 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 7641 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7641 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342023 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 10300458 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2852323 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 992320 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 439929 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 359269 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 498097 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1135001 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1111432 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8450384 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4652967 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 462443 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 408042 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25350826 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16287327 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370687 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1094902 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 43103742 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1081622336 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 628052039 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1412064 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4140800 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1715227239 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6782222 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 21311973 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.112849 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.316459 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 20999234 88.76% 88.76% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2658322 11.24% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 484 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 18907277 88.72% 88.72% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2404354 11.28% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 342 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 23658040 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 30538190977 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 21311973 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 27584218481 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 182787124 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 185839513 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13885672200 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 12678955503 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8385983653 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7484332893 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 183975884 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 194250357 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 697921212 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 577391819 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40434 # Transaction distribution -system.iobus.trans_dist::ReadResp 40434 # Transaction distribution -system.iobus.trans_dist::WriteReq 136979 # Transaction distribution -system.iobus.trans_dist::WriteResp 136979 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47874 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40390 # Transaction distribution +system.iobus.trans_dist::ReadResp 40390 # Transaction distribution +system.iobus.trans_dist::WriteReq 136973 # Transaction distribution +system.iobus.trans_dist::WriteResp 136973 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2325,15 +2406,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122964 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231782 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231782 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122924 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231722 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231722 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354826 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47894 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354726 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2344,103 +2425,103 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156002 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155939 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355240 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47273505 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42523001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26273501 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25802501 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36398000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36398001 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568842992 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568577386 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92972000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92938000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148222000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148162000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115872 # number of replacements -system.iocache.tags.tagsinuse 11.252872 # Cycle average of tags in use +system.iocache.tags.replacements 115843 # number of replacements +system.iocache.tags.tagsinuse 11.310828 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115888 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115859 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9138217056000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.833219 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.419652 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239576 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.463728 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.703304 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9138959017000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.826637 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.484190 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239165 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.467762 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706927 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043376 # Number of tag accesses -system.iocache.tags.data_accesses 1043376 # Number of data accesses +system.iocache.tags.tag_accesses 1043106 # Number of tag accesses +system.iocache.tags.data_accesses 1043106 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8907 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8944 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8907 # number of demand (read+write) misses -system.iocache.demand_misses::total 8947 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses +system.iocache.demand_misses::total 8917 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8907 # number of overall misses -system.iocache.overall_misses::total 8947 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5277000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1705079977 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1710356977 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8877 # number of overall misses +system.iocache.overall_misses::total 8917 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1651659585 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1656859085 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13558851015 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13558851015 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5646000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1705079977 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1710725977 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5646000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1705079977 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1710725977 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13563940301 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13563940301 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1651659585 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1657228085 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1651659585 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1657228085 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8907 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8944 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8907 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8947 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8907 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8947 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2454,55 +2535,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142621.621622 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 191431.455821 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 191229.536784 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186060.559311 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 185871.559906 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126737.185140 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126737.185140 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 141150 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 191431.455821 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 191206.658880 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 141150 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 191431.455821 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 191206.658880 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 35119 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126784.755674 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126784.755674 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 185850.407648 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 185850.407648 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32764 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3508 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3385 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.011117 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.679173 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106950 # number of writebacks -system.iocache.writebacks::total 106950 # number of writebacks +system.iocache.writebacks::writebacks 106951 # number of writebacks +system.iocache.writebacks::total 106951 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8907 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8944 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8907 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8947 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8907 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8947 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3427000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1259729977 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1263156977 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1207809585 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1211159085 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8203408528 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8203408528 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3646000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1259729977 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1263375977 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3646000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1259729977 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1263375977 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8208491858 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8208491858 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1207809585 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1211378085 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1207809585 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1211378085 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2516,654 +2597,647 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92621.621622 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141431.455821 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 141229.536784 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136060.559311 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 135871.559906 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76678.835415 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76678.835415 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 91150 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 141431.455821 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 141206.658880 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 91150 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 141431.455821 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 141206.658880 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76726.350277 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76726.350277 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1736304 # number of replacements -system.l2c.tags.tagsinuse 63595.107970 # Cycle average of tags in use -system.l2c.tags.total_refs 7296515 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1796625 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.061234 # Average number of references to valid blocks. +system.l2c.tags.replacements 1387428 # number of replacements +system.l2c.tags.tagsinuse 63551.257518 # Cycle average of tags in use +system.l2c.tags.total_refs 6641936 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1448331 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.585924 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 21438.357602 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.623523 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 216.352807 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5273.180907 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7402.273131 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10592.541457 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 149.822853 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 191.052659 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3264.316466 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6229.486316 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8664.100250 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.327123 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002649 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003301 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080462 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.112950 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.161629 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002286 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002915 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.049810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.095054 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.132204 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.970384 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 8701 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 194 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 51426 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 62 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 67 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 253 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1394 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 6925 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 186 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 389 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2651 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 12885 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 35470 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.132767 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.002960 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.784698 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 90467673 # Number of tag accesses -system.l2c.tags.data_accesses 90467673 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 3161640 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 3161640 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 190042 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 150318 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 340360 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 46175 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 40691 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 86866 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 66080 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 54849 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 120929 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7647 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4987 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 699090 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 694199 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 343045 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6831 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3980 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 688497 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 675339 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 302251 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3425866 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 143577 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 133038 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 276615 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 7647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4987 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 699090 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 760279 # 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average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70566.394621 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73641.009191 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73548.748351 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73596.483261 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 127912.406083 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 128004.597362 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 127951.987161 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131423.037819 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134145.307792 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 150265.373892 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70087.808865 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69270.608839 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69850.417852 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 130299.138826 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 132073.816824 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 147452.086842 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 130299.138826 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 132073.816824 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 147452.086842 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.275862 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.306052 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.290013 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.237874 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.225288 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.231817 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.604734 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.454062 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.535825 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.194759 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.255466 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.100380 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.189967 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.410594 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.245303 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.273125 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.069794 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.145225 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.371856 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.200269 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.779086 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.408078 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.675667 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.194759 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.255466 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100380 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.251652 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.410594 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.245303 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.273125 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.069794 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.188212 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.371856 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.219641 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.194759 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.255466 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100380 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.251652 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.410594 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.245303 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.273125 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.069794 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.188212 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.371856 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.219641 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70511.570770 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70744.197959 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70626.640641 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73589.975384 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73559.456325 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73575.702400 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128404.792537 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123335.036761 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 126439.976478 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124515.989087 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129589.310186 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 164766.720913 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129716.605957 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130685.882265 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124743.086118 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131084.361928 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146034.545309 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69905.751133 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69900.131209 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69904.804990 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124515.989087 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129165.978772 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 164766.720913 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129716.605957 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130685.882265 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124743.086118 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 128482.179649 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 143274.851193 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124515.989087 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129165.978772 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 164766.720913 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129716.605957 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130685.882265 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124743.086118 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128482.179649 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 143274.851193 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 148992.246785 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158707.724699 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130545.300866 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147439.379444 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163149.942166 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156581.535643 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165462.983424 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99350.240900 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129888.689437 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162895.997753 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 118753.507002 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154200.419836 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148193.566448 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160879.796728 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 138261.266457 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164187.760622 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109250.104434 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 137138.398922 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 90728 # Transaction distribution -system.membus.trans_dist::ReadResp 1177835 # Transaction distribution -system.membus.trans_dist::WriteReq 38212 # Transaction distribution -system.membus.trans_dist::WriteResp 38212 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1451911 # Transaction distribution -system.membus.trans_dist::CleanEvict 312799 # Transaction distribution -system.membus.trans_dist::UpgradeReq 438732 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 328709 # Transaction distribution -system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 166722 # Transaction distribution -system.membus.trans_dist::ReadExResp 150087 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1087107 # Transaction distribution -system.membus.trans_dist::InvalidateReq 695373 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122964 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 91289 # Transaction distribution +system.membus.trans_dist::ReadResp 902614 # Transaction distribution +system.membus.trans_dist::WriteReq 38789 # Transaction distribution +system.membus.trans_dist::WriteResp 38789 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1182866 # Transaction distribution +system.membus.trans_dist::CleanEvict 259673 # Transaction distribution +system.membus.trans_dist::UpgradeReq 445486 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 315870 # Transaction distribution +system.membus.trans_dist::UpgradeResp 22 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 143483 # Transaction distribution +system.membus.trans_dist::ReadExResp 126149 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 811325 # Transaction distribution +system.membus.trans_dist::InvalidateReq 668729 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122924 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5587054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5734962 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238554 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238554 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5973516 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156002 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4633500 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4783684 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5021882 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155939 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168012608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 168219718 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276864 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7276864 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 175496582 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 622390 # Total snoops (count) -system.membus.snoop_fanout::samples 4610336 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 131613504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 131825183 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7257920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 139083103 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 621301 # Total snoops (count) +system.membus.snoop_fanout::samples 3957559 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4610336 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3957559 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4610336 # Request fanout histogram -system.membus.reqLayer0.occupancy 110366494 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3957559 # Request fanout histogram +system.membus.reqLayer0.occupancy 105148497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20951999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22946496 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 10147074149 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8356686345 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6858565377 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5285705581 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45617493 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45456154 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3217,53 +3291,53 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 13817515 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 7477037 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2215935 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 187202 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 169247 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 17955 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 90730 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5393978 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38212 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38212 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4613586 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 3368394 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 769711 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 415575 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1185286 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 166 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 331620 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 331620 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 5310492 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 975909 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 868925 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10817825 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9492092 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 20309917 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 274107435 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 237950875 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 512058310 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3424368 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9784683 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.340448 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.477717 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 12610950 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6824430 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2134576 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 142334 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 128133 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 14201 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 91291 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4901304 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38789 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38789 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3987141 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 3034318 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 743952 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 399827 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1143779 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302895 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302895 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4817262 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 944420 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 837436 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10209362 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8295779 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18505141 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250153960 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 205145975 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 455299935 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3080857 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8841930 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.362342 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.484007 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6471464 66.14% 66.14% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3295264 33.68% 99.82% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 17955 0.18% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5652330 63.93% 63.93% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3175399 35.91% 99.84% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 14201 0.16% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9784683 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 10614903907 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8841930 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9598709952 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2624417 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2569910 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5004390482 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4696248682 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4630478453 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4118726891 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |