diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 4746 |
1 files changed, 2424 insertions, 2322 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 864e98054..ecc4cd446 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,165 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.349475 # Number of seconds simulated -sim_ticks 47349475204500 # Number of ticks simulated -final_tick 47349475204500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.349389 # Number of seconds simulated +sim_ticks 47349388766500 # Number of ticks simulated +final_tick 47349388766500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170024 # Simulator instruction rate (inst/s) -host_op_rate 200007 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9521770968 # Simulator tick rate (ticks/s) -host_mem_usage 827688 # Number of bytes of host memory used -host_seconds 4972.76 # Real time elapsed on the host -sim_insts 845490438 # Number of instructions simulated -sim_ops 994586036 # Number of ops (including micro ops) simulated +host_inst_rate 148460 # Simulator instruction rate (inst/s) +host_op_rate 174619 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7799944718 # Simulator tick rate (ticks/s) +host_mem_usage 883812 # Number of bytes of host memory used +host_seconds 6070.48 # Real time elapsed on the host +sim_insts 901223526 # Number of instructions simulated +sim_ops 1060022042 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 457024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 242432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 409152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 13269720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 28432512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 254656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 419648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 10291040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 23441792 # Number of bytes read from this memory -system.physmem.bytes_read::total 77217976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3825664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 566400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4392064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 33722560 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.inst 56250828 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.inst 43534148 # Number of bytes written to this memory -system.physmem.bytes_written::total 140338128 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 7141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 3788 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 6393 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 207361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 444258 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3979 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 6557 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 160812 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 366278 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1206567 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 526915 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.inst 881196 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.inst 680222 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2195061 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 9652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 5120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 8641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 280251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 600482 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 5378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 8863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 217342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 495080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1630810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 80796 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 11962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 712206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 144259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 1187993 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 919422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2963879 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 712206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 153911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 5120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 8641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 1468243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 600482 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 5378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 8863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1136764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 495080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4594689 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1206567 # Number of read requests accepted -system.physmem.writeReqs 2195061 # Number of write requests accepted -system.physmem.readBursts 1206567 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2195061 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 76928704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 291584 # Total number of bytes read from write queue -system.physmem.bytesWritten 135133184 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 77217976 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 140338128 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 4556 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 83588 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 93227 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 68916 # Per bank write bursts -system.physmem.perBankRdBursts::1 78372 # Per bank write bursts -system.physmem.perBankRdBursts::2 66961 # Per bank write bursts -system.physmem.perBankRdBursts::3 74483 # Per bank write bursts -system.physmem.perBankRdBursts::4 67860 # Per bank write bursts -system.physmem.perBankRdBursts::5 84994 # Per bank write bursts -system.physmem.perBankRdBursts::6 78873 # Per bank write bursts -system.physmem.perBankRdBursts::7 74831 # Per bank write bursts -system.physmem.perBankRdBursts::8 70689 # Per bank write bursts -system.physmem.perBankRdBursts::9 121049 # Per bank write bursts -system.physmem.perBankRdBursts::10 55712 # Per bank write bursts -system.physmem.perBankRdBursts::11 71204 # Per bank write bursts -system.physmem.perBankRdBursts::12 68805 # Per bank write bursts -system.physmem.perBankRdBursts::13 80552 # Per bank write bursts -system.physmem.perBankRdBursts::14 71313 # Per bank write bursts -system.physmem.perBankRdBursts::15 67397 # Per bank write bursts -system.physmem.perBankWrBursts::0 131295 # Per bank write bursts -system.physmem.perBankWrBursts::1 120115 # Per bank write bursts -system.physmem.perBankWrBursts::2 136218 # Per bank write bursts -system.physmem.perBankWrBursts::3 122111 # Per bank write bursts -system.physmem.perBankWrBursts::4 136290 # Per bank write bursts -system.physmem.perBankWrBursts::5 134780 # Per bank write bursts -system.physmem.perBankWrBursts::6 183921 # Per bank write bursts -system.physmem.perBankWrBursts::7 113990 # Per bank write bursts -system.physmem.perBankWrBursts::8 112648 # Per bank write bursts -system.physmem.perBankWrBursts::9 120303 # Per bank write bursts -system.physmem.perBankWrBursts::10 105255 # Per bank write bursts -system.physmem.perBankWrBursts::11 150368 # Per bank write bursts -system.physmem.perBankWrBursts::12 133266 # Per bank write bursts -system.physmem.perBankWrBursts::13 132701 # Per bank write bursts -system.physmem.perBankWrBursts::14 112511 # Per bank write bursts -system.physmem.perBankWrBursts::15 165684 # Per bank write bursts +system.physmem.bytes_read::cpu0.dtb.walker 126592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 108352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 12219800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 55224576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 171840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 160768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 11630176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 36221056 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 451968 # Number of bytes read from this memory +system.physmem.bytes_read::total 116315128 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4075008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 659840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4734848 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 84862912 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.inst 20812 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.inst 4 # Number of bytes written to this memory +system.physmem.bytes_written::total 84883728 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1693 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 190956 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 862884 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2685 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2512 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 181736 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 565954 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7062 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1817460 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1325983 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.inst 2602 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.inst 1 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1328586 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 258077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 1166321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 245625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 764974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2456529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 86063 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 13936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 99998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1792270 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.inst 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1792710 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1792270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 258517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 1166321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 245625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 764974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4249239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1817460 # Number of read requests accepted +system.physmem.writeReqs 1459105 # Number of write requests accepted +system.physmem.readBursts 1817460 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1459105 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 116259968 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 57472 # Total number of bytes read from write queue +system.physmem.bytesWritten 92884608 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 116315128 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 93236944 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 898 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7766 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 92270 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 109521 # Per bank write bursts +system.physmem.perBankRdBursts::1 125500 # Per bank write bursts +system.physmem.perBankRdBursts::2 109858 # Per bank write bursts +system.physmem.perBankRdBursts::3 118807 # Per bank write bursts +system.physmem.perBankRdBursts::4 114750 # Per bank write bursts +system.physmem.perBankRdBursts::5 133958 # Per bank write bursts +system.physmem.perBankRdBursts::6 108183 # Per bank write bursts +system.physmem.perBankRdBursts::7 109296 # Per bank write bursts +system.physmem.perBankRdBursts::8 104951 # Per bank write bursts +system.physmem.perBankRdBursts::9 157608 # Per bank write bursts +system.physmem.perBankRdBursts::10 96466 # Per bank write bursts +system.physmem.perBankRdBursts::11 111139 # Per bank write bursts +system.physmem.perBankRdBursts::12 103753 # Per bank write bursts +system.physmem.perBankRdBursts::13 116262 # Per bank write bursts +system.physmem.perBankRdBursts::14 95073 # Per bank write bursts +system.physmem.perBankRdBursts::15 101437 # Per bank write bursts +system.physmem.perBankWrBursts::0 88391 # Per bank write bursts +system.physmem.perBankWrBursts::1 94888 # Per bank write bursts +system.physmem.perBankWrBursts::2 89089 # Per bank write bursts +system.physmem.perBankWrBursts::3 94540 # Per bank write bursts +system.physmem.perBankWrBursts::4 92096 # Per bank write bursts +system.physmem.perBankWrBursts::5 104028 # Per bank write bursts +system.physmem.perBankWrBursts::6 87215 # Per bank write bursts +system.physmem.perBankWrBursts::7 89925 # Per bank write bursts +system.physmem.perBankWrBursts::8 85891 # Per bank write bursts +system.physmem.perBankWrBursts::9 90043 # Per bank write bursts +system.physmem.perBankWrBursts::10 85085 # Per bank write bursts +system.physmem.perBankWrBursts::11 94536 # Per bank write bursts +system.physmem.perBankWrBursts::12 86659 # Per bank write bursts +system.physmem.perBankWrBursts::13 94890 # Per bank write bursts +system.physmem.perBankWrBursts::14 85144 # Per bank write bursts +system.physmem.perBankWrBursts::15 88902 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 47349473266500 # Total gap between requests +system.physmem.totGap 47349386828500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1206525 # Read request sizes (log2) +system.physmem.readPktSize::6 1817418 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2192458 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 701586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 159041 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 78388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 62534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 48409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 42357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24739 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 6356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1456502 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 724796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 275224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 218778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 130576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 121480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 92297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 78276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 67824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 54542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29215 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 6539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 4680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 3658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -183,158 +180,156 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 77454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 97715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 98472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 108608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 137758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 125184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 127483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 141417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 129468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 120366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 126014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 120082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 115005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 123737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 112481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 110136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 106316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 102758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 691339 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 306.739519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.472793 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 357.323128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 329714 47.69% 47.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 128094 18.53% 66.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 46159 6.68% 72.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24419 3.53% 76.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20272 2.93% 79.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13585 1.97% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10457 1.51% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 11430 1.65% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 107209 15.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 691339 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 99075 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.132152 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 222.564559 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 99072 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 99075 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 99075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.311693 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.731664 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.258880 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 33791 34.11% 34.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 48957 49.41% 83.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 10331 10.43% 93.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 2038 2.06% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1546 1.56% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 746 0.75% 98.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 511 0.52% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 316 0.32% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 116 0.12% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 38 0.04% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 31 0.03% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 20 0.02% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 438 0.44% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 35 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 39 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 38 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 24 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 10 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 7 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 99075 # Writes before turning the bus around for reads -system.physmem.totQLat 32464480274 # Total ticks spent queuing -system.physmem.totMemAccLat 55002186524 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6010055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27008.47 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 20715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 37146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 48711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 55470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 75025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 82665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 93812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 97796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 101866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 103500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 107192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 100425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 105997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 102597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 17377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 13177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 9215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 894898 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 233.707153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.846498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 284.283402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 463489 51.79% 51.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 185877 20.77% 72.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 67737 7.57% 80.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 36988 4.13% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 29329 3.28% 87.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 22133 2.47% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 15835 1.77% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13649 1.53% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 59861 6.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 894898 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 77790 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.351999 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 144.403085 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 77788 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 77790 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 77790 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.656922 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.550932 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.537959 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 73893 94.99% 94.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 1079 1.39% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 616 0.79% 97.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 255 0.33% 97.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 611 0.79% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 159 0.20% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 204 0.26% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 127 0.16% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 198 0.25% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 57 0.07% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 225 0.29% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 47 0.06% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 57 0.07% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 49 0.06% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 102 0.13% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 22 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 26 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 10 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 13 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 9 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 77790 # Writes before turning the bus around for reads +system.physmem.totQLat 101322311265 # Total ticks spent queuing +system.physmem.totMemAccLat 135382848765 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9082810000 # Total ticks spent in databus transfers +system.physmem.avgQLat 55776.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45758.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.62 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.63 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.96 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 74526.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.37 # Average write queue length when enqueuing -system.physmem.readRowHits 944165 # Number of row buffer hits during reads -system.physmem.writeRowHits 1677959 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.47 # Row buffer hit rate for writes -system.physmem.avgGap 13919650.61 # Average gap between requests -system.physmem.pageHitRate 79.13 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45391806829500 # Time in different power states -system.physmem.memoryStateTime::REF 1581102900000 # Time in different power states +system.physmem.avgWrQLen 27.53 # Average write queue length when enqueuing +system.physmem.readRowHits 1479200 # Number of row buffer hits during reads +system.physmem.writeRowHits 893785 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.58 # Row buffer hit rate for writes +system.physmem.avgGap 14450922.48 # Average gap between requests +system.physmem.pageHitRate 72.61 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 45452153624500 # Time in different power states +system.physmem.memoryStateTime::REF 1581100040000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 376561525500 # Time in different power states +system.physmem.memoryStateTime::ACT 316134376000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2682083880 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2544438960 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1463438625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1388334750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 4643184000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 4732392600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 6990105600 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 6692129280 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3092637272400 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3092637272400 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1220178523320 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1215644323230 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27339350706750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27343328075250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31667945314575 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31666966966470 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.813072 # Core power per rank (mW) -system.physmem.averagePower::1 668.792410 # Core power per rank (mW) +system.physmem.actEnergy::0 3577346640 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3188082240 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1951925250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1739529000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 7253009400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 6916111800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 4796314560 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 4608252000 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3092631678240 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3092631678240 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1196963299980 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1185023558430 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 27359663548500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 27370137006000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 31666837122570 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 31664244217710 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.790877 # Core power per rank (mW) +system.physmem.averagePower::1 668.736116 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory @@ -353,703 +348,22 @@ system.realview.nvmem.bw_inst_read::total 27 # I system.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1114990 # Transaction distribution -system.membus.trans_dist::ReadResp 1114990 # Transaction distribution -system.membus.trans_dist::WriteReq 37937 # Transaction distribution -system.membus.trans_dist::WriteResp 37937 # Transaction distribution -system.membus.trans_dist::Writeback 526915 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1665543 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1665543 # Transaction distribution -system.membus.trans_dist::UpgradeReq 343558 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 290459 # Transaction distribution -system.membus.trans_dist::UpgradeResp 93233 # Transaction distribution -system.membus.trans_dist::ReadExReq 145423 # Transaction distribution -system.membus.trans_dist::ReadExResp 131308 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122918 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 23584 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6789962 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6936516 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 229526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7166042 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 47168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210268488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 210473028 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7287616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7287616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 217760644 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 556693 # Total snoops (count) -system.membus.snoop_fanout::samples 3996553 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3996553 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3996553 # Request fanout histogram -system.membus.reqLayer0.occupancy 106711482 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 35984 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20060995 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 21791270978 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 13392760110 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187374753 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 893379 # number of replacements -system.l2c.tags.tagsinuse 64139.353797 # Cycle average of tags in use -system.l2c.tags.total_refs 6866398 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 953433 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 7.201762 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 10411.534254 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 170.665758 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 236.653363 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5522.014615 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 25703.497535 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 145.004713 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 188.005532 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6322.307070 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 15439.670958 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.158867 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002604 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003611 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.084259 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.392204 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002213 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002869 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.096471 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.235591 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.978689 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 36012 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 260 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 23782 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 41 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 716 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1957 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 33290 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 51 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 190 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1450 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3907 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18298 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.549500 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.362885 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 80317062 # Number of tag accesses -system.l2c.tags.data_accesses 80317062 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 7070 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4466 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 557041 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 2033838 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 7318 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4580 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 521752 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1881001 # number of ReadReq hits -system.l2c.ReadReq_hits::total 5017066 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1844732 # number of Writeback hits -system.l2c.Writeback_hits::total 1844732 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 30097 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 27244 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 57341 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 7329 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 7124 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 14453 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 51408 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 52005 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 103413 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 7070 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4466 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 608449 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 2033838 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 7318 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4580 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 573757 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 1881001 # number of demand (read+write) hits -system.l2c.demand_hits::total 5120479 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 7070 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4466 # number of overall hits -system.l2c.overall_hits::cpu0.inst 608449 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 2033838 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 7318 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4580 # number of overall hits -system.l2c.overall_hits::cpu1.inst 573757 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 1881001 # number of overall hits -system.l2c.overall_hits::total 5120479 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3788 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 6393 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 87512 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 444466 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3979 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 6557 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 97026 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 366468 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1016189 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 36620 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 34601 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 71221 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 9478 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 8512 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 17990 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 69660 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 65667 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 135327 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3788 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 6393 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 157172 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 444466 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3979 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 6557 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 162693 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 366468 # number of demand (read+write) misses -system.l2c.demand_misses::total 1151516 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3788 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 6393 # number of overall misses -system.l2c.overall_misses::cpu0.inst 157172 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 444466 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3979 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 6557 # number of overall misses -system.l2c.overall_misses::cpu1.inst 162693 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 366468 # number of overall misses -system.l2c.overall_misses::total 1151516 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 295641239 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 507564744 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 6935191428 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 45326284922 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 312400496 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 512318742 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 7688372365 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 38103566034 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 99681339970 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 177719564 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 161535756 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 339255320 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 49426933 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 49799411 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 99226344 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 5124274653 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 4787449538 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9911724191 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 295641239 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 507564744 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 12059466081 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 45326284922 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 312400496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 512318742 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 12475821903 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 38103566034 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 109593064161 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 295641239 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 507564744 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 12059466081 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 45326284922 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 312400496 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 512318742 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 12475821903 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 38103566034 # number of overall miss cycles -system.l2c.overall_miss_latency::total 109593064161 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 10858 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 10859 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 644553 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2478304 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 11297 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 11137 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 618778 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2247469 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 6033255 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1844732 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1844732 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 66717 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 61845 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 128562 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 16807 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 15636 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 32443 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 121068 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 117672 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 238740 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 10858 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 10859 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 765621 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 2478304 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 11297 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 11137 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 736450 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2247469 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 6271995 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 10858 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 10859 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 765621 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 2478304 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 11297 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 11137 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 736450 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2247469 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 6271995 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.348867 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.588728 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.135772 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.179343 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.352217 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.588758 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.156803 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.163058 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.168431 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.548886 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.559479 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.553982 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.563932 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.544385 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.554511 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.inst 0.575379 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.inst 0.558051 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.566838 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.348867 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.588728 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.205287 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.179343 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.352217 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.588758 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.220915 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.163058 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.183596 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.348867 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.588728 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.205287 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.179343 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.352217 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.588758 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.220915 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.163058 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.183596 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78046.789599 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79393.828250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79248.462245 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78512.313647 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 78133.100808 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79240.331097 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 98093.307416 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 4853.073839 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 4668.528540 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4763.416970 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 5214.911690 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 5850.494713 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5515.638911 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 73561.220973 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 72904.952838 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73242.768930 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78046.789599 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79393.828250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 76727.827355 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78512.313647 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 78133.100808 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76683.212572 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 95172.854012 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78046.789599 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79393.828250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 76727.827355 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78512.313647 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 78133.100808 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76683.212572 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 95172.854012 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 9985 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 293 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 34.078498 # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 526915 # number of writebacks -system.l2c.writebacks::total 526915 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 41 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 208 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 31 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 190 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 470 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 41 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 208 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 31 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 190 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 470 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 41 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 208 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 31 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 190 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 470 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3788 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 6393 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 87471 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 444258 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3979 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 6557 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 96995 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 366278 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 1015719 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.inst 36620 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.inst 34601 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 71221 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 9478 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 8512 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 17990 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.inst 69660 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.inst 65667 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 135327 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 3788 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 6393 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 157131 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 444258 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 3979 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 6557 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 162662 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 366278 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 1151046 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 3788 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 6393 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 157131 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 444258 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 3979 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 6557 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 162662 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 366278 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 1151046 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 248599239 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 428022244 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 5837610680 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 39831799422 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 430600242 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 6471220731 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 87083288091 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 17889181875 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 13903512484 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 31792694359 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 372768590 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 351692080 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 724460670 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 96695300 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 86940850 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 183636150 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 4247852269 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 3960733380 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8208585649 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 248599239 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 428022244 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 10085462949 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 39831799422 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 430600242 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 10431954111 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 95291873740 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 248599239 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 428022244 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 10085462949 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39831799422 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 430600242 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 10431954111 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 95291873740 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4946669501 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3170681000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 8117350501 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 2118382500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 3125324001 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5243706501 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7065052001 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6296005001 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 13361057002 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.135708 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.156753 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.168353 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.548886 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.559479 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.553982 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.563932 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.544385 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.554511 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.575379 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.558051 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.566838 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.205233 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.220873 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.183522 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.205233 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.220873 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.183522 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 66737.669399 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66717.054807 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 85735.610037 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10179.371655 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10164.217219 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10172.009239 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10202.078498 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10213.915648 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10207.679266 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 60979.791401 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60315.430582 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60657.412408 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64185.061821 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64132.705309 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 82787.198548 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64185.061821 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64132.705309 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 82787.198548 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 6929805 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 6922247 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 37937 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 37937 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1844732 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1558815 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 396880 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 304912 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 701792 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 122 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 286652 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 286652 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10302950 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9169444 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 19472394 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 332778181 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 290120831 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 622899012 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1503135 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 11338555 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.010201 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.100485 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 11222888 98.98% 98.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115667 1.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 11338555 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 19325316227 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 6157500 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 17505808152 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 16090621161 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40386 # Transaction distribution -system.iobus.trans_dist::ReadResp 40386 # Transaction distribution -system.iobus.trans_dist::WriteReq 136543 # Transaction distribution -system.iobus.trans_dist::WriteResp 136730 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 187 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48036 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354232 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156048 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36503000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 982100345 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92919000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179226247 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 130284886 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91971902 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5996877 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 97983342 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 71203631 # Number of BTB hits +system.cpu0.branchPred.lookups 127854962 # Number of BP lookups +system.cpu0.branchPred.condPredicted 91169153 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5795491 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 97464931 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 70565780 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.669119 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15456951 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1030979 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.401200 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 14662444 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 979053 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1073,25 +387,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 84560824 # DTB read hits -system.cpu0.dtb.read_misses 213472 # DTB read misses -system.cpu0.dtb.write_hits 73762718 # DTB write hits -system.cpu0.dtb.write_misses 44801 # DTB write misses +system.cpu0.dtb.read_hits 80634882 # DTB read hits +system.cpu0.dtb.read_misses 217470 # DTB read misses +system.cpu0.dtb.write_hits 71942682 # DTB write hits +system.cpu0.dtb.write_misses 47848 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35801 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1794 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7921 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 34852 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1874 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8493 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10648 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 84774296 # DTB read accesses -system.cpu0.dtb.write_accesses 73807519 # DTB write accesses +system.cpu0.dtb.perms_faults 11561 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 80852352 # DTB read accesses +system.cpu0.dtb.write_accesses 71990530 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 158323542 # DTB hits -system.cpu0.dtb.misses 258273 # DTB misses -system.cpu0.dtb.accesses 158581815 # DTB accesses +system.cpu0.dtb.hits 152577564 # DTB hits +system.cpu0.dtb.misses 265318 # DTB misses +system.cpu0.dtb.accesses 152842882 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1113,93 +427,294 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 233888906 # ITB inst hits -system.cpu0.itb.inst_misses 61464 # ITB inst misses +system.cpu0.itb.inst_hits 228743332 # ITB inst hits +system.cpu0.itb.inst_misses 63317 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25786 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24510 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 208811 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 202277 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 233950370 # ITB inst accesses -system.cpu0.itb.hits 233888906 # DTB hits -system.cpu0.itb.misses 61464 # DTB misses -system.cpu0.itb.accesses 233950370 # DTB accesses -system.cpu0.numCycles 883850249 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 228806649 # ITB inst accesses +system.cpu0.itb.hits 228743332 # DTB hits +system.cpu0.itb.misses 63317 # DTB misses +system.cpu0.itb.accesses 228806649 # DTB accesses +system.cpu0.numCycles 867293351 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 434327088 # Number of instructions committed -system.cpu0.committedOps 509859279 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 43671037 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 5040 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93815840018 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.034988 # CPI: cycles per instruction -system.cpu0.ipc 0.491403 # IPC: instructions per cycle +system.cpu0.committedInsts 417325536 # Number of instructions committed +system.cpu0.committedOps 490736323 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 44793539 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4342 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93832115526 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.078218 # CPI: cycles per instruction +system.cpu0.ipc 0.481182 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5406 # number of quiesce instructions executed -system.cpu0.tickCycles 675499590 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 208350659 # Total number of cycles that the object has spent stopped -system.cpu0.icache.tags.replacements 9024677 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.937426 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 224649292 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9025189 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.891367 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 16724996500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937426 # Average occupied blocks per requestor +system.cpu0.kern.inst.quiesce 4790 # number of quiesce instructions executed +system.cpu0.tickCycles 682045150 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 185248201 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5375859 # number of replacements +system.cpu0.dcache.tags.tagsinuse 504.387778 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 144555742 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5376371 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.887233 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4951320000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 504.387778 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.985132 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.985132 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 308078040 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 308078040 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 74032777 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 74032777 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 66638302 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 66638302 # number of WriteReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 115191 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 115191 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1688442 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1688442 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1614699 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1614699 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.inst 140671079 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 140671079 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.inst 140671079 # number of overall hits +system.cpu0.dcache.overall_hits::total 140671079 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.inst 3863790 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3863790 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.inst 2319255 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2319255 # number of WriteReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst 742685 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 742685 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 105957 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 105957 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 178436 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 178436 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.inst 6183045 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6183045 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.inst 6183045 # number of overall misses +system.cpu0.dcache.overall_misses::total 6183045 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 54382834533 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 54382834533 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 36195221997 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 36195221997 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst 21037893950 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 21037893950 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1466052740 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 1466052740 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3737583856 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3737583856 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 3062000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3062000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.inst 90578056530 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 90578056530 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.inst 90578056530 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 90578056530 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 77896567 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 77896567 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.inst 68957557 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 68957557 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 857876 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 857876 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1794399 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1794399 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1793135 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1793135 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 146854124 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 146854124 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 146854124 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 146854124 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.049602 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.049602 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.033633 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.033633 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst 0.865725 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.865725 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.059049 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059049 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.099511 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099511 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.042103 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.042103 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.042103 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.042103 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14074.997485 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14074.997485 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15606.400330 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15606.400330 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 28326.806048 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 28326.806048 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13836.299065 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13836.299065 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20946.355309 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20946.355309 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 14649.425409 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14649.425409 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 14649.425409 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14649.425409 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 3741617 # number of writebacks +system.cpu0.dcache.writebacks::total 3741617 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 374932 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 374932 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 967778 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 967778 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst 26 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 26 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 53 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 53 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 76 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 76 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 1342710 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1342710 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 1342710 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1342710 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3488858 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3488858 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1351477 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1351477 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.inst 742659 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 742659 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 105904 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 105904 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 178360 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 178360 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 4840335 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4840335 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 4840335 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4840335 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 42020078260 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42020078260 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 19120911908 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19120911908 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 19537847050 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 19537847050 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1252614238 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1252614238 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3369767592 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3369767592 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2341000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2341000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 61140990168 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61140990168 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 61140990168 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 61140990168 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2949307890 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2949307890 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 3070097397 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3070097397 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 6019405287 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6019405287 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.044788 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.044788 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.019599 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019599 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.865695 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.865695 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.059019 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059019 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.099468 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099468 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.032960 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032960 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.032960 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032960 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12044.078108 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.078108 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14148.159316 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14148.159316 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 26307.965096 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26307.965096 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11827.827447 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11827.827447 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18893.067908 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18893.067908 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12631.561693 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12631.561693 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12631.561693 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12631.561693 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 8781546 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.937582 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 219752565 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 8782058 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 25.022901 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 16633914000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937582 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999878 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999878 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 476374153 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 476374153 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 224649292 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 224649292 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 224649292 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 224649292 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 224649292 # number of overall hits -system.cpu0.icache.overall_hits::total 224649292 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9025190 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9025190 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9025190 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9025190 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9025190 # number of overall misses -system.cpu0.icache.overall_misses::total 9025190 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 76329373412 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 76329373412 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 76329373412 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 76329373412 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 76329373412 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 76329373412 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 233674482 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 233674482 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 233674482 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 233674482 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 233674482 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 233674482 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038623 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.038623 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038623 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.038623 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038623 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.038623 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8457.370251 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8457.370251 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8457.370251 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8457.370251 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8457.370251 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8457.370251 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 465851331 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 465851331 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 219752565 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 219752565 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 219752565 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 219752565 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 219752565 # number of overall hits +system.cpu0.icache.overall_hits::total 219752565 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 8782067 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 8782067 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 8782067 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 8782067 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 8782067 # number of overall misses +system.cpu0.icache.overall_misses::total 8782067 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 75181971221 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 75181971221 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 75181971221 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 75181971221 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 75181971221 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 75181971221 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 228534632 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 228534632 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 228534632 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 228534632 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 228534632 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 228534632 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038428 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.038428 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038428 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.038428 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038428 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.038428 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8560.851474 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8560.851474 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8560.851474 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8560.851474 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8560.851474 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8560.851474 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1208,384 +723,353 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9025190 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9025190 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9025190 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9025190 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9025190 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9025190 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62781832574 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 62781832574 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62781832574 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 62781832574 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62781832574 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 62781832574 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713380500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713380500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713380500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 4713380500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038623 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.038623 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.038623 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6956.289294 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6956.289294 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6956.289294 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8782067 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 8782067 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 8782067 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 8782067 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8782067 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 8782067 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 61997855741 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 61997855741 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 61997855741 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 61997855741 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 61997855741 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 61997855741 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713229500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 4713229500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038428 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.038428 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.038428 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7059.597216 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 16744363 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 13538941 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 16377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 16377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 2993146 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 4286145 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 878594 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 389729 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 340122 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 446153 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1234377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1099479 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18154960 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15139641 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 334891 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1016427 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 34645919 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 580958656 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 555417413 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1211560 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3676024 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1141263653 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 9180766 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 27586114 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.321691 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.467125 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 18711910 67.83% 67.83% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 8874204 32.17% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 27586114 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 13279117937 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 196246989 # Layer occupancy (ticks) -system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 13633302169 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7744080967 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 184135419 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 557460915 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 80006652 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 1538976 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 75387543 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49644 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 84003023 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 4398912 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 74572645 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1090360 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2517 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3027964 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6795468 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 154166 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3786940 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6742713 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 3295318 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16239.521092 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15183735 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3311433 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.585246 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 14515776000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5108.942549 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.019654 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 70.169979 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2735.324727 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8261.064181 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.311825 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003907 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004283 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.166951 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.504215 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.991182 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 10731 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5301 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 4037603 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16229.874548 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 15269588 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 4053811 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.766724 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 14918796500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 3465.639505 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 40.958286 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 27.625357 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2577.016988 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 10118.634411 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.211526 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002500 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001686 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.157289 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.617592 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.990593 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 10250 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5866 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 116 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 730 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2564 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4307 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 3014 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 30 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 447 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1426 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2059 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1321 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.654968 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.323547 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 302494843 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 302494843 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 445653 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140462 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 11717958 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 12304073 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 2993146 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 2993146 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 70651 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 70651 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 35155 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 35155 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 863705 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 863705 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 445653 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140462 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 12581663 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 13167778 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 445653 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140462 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 12581663 # number of overall hits -system.cpu0.l2cache.overall_hits::total 13167778 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13850 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10983 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 913042 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 937875 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 117562 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 117562 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 153389 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 153389 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 228005 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 228005 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13850 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10983 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 1141047 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1165880 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13850 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10983 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 1141047 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1165880 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 571410377 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 698481694 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 26359609041 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 27629501112 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 2365914343 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2365914343 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 3101977603 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3101977603 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 2176500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2176500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 9967705721 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 9967705721 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 571410377 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 698481694 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 36327314762 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 37597206833 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 571410377 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 698481694 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 36327314762 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 37597206833 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 459503 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 151445 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 12631000 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 13241948 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 2993146 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 2993146 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 188213 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 188213 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 188544 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 188544 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 1091710 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1091710 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 459503 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 151445 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 13722710 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 14333658 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 459503 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 151445 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 13722710 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 14333658 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.030141 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.072521 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.072286 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.070826 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.624622 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.624622 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.813545 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.813545 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 1048 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 4016 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3415 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1655 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 22 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 525 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2441 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1975 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 887 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.625610 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.358032 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 311163440 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 311163440 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 470272 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 147367 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 11429450 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 12047089 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 3741617 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 3741617 # number of Writeback hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.inst 295044 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::total 295044 # number of WriteInvalidateReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 86443 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 86443 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 36465 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 36465 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 911350 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 911350 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 470272 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 147367 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 12340800 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 12958439 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 470272 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 147367 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 12340800 # number of overall hits +system.cpu0.l2cache.overall_hits::total 12958439 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13865 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10088 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 947171 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 971124 # number of ReadReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.inst 446451 # number of WriteInvalidateReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::total 446451 # number of WriteInvalidateReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 123568 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 123568 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 141888 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 141888 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 7 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 231493 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 231493 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13865 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10088 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 1178664 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1202617 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13865 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10088 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 1178664 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1202617 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 459903131 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 354751936 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 28411115925 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 29225770992 # number of ReadReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.inst 15916059245 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 15916059245 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 2454108805 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2454108805 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 2872469472 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2872469472 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 2284000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2284000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 8822124839 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 8822124839 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 459903131 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 354751936 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 37233240764 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 38047895831 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 459903131 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 354751936 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 37233240764 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 38047895831 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 484137 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 157455 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 12376621 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 13018213 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 3741617 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 3741617 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.inst 741495 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::total 741495 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 210011 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 210011 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 178353 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 178353 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 1142843 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1142843 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 484137 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 157455 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 13519464 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 14161056 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 484137 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 157455 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 13519464 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 14161056 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028639 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.064069 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.076529 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.074597 # miss rate for ReadReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.inst 0.602096 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.602096 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.588388 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.588388 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.795546 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.795546 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.208851 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.208851 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.030141 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.072521 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.083150 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.081339 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.030141 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.072521 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.083150 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.081339 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 41257.066931 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 63596.621506 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 28870.094739 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29459.683979 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 20124.822162 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20124.822162 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 20222.946906 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20222.946906 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 725500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 725500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 43717.048841 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 43717.048841 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 41257.066931 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 63596.621506 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31836.825969 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 32247.921598 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 41257.066931 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 63596.621506 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31836.825969 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 32247.921598 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 62612 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.202559 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.202559 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028639 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064069 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.087183 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.084924 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028639 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.064069 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.087183 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.084924 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33170.077966 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35165.735131 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29995.762038 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30094.788093 # average ReadReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 35650.181644 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 35650.181644 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 19860.391080 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19860.391080 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 20244.625846 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20244.625846 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 326285.714286 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 326285.714286 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 38109.682967 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 38109.682967 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33170.077966 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35165.735131 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31589.359448 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 31637.583562 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33170.077966 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35165.735131 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31589.359448 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 31637.583562 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 196093 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 1060 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 2541 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 59.067925 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 77.171586 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1001402 # number of writebacks -system.cpu0.l2cache.writebacks::total 1001402 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 72428 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 72428 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 6233 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 6233 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 78661 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 78661 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 78661 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 78661 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13850 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10983 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 840614 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 865447 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 3027916 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 3027916 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 117562 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 117562 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 153389 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 153389 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 3 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 221772 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 221772 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13850 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10983 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 1062386 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1087219 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13850 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10983 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 1062386 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 3027916 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 4115135 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 473721015 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 620302796 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 19074448661 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 20168472472 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 79252881469 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 79252881469 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 33127814392 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 33127814392 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 2005449750 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2005449750 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 2118741906 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2118741906 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1770500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1770500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 7853083593 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 7853083593 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 473721015 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 620302796 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 26927532254 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 28021556065 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 473721015 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 620302796 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 26927532254 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 79252881469 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 107274437534 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6580252048 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6580252048 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 2399021553 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2399021553 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 8979273601 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8979273601 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.030141 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.072521 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.066552 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.065356 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.writebacks::writebacks 1602519 # number of writebacks +system.cpu0.l2cache.writebacks::total 1602519 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 5 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 79969 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 79976 # number of ReadReq MSHR hits +system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.inst 383227 # number of WriteInvalidateReq MSHR hits +system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 383227 # number of WriteInvalidateReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 9177 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 9177 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 5 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 89146 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 89153 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 5 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 89146 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 89153 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13863 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10083 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 867202 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 891148 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 3786879 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 3786879 # number of HardPFReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.inst 63224 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 63224 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 123568 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 123568 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 141888 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 141888 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 7 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 222316 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 222316 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13863 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10083 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 1089518 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1113464 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13863 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10083 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 1089518 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 3786879 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 4900343 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 362187797 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 283585554 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 20498207280 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 21143980631 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 168439656794 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 168439656794 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 1410635970 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 1410635970 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 2082130886 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2082130886 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 1980278880 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 1980278880 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1885000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1885000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 6408519883 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 6408519883 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 362187797 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 283585554 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 26906727163 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 27552500514 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 362187797 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 283585554 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 26906727163 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 168439656794 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 195992157308 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6920870357 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6920870357 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 2922560102 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2922560102 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 9843430459 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9843430459 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.028634 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.064037 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.070068 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.068454 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.624622 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.624622 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813545 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813545 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.085266 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.085266 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.588388 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.588388 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.795546 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.795546 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.203142 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.203142 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.030141 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.072521 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.077418 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075851 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.030141 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.072521 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.077418 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.194529 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.194529 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.028634 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064037 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080589 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.078629 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.028634 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064037 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080589 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.287096 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34203.683394 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56478.448147 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22691.090870 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23304.110445 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 26174.068722 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 26174.068722 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17058.656283 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17058.656283 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13812.867324 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13812.867324 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 590166.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 590166.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 35410.618081 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35410.618081 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34203.683394 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56478.448147 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25346.279275 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25773.607769 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34203.683394 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56478.448147 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25346.279275 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 26174.068722 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 26068.266906 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.346044 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23637.177128 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23726.676861 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 44479.809572 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22311.716595 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 22311.716595 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16850.081623 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16850.081623 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13956.633965 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13956.633965 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 269285.714286 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 269285.714286 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 28826.174828 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 28826.174828 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24695.991404 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 24744.850767 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24695.991404 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39995.599759 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1593,202 +1077,68 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 5337320 # number of replacements -system.cpu0.dcache.tags.tagsinuse 473.198574 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 150291577 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5337832 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.155921 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4951320000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 473.198574 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.924216 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.924216 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 319289852 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 319289852 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 77767484 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77767484 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 68524145 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 68524145 # number of WriteReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 878594 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 878594 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1744720 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1744720 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1671495 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1671495 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 146291629 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 146291629 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 146291629 # number of overall hits -system.cpu0.dcache.overall_hits::total 146291629 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 3855307 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3855307 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 2180509 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2180509 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 116717 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 116717 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 188600 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 188600 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 6035816 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6035816 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 6035816 # number of overall misses -system.cpu0.dcache.overall_misses::total 6035816 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 52949262121 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 52949262121 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 36682258766 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 36682258766 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1582680255 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 1582680255 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3978646923 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3978646923 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 2553000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2553000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 89631520887 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 89631520887 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 89631520887 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 89631520887 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 81622791 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 81622791 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 70704654 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 70704654 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 878594 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 878594 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1861437 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1861437 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1860095 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1860095 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 152327445 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 152327445 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 152327445 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 152327445 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.047233 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.047233 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030840 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030840 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.062703 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062703 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.101393 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101393 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.039624 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.039624 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.039624 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.039624 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 13734.123410 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13734.123410 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 16822.796313 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 16822.796313 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13559.980594 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13559.980594 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21095.688881 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21095.688881 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 14849.942557 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14849.942557 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 14849.942557 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14849.942557 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 878594 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 2993146 # number of writebacks -system.cpu0.dcache.writebacks::total 2993146 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 365860 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 365860 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 900170 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 900170 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 65 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 53 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 1266030 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1266030 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 1266030 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1266030 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3489447 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3489447 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1279618 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1279618 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 116652 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 116652 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 188547 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 188547 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 4769065 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4769065 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 4769065 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4769065 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 40912958493 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40912958493 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 19695838269 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19695838269 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 39725259601 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 39725259601 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1347811737 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1347811737 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3591126546 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3591126546 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2234500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2234500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 60608796762 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 60608796762 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 60608796762 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 60608796762 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2590105703 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2590105703 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 2521930197 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2521930197 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 5112035900 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5112035900 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.042751 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.042751 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.018098 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018098 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.062668 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062668 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.101364 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101364 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031308 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.031308 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031308 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031308 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11724.768564 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11724.768564 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 15391.967188 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15391.967188 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11554.124550 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11554.124550 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19046.320260 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19046.320260 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12708.737826 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12708.737826 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12708.737826 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12708.737826 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 124419206 # Number of BP lookups -system.cpu1.branchPred.condPredicted 87805046 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6051921 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 92935126 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 66733716 # Number of BTB hits +system.cpu0.toL2Bus.trans_dist::ReadReq 17406363 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 13329872 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19688 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19687 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3741617 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 5530609 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 862152 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 741495 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 486160 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 325301 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 465486 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1278141 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1152631 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17668715 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15752783 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 346532 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1063511 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 34831541 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 565398848 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 598192623 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1259640 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3873096 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1168724207 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 10729638 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 29561564 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.351841 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.477545 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 19160579 64.82% 64.82% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 10400985 35.18% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 29561564 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14119794312 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 225496496 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 13269247990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 7748577182 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 189385144 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 579874631 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.branchPred.lookups 146637664 # Number of BP lookups +system.cpu1.branchPred.condPredicted 104244557 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6464776 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 109760718 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 80092874 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.806774 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 14888837 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1052333 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.970436 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17287162 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1125459 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1812,25 +1162,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 80858392 # DTB read hits -system.cpu1.dtb.read_misses 227532 # DTB read misses -system.cpu1.dtb.write_hits 71539111 # DTB write hits -system.cpu1.dtb.write_misses 46368 # DTB write misses +system.cpu1.dtb.read_hits 95196820 # DTB read hits +system.cpu1.dtb.read_misses 258683 # DTB read misses +system.cpu1.dtb.write_hits 82774540 # DTB write hits +system.cpu1.dtb.write_misses 48918 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 35324 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1220 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8196 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 40938 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1166 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8454 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10514 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 81085924 # DTB read accesses -system.cpu1.dtb.write_accesses 71585479 # DTB write accesses +system.cpu1.dtb.perms_faults 11190 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 95455503 # DTB read accesses +system.cpu1.dtb.write_accesses 82823458 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 152397503 # DTB hits -system.cpu1.dtb.misses 273900 # DTB misses -system.cpu1.dtb.accesses 152671403 # DTB accesses +system.cpu1.dtb.hits 177971360 # DTB hits +system.cpu1.dtb.misses 307601 # DTB misses +system.cpu1.dtb.accesses 178278961 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1852,92 +1202,294 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 221287255 # ITB inst hits -system.cpu1.itb.inst_misses 68040 # ITB inst misses +system.cpu1.itb.inst_hits 262373201 # ITB inst hits +system.cpu1.itb.inst_misses 66107 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25097 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 29545 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 202601 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 222220 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 221355295 # ITB inst accesses -system.cpu1.itb.hits 221287255 # DTB hits -system.cpu1.itb.misses 68040 # DTB misses -system.cpu1.itb.accesses 221355295 # DTB accesses -system.cpu1.numCycles 841372178 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 262439308 # ITB inst accesses +system.cpu1.itb.hits 262373201 # DTB hits +system.cpu1.itb.misses 66107 # DTB misses +system.cpu1.itb.accesses 262439308 # DTB accesses +system.cpu1.numCycles 965776076 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 411163350 # Number of instructions committed -system.cpu1.committedOps 484726757 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 42974941 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4643 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93858235376 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.046321 # CPI: cycles per instruction -system.cpu1.ipc 0.488682 # IPC: instructions per cycle +system.cpu1.committedInsts 483897990 # Number of instructions committed +system.cpu1.committedOps 569285719 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 49152054 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5850 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93733878410 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 1.995826 # CPI: cycles per instruction +system.cpu1.ipc 0.501046 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13250 # number of quiesce instructions executed -system.cpu1.tickCycles 646022417 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 195349761 # Total number of cycles that the object has spent stopped -system.cpu1.icache.tags.replacements 9199343 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.111645 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 211878543 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9199855 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 23.030639 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8364993861000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.111645 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990452 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990452 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 14403 # number of quiesce instructions executed +system.cpu1.tickCycles 777604637 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 188171439 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5691678 # number of replacements +system.cpu1.dcache.tags.tagsinuse 432.252247 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 169393329 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5692190 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.758903 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8364525946500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.inst 432.252247 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.844243 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.844243 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 358720623 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 358720623 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.inst 87552380 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 87552380 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.inst 77214593 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 77214593 # number of WriteReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 211985 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 211985 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1994962 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1994962 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1944639 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1944639 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.inst 164766973 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 164766973 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.inst 164766973 # number of overall hits +system.cpu1.dcache.overall_hits::total 164766973 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.inst 4362572 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 4362572 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.inst 2362737 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2362737 # number of WriteReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst 497251 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 497251 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 139927 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 139927 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 188742 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 188742 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.inst 6725309 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 6725309 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.inst 6725309 # number of overall misses +system.cpu1.dcache.overall_misses::total 6725309 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 63153941750 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 63153941750 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 37295206516 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 37295206516 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst 9223332559 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 9223332559 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1921743254 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 1921743254 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3886161820 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3886161820 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 3267000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3267000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.inst 100449148266 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 100449148266 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.inst 100449148266 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 100449148266 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.inst 91914952 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 91914952 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.inst 79577330 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 79577330 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst 709236 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 709236 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 2134889 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2134889 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 2133381 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2133381 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.inst 171492282 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 171492282 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.inst 171492282 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 171492282 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.047463 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.047463 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.029691 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029691 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst 0.701108 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.701108 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.065543 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.065543 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.088471 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.088471 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.039216 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.039216 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.039216 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.039216 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14476.309331 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14476.309331 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 15784.747315 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 15784.747315 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 18548.645571 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 18548.645571 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13733.898776 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13733.898776 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20589.809475 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20589.809475 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14935.990044 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14935.990044 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14935.990044 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14935.990044 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 3739270 # number of writebacks +system.cpu1.dcache.writebacks::total 3739270 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 400087 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 400087 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 959724 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 959724 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst 47 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 47 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 67 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst 75 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 75 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 1359811 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1359811 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.inst 1359811 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1359811 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3962485 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3962485 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1403013 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1403013 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.inst 497204 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 497204 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 139860 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 139860 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 188667 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 188667 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 5365498 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 5365498 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 5365498 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5365498 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 49100377691 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 49100377691 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 20233474919 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20233474919 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 8220345441 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 8220345441 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1640188222 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1640188222 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3498307132 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498307132 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 2504000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2504000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 69333852610 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 69333852610 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 69333852610 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 69333852610 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3411173732 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3411173732 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 3123925989 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3123925989 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 6535099721 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6535099721 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.043110 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043110 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.017631 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017631 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.701042 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.701042 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.065512 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065512 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.088436 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088436 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.031287 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031287 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.031287 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031287 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12391.309416 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12391.309416 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14421.445075 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14421.445075 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 16533.144225 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 16533.144225 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11727.357515 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11727.357515 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18542.231190 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18542.231190 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12922.165400 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12922.165400 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12922.165400 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12922.165400 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 10003641 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.113561 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 252141010 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 10004153 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.203634 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8364450905000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.113561 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990456 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990456 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 451356678 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 451356678 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 211878543 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 211878543 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 211878543 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 211878543 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 211878543 # number of overall hits -system.cpu1.icache.overall_hits::total 211878543 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 9199864 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 9199864 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 9199864 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 9199864 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 9199864 # number of overall misses -system.cpu1.icache.overall_misses::total 9199864 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 77780449816 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 77780449816 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 77780449816 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 77780449816 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 77780449816 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 77780449816 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 221078407 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 221078407 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 221078407 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 221078407 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 221078407 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 221078407 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.041614 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.041614 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.041614 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.041614 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.041614 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.041614 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8454.521699 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8454.521699 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8454.521699 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8454.521699 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8454.521699 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8454.521699 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 534294484 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 534294484 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 252141010 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 252141010 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 252141010 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 252141010 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 252141010 # number of overall hits +system.cpu1.icache.overall_hits::total 252141010 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 10004155 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 10004155 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 10004155 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 10004155 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 10004155 # number of overall misses +system.cpu1.icache.overall_misses::total 10004155 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 85019530358 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 85019530358 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 85019530358 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 85019530358 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 85019530358 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 85019530358 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 262145165 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 262145165 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 262145165 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 262145165 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 262145165 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 262145165 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038163 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.038163 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038163 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.038163 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038163 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.038163 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8498.421941 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8498.421941 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8498.421941 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8498.421941 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8498.421941 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8498.421941 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1946,380 +1498,353 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9199864 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9199864 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9199864 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 9199864 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 9199864 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 9199864 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 63970402202 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 63970402202 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 63970402202 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 63970402202 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 63970402202 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 63970402202 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8551999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8551999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8551999 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8551999 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.041614 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.041614 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.041614 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6953.407377 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6953.407377 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6953.407377 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 10004155 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 10004155 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 10004155 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 10004155 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 10004155 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 10004155 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 70001431618 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 70001431618 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 70001431618 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 70001431618 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 70001431618 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 70001431618 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8751000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8751000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8751000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8751000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038163 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.038163 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.038163 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6997.235810 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6997.235810 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6997.235810 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 16974832 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13523495 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 21560 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 21560 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 2756922 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 3912463 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 680221 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 382477 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337171 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 432582 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1151878 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1012928 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18399906 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13962178 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 374507 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1077414 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 33814005 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 588796992 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 509690879 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1369000 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3931224 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1103788095 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 9217690 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 27159033 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.328913 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.469818 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 18226076 67.11% 67.11% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 8932957 32.89% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 27159033 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 12584209028 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 175099992 # Layer occupancy (ticks) -system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13805070808 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7247611234 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 204139691 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 586587181 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 79358164 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 1355061 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 75203006 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49096 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 91266400 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2590593 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 83739964 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1124296 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 3073 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2747928 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6733876 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 159143 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 3652396 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 7945944 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 3063828 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13784.638052 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 15005563 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 3079680 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.872442 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9994842368500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 2928.842366 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.432287 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 61.914602 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2764.974382 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7961.474415 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.178762 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004116 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003779 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.168761 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.485930 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.841348 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9851 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 102 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5899 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 232 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4639 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 3547 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1433 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 75 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2951 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2204 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 483 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.601257 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006226 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.360046 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 294450591 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 294450591 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 477253 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 159835 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 11727223 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 12364311 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 2756922 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 2756922 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 68490 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 68490 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 32200 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 32200 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 776956 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 776956 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 477253 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 159835 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 12504179 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 13141267 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 477253 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 159835 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 12504179 # number of overall hits -system.cpu1.l2cache.overall_hits::total 13141267 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 14150 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11290 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 893170 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 918610 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 118620 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 118620 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 151637 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 151637 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 230937 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 230937 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 14150 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11290 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 1124107 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1149547 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 14150 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11290 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 1124107 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1149547 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 593312131 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 709102173 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 26528840524 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 27831254828 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2374329628 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2374329628 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 3078262421 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3078262421 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 2493000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2493000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9672285471 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 9672285471 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 593312131 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 709102173 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 36201125995 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 37503540299 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 593312131 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 709102173 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 36201125995 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 37503540299 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 491403 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 171125 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 12620393 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 13282921 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 2756922 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 2756922 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 187110 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 187110 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 183837 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 183837 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 1007893 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1007893 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 491403 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 171125 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 13628286 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 14290814 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 491403 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 171125 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 13628286 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 14290814 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028795 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065975 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.070772 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.069157 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.633959 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.633959 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.824845 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.824845 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.replacements 3964575 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13771.716542 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 17209014 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 3980703 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.323109 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9604482251250 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4186.861890 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.243250 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 63.010570 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2902.209445 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6553.391387 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.255546 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004043 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003846 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.177137 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.399987 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.840559 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9777 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6309 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 89 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 734 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4083 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 3317 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1554 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 691 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1911 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 531 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.596741 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.385071 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 336896441 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 336896441 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 545727 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 151675 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 13043643 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 13741045 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3739269 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3739269 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.inst 314994 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 314994 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 88927 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 88927 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 41659 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 41659 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 944385 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 944385 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 545727 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 151675 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 13988028 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 14685430 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 545727 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 151675 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 13988028 # number of overall hits +system.cpu1.l2cache.overall_hits::total 14685430 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 14704 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10320 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 1062508 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1087532 # number of ReadReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.inst 180857 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::total 180857 # number of WriteInvalidateReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 132678 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 132678 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 147002 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 147002 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 238730 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 238730 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 14704 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10320 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 1301238 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1326262 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 14704 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10320 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 1301238 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1326262 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 525735124 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 414121710 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 33089400106 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 34029256940 # number of ReadReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst 5173608568 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 5173608568 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2603383383 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 2603383383 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 2990869344 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2990869344 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 2444000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2444000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9524400999 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 9524400999 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 525735124 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 414121710 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 42613801105 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 43553657939 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 525735124 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 414121710 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 42613801105 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 43553657939 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 560431 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 161995 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 14106151 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 14828577 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3739269 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3739269 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst 495851 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 495851 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 221605 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 221605 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 188661 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 188661 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 1183115 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1183115 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 560431 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 161995 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 15289266 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 16011692 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 560431 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 161995 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 15289266 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 16011692 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026237 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.063706 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.075322 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.073340 # miss rate for ReadReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst 0.364741 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.364741 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.598714 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.598714 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.779186 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.779186 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.229128 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.229128 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028795 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065975 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.082483 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.080440 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028795 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065975 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.082483 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.080440 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 41930.185936 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 62807.986980 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29701.893843 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30297.138969 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 20016.267307 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20016.267307 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20300.206552 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20300.206552 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 498600 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 498600 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 41882.788254 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41882.788254 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 41930.185936 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 62807.986980 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32204.341753 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 32624.625439 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 41930.185936 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 62807.986980 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32204.341753 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 32624.625439 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 62499 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.201781 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.201781 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026237 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.063706 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.085108 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.082831 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026237 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.063706 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.085108 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.082831 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35754.565016 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40128.072674 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31142.730319 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31290.350022 # average ReadReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 28606.073130 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 28606.073130 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 19621.816601 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19621.816601 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20345.773146 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20345.773146 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 407333.333333 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 407333.333333 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 39896.121137 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39896.121137 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35754.565016 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40128.072674 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32748.660203 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 32839.407251 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35754.565016 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40128.072674 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32748.660203 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 32839.407251 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 95890 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 1018 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 1623 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 61.393910 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 59.081947 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 843330 # number of writebacks -system.cpu1.l2cache.writebacks::total 843330 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 70371 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 70371 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 5416 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 5416 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 75787 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 75787 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 75787 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 75787 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 14150 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 11290 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 822799 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 848239 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 2747875 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 2747875 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 118620 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 118620 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 151637 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 151637 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 5 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 225521 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 225521 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 14150 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 11290 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 1048320 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1073760 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 14150 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 11290 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 1048320 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 2747875 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 3821635 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 493428269 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 628615807 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 19412995328 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 20535039404 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 69814591572 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 69814591572 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 25734891864 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 25734891864 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 1991641357 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 1991641357 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 2078386327 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2078386327 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 2045000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2045000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 7579512625 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7579512625 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 493428269 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 628615807 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 26992507953 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 28114552029 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 493428269 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 628615807 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 26992507953 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 69814591572 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 97929143601 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3580047284 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3580047284 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 3492978036 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3492978036 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7073025320 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7073025320 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028795 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.065975 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.065196 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.063859 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 1340101 # number of writebacks +system.cpu1.l2cache.writebacks::total 1340101 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 83863 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 83867 # number of ReadReq MSHR hits +system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.inst 117019 # number of WriteInvalidateReq MSHR hits +system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 117019 # number of WriteInvalidateReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 10752 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 10752 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 94615 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 94619 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 94615 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 94619 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 14703 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10317 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 978645 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 1003665 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 3652327 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 3652327 # number of HardPFReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.inst 63838 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 63838 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 132678 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 132678 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 147002 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 147002 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 227978 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 227978 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 14703 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10317 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 1206623 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1231643 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 14703 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10317 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 1206623 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 3652327 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 4883970 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 421971770 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 341099282 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 24526546457 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 25289617509 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 110063206845 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 110063206845 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 1132471294 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 1132471294 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 2172031189 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2172031189 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 2030926339 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2030926339 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 2024000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2024000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 6846769063 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6846769063 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 421971770 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 341099282 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 31373315520 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 32136386572 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 421971770 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 341099282 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 31373315520 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 110063206845 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 142199593417 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3254469267 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3254469267 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 2984537511 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2984537511 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6239006778 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 6239006778 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026235 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.063687 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.069377 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.067685 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.633959 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.633959 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.824845 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.824845 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.128744 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.128744 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.598714 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.598714 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.779186 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.779186 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.223755 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.223755 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028795 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.065975 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076922 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.075136 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028795 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.065975 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076922 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.192693 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.192693 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026235 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.063687 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.078920 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.076921 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026235 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.063687 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.078920 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.267419 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23593.848957 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24209.025291 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25406.756702 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25406.756702 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16790.097429 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16790.097429 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13706.327130 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13706.327130 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 409000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 409000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 33608.899504 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33608.899504 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25748.347788 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26183.273757 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 25748.347788 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25406.756702 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25624.933726 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.305025 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25061.739913 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25197.269516 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30135.091093 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 17739.767756 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 17739.767756 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16370.695888 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16370.695888 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13815.637468 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13815.637468 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 337333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 337333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30032.586754 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30032.586754 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26092.290194 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29115.574710 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -2327,327 +1852,904 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 4834403 # number of replacements -system.cpu1.dcache.tags.tagsinuse 460.748614 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 144950857 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4834915 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.980022 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8365240216000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 460.748614 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.899900 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.899900 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 306842506 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 306842506 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 74397461 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 74397461 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 66754653 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 66754653 # number of WriteReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 680221 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 680221 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1623333 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1623333 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1553141 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1553141 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 141152114 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 141152114 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 141152114 # number of overall hits -system.cpu1.dcache.overall_hits::total 141152114 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 3628151 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3628151 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 2024929 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2024929 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 114968 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 114968 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 183901 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 183901 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 5653080 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5653080 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 5653080 # number of overall misses -system.cpu1.dcache.overall_misses::total 5653080 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 51111445827 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 51111445827 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 34750982270 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 34750982270 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1576484749 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 1576484749 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3893749340 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3893749340 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 2823500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2823500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 85862428097 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 85862428097 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 85862428097 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 85862428097 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 78025612 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 78025612 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 68779582 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 68779582 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst 680221 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 680221 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 1738301 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1738301 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 1737042 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1737042 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 146805194 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 146805194 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 146805194 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 146805194 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046499 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.046499 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.029441 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029441 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.066138 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066138 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.105870 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105870 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.038507 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038507 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.038507 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.038507 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14087.463787 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14087.463787 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 17161.580613 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17161.580613 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13712.378653 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13712.378653 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 21173.073230 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21173.073230 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 15188.610120 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15188.610120 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 15188.610120 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15188.610120 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 680221 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 2756922 # number of writebacks -system.cpu1.dcache.writebacks::total 2756922 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 322268 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 322268 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 829273 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 829273 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 78 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 78 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst 59 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 1151541 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1151541 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 1151541 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1151541 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3305883 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3305883 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1194736 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1194736 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 114890 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 114890 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 183842 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 183842 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 4500619 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4500619 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 4500619 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4500619 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 39848912237 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39848912237 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 18776610903 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18776610903 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 30844406102 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 30844406102 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1344930230 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1344930230 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3516398127 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3516398127 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 2557000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2557000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 58625523140 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 58625523140 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 58625523140 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 58625523140 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3752867967 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3752867967 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 3654726713 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3654726713 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 7407594680 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7407594680 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042369 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042369 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.017371 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017371 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.066093 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066093 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.105836 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105836 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030657 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030657 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030657 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030657 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12053.939065 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12053.939065 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 15716.117120 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15716.117120 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11706.242754 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11706.242754 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 19127.283901 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19127.283901 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 13026.102218 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13026.102218 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 13026.102218 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13026.102218 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 115612 # number of replacements -system.iocache.tags.tagsinuse 11.299913 # Cycle average of tags in use +system.cpu1.toL2Bus.trans_dist::ReadReq 19283354 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 15081139 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 18583 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 18583 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3739269 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 5170827 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 625737 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 495851 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 477449 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 330499 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 473092 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1314338 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1188302 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 20008489 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16359278 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 359533 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1226091 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 37953391 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640271616 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 615594373 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1295960 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4483448 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1261645397 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 10423087 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 30921485 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.327379 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.469257 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 20798445 67.26% 67.26% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 10123040 32.74% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 30921485 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 14664539498 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 176010242 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 15012316370 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 8461463125 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 197959664 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 666269864 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40348 # Transaction distribution +system.iobus.trans_dist::ReadResp 40348 # Transaction distribution +system.iobus.trans_dist::WriteReq 136740 # Transaction distribution +system.iobus.trans_dist::WriteResp 30012 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122926 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7496838 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36517000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 1042881499 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 92917000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179159841 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115566 # number of replacements +system.iocache.tags.tagsinuse 11.298842 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115582 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9121131291000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.419527 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.880386 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463720 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.242524 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706245 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9120788284000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.841658 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.457184 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240104 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466074 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706178 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042406 # Number of tag accesses -system.iocache.tags.data_accesses 1042406 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1040622 # Number of tag accesses +system.iocache.tags.data_accesses 1040622 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8857 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8894 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 187 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 187 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8889 # number of demand (read+write) misses -system.iocache.demand_misses::total 8929 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8857 # number of demand (read+write) misses +system.iocache.demand_misses::total 8897 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8889 # number of overall misses -system.iocache.overall_misses::total 8929 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5701000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1965059357 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1970760357 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8857 # number of overall misses +system.iocache.overall_misses::total 8897 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1971462847 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1977169847 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6058000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1965059357 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1971117357 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6058000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1965059357 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1971117357 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28907198811 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28907198811 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1971462847 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1977526847 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1971462847 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1977526847 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8857 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8894 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106915 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106915 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8889 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8929 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8857 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8897 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8889 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8929 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8857 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8897 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.001749 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.001749 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 221066.414332 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 220788.747143 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 222588.105115 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 222303.783112 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151450 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 221066.414332 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220754.547766 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151450 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 221066.414332 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220754.547766 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 54362 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270849.250534 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270849.250534 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 222588.105115 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 222268.949871 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 222588.105115 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 222268.949871 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 228015 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27566 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.902004 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.271603 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106728 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8857 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8889 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8929 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8857 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8897 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8889 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8929 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3777000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1502702365 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1506479365 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8857 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8897 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1510755865 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1514538865 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6627847227 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6627847227 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3978000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1502702365 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1506680365 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3978000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1502702365 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1506680365 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23356679475 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23356679475 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1510755865 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1514739865 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1510755865 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1514739865 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102081.081081 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 169051.902914 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 168774.295877 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170571.961725 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 170287.706881 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99450 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 169051.902914 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168740.101355 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99450 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 169051.902914 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168740.101355 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218843.035333 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218843.035333 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 1797599 # number of replacements +system.l2c.tags.tagsinuse 64905.725288 # Cycle average of tags in use +system.l2c.tags.total_refs 8591301 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1860596 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.617499 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6896032000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 7600.616161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.639535 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 9.409863 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1890.006249 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16961.129535 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 324.497512 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 441.216776 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 10554.786238 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 27107.423418 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.115976 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000254 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.028839 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.258806 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004951 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006732 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.161053 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.413626 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.990383 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 43530 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 179 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 19288 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 252 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1656 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6242 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 35370 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1730 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 16555 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.664215 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.002731 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.294312 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 89688959 # Number of tag accesses +system.l2c.tags.data_accesses 89688959 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8987 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6604 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 578381 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 2301852 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 8168 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5333 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 630016 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 2353942 # number of ReadReq hits +system.l2c.ReadReq_hits::total 5893283 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2942617 # number of Writeback hits +system.l2c.Writeback_hits::total 2942617 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.inst 6235 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.inst 6750 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 12985 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.inst 39044 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 35229 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 74273 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 7514 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.inst 7779 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 15293 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.inst 64131 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.inst 55187 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 119318 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8987 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6604 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 642512 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 2301852 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 8168 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5333 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 685203 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 2353942 # number of demand (read+write) hits +system.l2c.demand_hits::total 6012601 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8987 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6604 # number of overall hits +system.l2c.overall_hits::cpu0.inst 642512 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 2301852 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 8168 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5333 # number of overall hits +system.l2c.overall_hits::cpu1.inst 685203 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 2353942 # number of overall hits +system.l2c.overall_hits::total 6012601 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1978 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1693 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 95514 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 863521 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2685 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2512 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 131326 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 566480 # number of ReadReq misses +system.l2c.ReadReq_misses::total 1665709 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.inst 16918 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.inst 7174 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 24092 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.inst 36442 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.inst 33251 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 69693 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.inst 9494 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.inst 9010 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 18504 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.inst 45340 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.inst 52041 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 97381 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1978 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1693 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 140854 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 863521 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2685 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2512 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 183367 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 566480 # number of demand (read+write) misses +system.l2c.demand_misses::total 1763090 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1978 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1693 # number of overall misses +system.l2c.overall_misses::cpu0.inst 140854 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 863521 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2685 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2512 # number of overall misses +system.l2c.overall_misses::cpu1.inst 183367 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 566480 # number of overall misses +system.l2c.overall_misses::total 1763090 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 165226748 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 144557248 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 7974806913 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 222345248 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 209364000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 10644136699 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 220050587910 # number of ReadReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu0.inst 3639850 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu1.inst 3440357 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::total 7080207 # number of WriteInvalidateReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.inst 167282107 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.inst 155790979 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 323073086 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 53447323 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 50683879 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 104131202 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.inst 3468272337 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.inst 3934530582 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7402802919 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 165226748 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 144557248 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 11443079250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 222345248 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 209364000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 14578667281 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 227453390829 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 165226748 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 144557248 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 11443079250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 222345248 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 209364000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 14578667281 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of overall miss cycles +system.l2c.overall_miss_latency::total 227453390829 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 10965 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 8297 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 673895 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 3165373 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 10853 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7845 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 761342 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2920422 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 7558992 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2942617 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2942617 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.inst 23153 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.inst 13924 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 37077 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.inst 75486 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.inst 68480 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 143966 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.inst 17008 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.inst 16789 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 33797 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.inst 109471 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.inst 107228 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 216699 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 10965 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 8297 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 783366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 3165373 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 10853 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7845 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 868570 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2920422 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 7775691 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 10965 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 8297 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 783366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 3165373 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 10853 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7845 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 868570 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2920422 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 7775691 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.180392 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.204050 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.141734 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.272802 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.247397 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.320204 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.172493 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.193972 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.220361 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.inst 0.730704 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.inst 0.515226 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.649783 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.482765 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.485558 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.484093 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.558208 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.536661 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.547504 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.inst 0.414174 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.inst 0.485330 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.449384 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.180392 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.204050 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.179806 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.272802 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.247397 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.320204 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.211114 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.193972 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.226744 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.180392 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.204050 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.179806 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.272802 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.247397 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.320204 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.211114 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.193972 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.226744 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83532.228514 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85385.261666 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83493.591651 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82810.148231 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83345.541401 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81051.251839 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 132106.261004 # average ReadReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.inst 215.146589 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.inst 479.559102 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::total 293.882077 # average WriteInvalidateReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 4590.365704 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 4685.302066 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 4635.660482 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 5629.589530 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 5625.291787 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5627.496866 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 76494.758205 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 75604.438462 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 76018.965907 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83532.228514 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85385.261666 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 81240.712014 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82810.148231 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83345.541401 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 79505.403268 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 129008.383480 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83532.228514 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85385.261666 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 81240.712014 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82810.148231 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83345.541401 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 79505.403268 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 129008.383480 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 43295 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 946 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 45.766385 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 1219289 # number of writebacks +system.l2c.writebacks::total 1219289 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 49 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 228 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 53 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 251 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 581 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 49 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 228 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 53 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 251 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 581 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 49 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 228 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 53 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 251 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 581 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1978 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1693 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 95465 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 863293 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2685 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2512 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 131273 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 566229 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 1665128 # number of ReadReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu0.inst 16918 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu1.inst 7174 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::total 24092 # number of WriteInvalidateReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.inst 36442 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.inst 33251 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 69693 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 9494 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 9010 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 18504 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.inst 45340 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.inst 52041 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 97381 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 1978 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1693 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 140805 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 863293 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2685 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2512 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 183314 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 566229 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1762509 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 1978 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1693 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 140805 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 863293 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2685 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2512 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 183314 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 566229 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1762509 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 140499248 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 123414748 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 6776817493 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 188732748 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 177898500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 8997883953 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 63932898160 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 199639162524 # number of ReadReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 385829647 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 157261640 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::total 543091287 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 371667466 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 338371346 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 710038812 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 97958865 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 92039394 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 189998259 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 2897122081 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 3278712382 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6175834463 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 140499248 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 123414748 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 9673939574 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 188732748 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 177898500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 12276596335 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 63932898160 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 205814996987 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 140499248 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 123414748 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 9673939574 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 188732748 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 177898500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 12276596335 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 63932898160 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 205814996987 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5245081248 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2881233750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 8126314998 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 2584862001 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 2667893000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5252755001 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7829943249 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5549126750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13379069999 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.180392 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.204050 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.141662 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.272730 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.247397 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.320204 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.172423 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.193886 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.220284 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.730704 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.515226 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.649783 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.482765 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.485558 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.484093 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.558208 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.536661 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.547504 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.414174 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.485330 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.449384 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.180392 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.204050 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.179744 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.272730 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.247397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.320204 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.211053 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.193886 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.226669 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.180392 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.204050 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.179744 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.272730 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.247397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.320204 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.211053 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.193886 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.226669 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70987.456062 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68543.294912 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 119894.183825 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22805.866355 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 21921.053805 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22542.391126 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10198.876736 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10176.275781 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10188.093668 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10317.976090 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10215.249057 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10267.956064 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 63897.708006 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63002.486155 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63419.295992 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68704.517411 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66970.315060 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 116773.870084 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68704.517411 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66970.315060 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 116773.870084 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 1764688 # Transaction distribution +system.membus.trans_dist::ReadResp 1764688 # Transaction distribution +system.membus.trans_dist::WriteReq 38271 # Transaction distribution +system.membus.trans_dist::WriteResp 38271 # Transaction distribution +system.membus.trans_dist::Writeback 1325983 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 130519 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 130519 # Transaction distribution +system.membus.trans_dist::UpgradeReq 461811 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 273493 # Transaction distribution +system.membus.trans_dist::UpgradeResp 92294 # Transaction distribution +system.membus.trans_dist::ReadExReq 109929 # Transaction distribution +system.membus.trans_dist::ReadExResp 93588 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122926 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5737506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5885368 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336109 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336109 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6221477 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49768 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 195441096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 195648244 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14110976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14110976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 209759220 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 661928 # Total snoops (count) +system.membus.snoop_fanout::samples 3975767 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 3975767 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 3975767 # Request fanout histogram +system.membus.reqLayer0.occupancy 109763969 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 34484 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 20835993 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 15443357238 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 16944581187 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 187180159 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 8566773 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 8559524 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38271 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38271 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2942617 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 143810 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 37077 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 531990 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 288786 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 820776 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 117 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 266520 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 266520 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10703555 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10080815 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 20784370 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 361515951 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 330513413 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 692029364 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1718447 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 12650717 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.009140 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.095166 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 12535087 99.09% 99.09% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115630 0.91% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 12650717 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 18290340474 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 7404000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 20424320611 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 19750107809 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |