diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 332 |
1 files changed, 143 insertions, 189 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 3367a33d1..7463dd4c7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.535940 # Nu sim_ticks 47535940136000 # Number of ticks simulated final_tick 47535940136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 225035 # Simulator instruction rate (inst/s) -host_op_rate 264677 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11911388135 # Simulator tick rate (ticks/s) -host_mem_usage 769700 # Number of bytes of host memory used -host_seconds 3990.80 # Real time elapsed on the host +host_inst_rate 200561 # Simulator instruction rate (inst/s) +host_op_rate 235891 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10615931561 # Simulator tick rate (ticks/s) +host_mem_usage 769436 # Number of bytes of host memory used +host_seconds 4477.79 # Real time elapsed on the host sim_insts 898069628 # Number of instructions simulated sim_ops 1056270581 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -647,10 +647,10 @@ system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877481 system.cpu0.dcache.LoadLockedReq_hits::total 1877481 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1849167 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 1849167 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 164286110 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 164286110 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 164591140 # number of overall hits -system.cpu0.dcache.overall_hits::total 164591140 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 164573170 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 164573170 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 164878200 # number of overall hits +system.cpu0.dcache.overall_hits::total 164878200 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 3693348 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 3693348 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 2460225 # number of WriteReq misses @@ -663,10 +663,10 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173543 system.cpu0.dcache.LoadLockedReq_misses::total 173543 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200600 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 200600 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6153573 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6153573 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6815315 # number of overall misses -system.cpu0.dcache.overall_misses::total 6815315 # number of overall misses +system.cpu0.dcache.demand_misses::cpu0.data 7001465 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 7001465 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 7663207 # number of overall misses +system.cpu0.dcache.overall_misses::total 7663207 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 64125292500 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 64125292500 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62047058000 # number of WriteReq miss cycles @@ -679,10 +679,10 @@ system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5699610500 system.cpu0.dcache.StoreCondReq_miss_latency::total 5699610500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5746000 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5746000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 126172350500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 126172350500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 126172350500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 126172350500 # number of overall miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 177339794500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 177339794500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 177339794500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 177339794500 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 90736709 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 90736709 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 79702974 # number of WriteReq accesses(hits+misses) @@ -695,10 +695,10 @@ system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2051024 system.cpu0.dcache.LoadLockedReq_accesses::total 2051024 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2049767 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 2049767 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 170439683 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 170439683 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 171406455 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 171406455 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 171574635 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 171574635 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 172541407 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 172541407 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040704 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.040704 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030867 # miss rate for WriteReq accesses @@ -711,10 +711,10 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084613 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084613 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097865 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097865 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036104 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.036104 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039761 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.039761 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040807 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.040807 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.044414 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.044414 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17362.374870 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 17362.374870 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25220.074587 # average WriteReq miss latency @@ -727,18 +727,16 @@ system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28412.814058 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28412.814058 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20503.917074 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20503.917074 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18513.062199 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18513.062199 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25328.955369 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25328.955369 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23141.720496 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23141.720496 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 5972043 # number of writebacks system.cpu0.dcache.writebacks::total 5972043 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444932 # number of ReadReq MSHR hits @@ -751,10 +749,10 @@ system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46565 system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46565 # number of LoadLockedReq MSHR hits system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 65 # number of StoreCondReq MSHR hits system.cpu0.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457263 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1457263 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457263 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1457263 # number of overall MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457353 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1457353 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457353 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1457353 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3248416 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 3248416 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1447894 # number of WriteReq MSHR misses @@ -767,10 +765,10 @@ system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126978 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126978 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200535 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 200535 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4696310 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4696310 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5356480 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5356480 # number of overall MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5544112 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5544112 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6204282 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6204282 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31552 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31552 # number of ReadReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31148 # number of WriteReq MSHR uncacheable @@ -791,16 +789,14 @@ system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5494928000 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5494928000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5416500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5416500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 87107602500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 87107602500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103687036000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 103687036000 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 137418972500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 137418972500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 153998406000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 153998406000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6041391000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6041391000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5837295500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5837295500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11878686500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11878686500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6041391000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6041391000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035800 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035800 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018166 # mshr miss rate for WriteReq accesses @@ -813,10 +809,10 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061910 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097833 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097833 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027554 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027554 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031250 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031250 # mshr miss rate for overall accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032313 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032313 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035958 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.035958 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15625.087427 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15625.087427 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25105.994292 # average WriteReq mshr miss latency @@ -831,17 +827,14 @@ system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27401.341412 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27401.341412 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18548.094674 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18548.094674 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19357.308531 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19357.308531 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24786.471215 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24786.471215 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24821.309863 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24821.309863 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191474.106237 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191474.106237 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187405.146398 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187405.146398 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189452.735247 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189452.735247 # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96353.923445 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96353.923445 # average overall mshr uncacheable latency system.cpu0.icache.tags.replacements 10516028 # number of replacements system.cpu0.icache.tags.tagsinuse 511.897153 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 249911266 # Total number of references to valid blocks. @@ -900,8 +893,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 10516028 # number of writebacks system.cpu0.icache.writebacks::total 10516028 # number of writebacks system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10516550 # number of ReadReq MSHR misses @@ -940,7 +931,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 8036343 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 8037705 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 1205 # number of redundant prefetches already in prefetch queue @@ -1158,8 +1148,6 @@ system.cpu0.l2cache.blocked::no_mshrs 0 # nu system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.fast_writes 0 # number of fast writes performed -system.cpu0.l2cache.cache_copies 0 # number of cache copies performed system.cpu0.l2cache.unused_prefetches 49728 # number of HardPF blocks evicted w/o reference system.cpu0.l2cache.writebacks::writebacks 1630983 # number of writebacks system.cpu0.l2cache.writebacks::total 1630983 # number of writebacks @@ -1255,11 +1243,9 @@ system.cpu0.l2cache.overall_mshr_miss_latency::total 124548471241 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5788797000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 12784952000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5603650500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5603650500 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11392447500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 18388602500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5788797000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12784952000 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026408 # mshr miss rate for ReadReq accesses @@ -1325,12 +1311,9 @@ system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43209.493938 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183468.464757 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152454.084735 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179904.022730 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179904.022730 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181697.727273 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159888.378301 # average overall mshr uncacheable latency -system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92325.311005 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111164.795799 # average overall mshr uncacheable latency system.cpu0.toL2Bus.snoop_filter.tot_requests 33857668 # Total number of requests made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_requests 17264460 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3128 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1653,10 +1636,10 @@ system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1678906 system.cpu1.dcache.LoadLockedReq_hits::total 1678906 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1638259 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 1638259 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 139703423 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 139703423 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 139904287 # number of overall hits -system.cpu1.dcache.overall_hits::total 139904287 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 139737373 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 139737373 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 139938237 # number of overall hits +system.cpu1.dcache.overall_hits::total 139938237 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 3193197 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 3193197 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 2277873 # number of WriteReq misses @@ -1669,10 +1652,10 @@ system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159945 system.cpu1.dcache.LoadLockedReq_misses::total 159945 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199493 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 199493 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5471070 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5471070 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6120062 # number of overall misses -system.cpu1.dcache.overall_misses::total 6120062 # number of overall misses +system.cpu1.dcache.demand_misses::cpu1.data 5881027 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5881027 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6530019 # number of overall misses +system.cpu1.dcache.overall_misses::total 6530019 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52208022500 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 52208022500 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51224639500 # number of WriteReq miss cycles @@ -1685,10 +1668,10 @@ system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5532212500 system.cpu1.dcache.StoreCondReq_miss_latency::total 5532212500 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5344000 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5344000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 103432662000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 103432662000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 103432662000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 103432662000 # number of overall miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 118332403000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 118332403000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 118332403000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 118332403000 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 76856004 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 76856004 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 68318489 # number of WriteReq accesses(hits+misses) @@ -1701,10 +1684,10 @@ system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1838851 system.cpu1.dcache.LoadLockedReq_accesses::total 1838851 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837752 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 1837752 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 145174493 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 145174493 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 146024349 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 146024349 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 145618400 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 145618400 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 146468256 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 146468256 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041548 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.041548 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033342 # miss rate for WriteReq accesses @@ -1717,10 +1700,10 @@ system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086981 system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086981 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108553 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108553 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037686 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.037686 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041911 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.041911 # miss rate for overall accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040387 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.040387 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044583 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044583 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16349.765611 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 16349.765611 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22487.926017 # average WriteReq miss latency @@ -1733,18 +1716,16 @@ system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27731.361501 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27731.361501 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18905.380849 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18905.380849 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16900.590550 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16900.590550 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20121.043995 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20121.043995 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18121.295359 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18121.295359 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 5011891 # number of writebacks system.cpu1.dcache.writebacks::total 5011891 # number of writebacks system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 367321 # number of ReadReq MSHR hits @@ -1757,10 +1738,10 @@ system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40165 system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40165 # number of LoadLockedReq MSHR hits system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 85 # number of StoreCondReq MSHR hits system.cpu1.dcache.StoreCondReq_mshr_hits::total 85 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310532 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1310532 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310532 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1310532 # number of overall MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310590 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1310590 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310590 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1310590 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2825876 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 2825876 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1334662 # number of WriteReq MSHR misses @@ -1773,10 +1754,10 @@ system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119780 system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119780 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199408 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 199408 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4160538 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4160538 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4809167 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4809167 # number of overall MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4570437 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4570437 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5219066 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5219066 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7337 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7337 # number of ReadReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable @@ -1797,16 +1778,14 @@ system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5327664500 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5327664500 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4914500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4914500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 71363385000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 71363385000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87278174000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 87278174000 # number of overall MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 85847670500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 85847670500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101762459500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 101762459500 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 919733500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 919733500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1094820000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1094820000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2014553500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2014553500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 919733500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 919733500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036768 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036768 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019536 # mshr miss rate for WriteReq accesses @@ -1819,10 +1798,10 @@ system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065139 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065139 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108506 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108506 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028659 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028659 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032934 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032934 # mshr miss rate for overall accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031386 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031386 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14625.215685 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14625.215685 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22503.329682 # average WriteReq mshr miss latency @@ -1837,17 +1816,14 @@ system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26717.406022 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26717.406022 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17152.441583 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17152.441583 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18148.293457 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18148.293457 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18783.252127 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18783.252127 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19498.212803 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19498.212803 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125355.526782 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125355.526782 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143282.292894 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 143282.292894 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134500.834557 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134500.834557 # average overall mshr uncacheable latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 61405.628255 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 61405.628255 # average overall mshr uncacheable latency system.cpu1.icache.tags.replacements 8449872 # number of replacements system.cpu1.icache.tags.tagsinuse 506.781387 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 217357255 # Total number of references to valid blocks. @@ -1906,8 +1882,6 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 8449872 # number of writebacks system.cpu1.icache.writebacks::total 8449872 # number of writebacks system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8450384 # number of ReadReq MSHR misses @@ -1946,7 +1920,6 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 139978.494624 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 139978.494624 # average overall mshr uncacheable latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 7137751 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 7137894 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 127 # number of redundant prefetches already in prefetch queue @@ -2162,8 +2135,6 @@ system.cpu1.l2cache.blocked::no_mshrs 0 # nu system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.fast_writes 0 # number of fast writes performed -system.cpu1.l2cache.cache_copies 0 # number of cache copies performed system.cpu1.l2cache.unused_prefetches 46108 # number of HardPF blocks evicted w/o reference system.cpu1.l2cache.writebacks::writebacks 1173247 # number of writebacks system.cpu1.l2cache.writebacks::total 1173247 # number of writebacks @@ -2256,11 +2227,9 @@ system.cpu1.l2cache.overall_mshr_miss_latency::total 101937567348 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12274000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 860931500 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 873205500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1037437000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1037437000 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12274000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1898368500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1910642500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 860931500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 873205500 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.031430 # mshr miss rate for ReadReq accesses @@ -2324,12 +2293,9 @@ system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37793.329747 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117341.079460 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117524.293405 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 135772.411988 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 135772.411988 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126743.790893 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126776.093159 # average overall mshr uncacheable latency -system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 57479.736948 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57939.453255 # average overall mshr uncacheable latency system.cpu1.toL2Bus.snoop_filter.tot_requests 27757324 # Total number of requests made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14199775 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1809 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -2491,11 +2457,11 @@ system.iocache.WriteReq_misses::total 3 # nu system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses -system.iocache.demand_misses::total 8917 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115861 # number of demand (read+write) misses +system.iocache.demand_misses::total 115901 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8877 # number of overall misses -system.iocache.overall_misses::total 8917 # number of overall misses +system.iocache.overall_misses::realview.ide 115861 # number of overall misses +system.iocache.overall_misses::total 115901 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::realview.ide 1651659585 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 1656859085 # number of ReadReq miss cycles @@ -2504,11 +2470,11 @@ system.iocache.WriteReq_miss_latency::total 369000 # system.iocache.WriteLineReq_miss_latency::realview.ide 13563940301 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 13563940301 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1651659585 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1657228085 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15215599886 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15221168386 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1651659585 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1657228085 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15215599886 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15221168386 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) @@ -2517,11 +2483,11 @@ system.iocache.WriteReq_accesses::total 3 # nu system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115861 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115901 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115861 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115901 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2543,19 +2509,17 @@ system.iocache.WriteReq_avg_miss_latency::total 123000 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126784.755674 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 126784.755674 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 185850.407648 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131329.051397 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 185850.407648 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131329.051397 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 32764 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 3385 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 9.679173 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106951 # number of writebacks system.iocache.writebacks::total 106951 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses @@ -2566,11 +2530,11 @@ system.iocache.WriteReq_mshr_misses::total 3 # system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115861 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115901 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 115861 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115901 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::realview.ide 1207809585 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 1211159085 # number of ReadReq MSHR miss cycles @@ -2579,11 +2543,11 @@ system.iocache.WriteReq_mshr_miss_latency::total 219000 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8208491858 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 8208491858 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1207809585 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1211378085 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9416301443 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9419869943 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1207809585 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1211378085 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9416301443 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9419869943 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2605,12 +2569,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76726.350277 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76726.350277 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency system.l2c.tags.replacements 1387428 # number of replacements system.l2c.tags.tagsinuse 63551.257518 # Cycle average of tags in use system.l2c.tags.total_refs 6641936 # Total number of references to valid blocks. @@ -2939,8 +2902,6 @@ system.l2c.blocked::no_mshrs 13 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs 74.692308 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 1075915 # number of writebacks system.l2c.writebacks::total 1075915 # number of writebacks system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 164 # number of ReadSharedReq MSHR hits @@ -3071,14 +3032,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5220688053 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10320500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 728734017 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 11857408570 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5073884538 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 907395547 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5981280085 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10294572591 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5220688053 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10320500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1636129564 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 17838688655 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 728734017 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11857408570 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.275862 # mshr miss rate for UpgradeReq accesses @@ -3176,15 +3134,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165462.983424 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99350.240900 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129888.689437 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162895.997753 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 118753.507002 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154200.419836 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164187.760622 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83264.562249 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109250.104434 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 137138.398922 # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48660.123998 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 91156.141469 # average overall mshr uncacheable latency system.membus.trans_dist::ReadReq 91289 # Transaction distribution system.membus.trans_dist::ReadResp 902614 # Transaction distribution system.membus.trans_dist::WriteReq 38789 # Transaction distribution |