diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 5111 |
1 files changed, 2577 insertions, 2534 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 63a2010ed..5aa558433 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.443139 # Number of seconds simulated -sim_ticks 47443139283500 # Number of ticks simulated -final_tick 47443139283500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.365947 # Number of seconds simulated +sim_ticks 47365946685500 # Number of ticks simulated +final_tick 47365946685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 174986 # Simulator instruction rate (inst/s) -host_op_rate 205797 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9320406551 # Simulator tick rate (ticks/s) -host_mem_usage 765676 # Number of bytes of host memory used -host_seconds 5090.24 # Real time elapsed on the host -sim_insts 890723033 # Number of instructions simulated -sim_ops 1047557701 # Number of ops (including micro ops) simulated +host_inst_rate 174192 # Simulator instruction rate (inst/s) +host_op_rate 204861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9672451523 # Simulator tick rate (ticks/s) +host_mem_usage 763596 # Number of bytes of host memory used +host_seconds 4897.00 # Real time elapsed on the host +sim_insts 853019792 # Number of instructions simulated +sim_ops 1003201701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 111744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 91648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7668224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13156952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 13340800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 149248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 146240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3865344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 11856672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 13765376 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 430976 # Number of bytes read from this memory -system.physmem.bytes_read::total 64583224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7668224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3865344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11533568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75782720 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 65472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7833792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 12003144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10766848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 71104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 69248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2839488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 7678416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 7994432 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 439552 # Number of bytes read from this memory +system.physmem.bytes_read::total 49825880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7833792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2839488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10673280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 62800512 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 75803536 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1746 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1432 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 119816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 205599 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 208450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2332 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2285 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 60396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 185275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 215084 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6734 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1009149 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1184105 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 62821096 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1023 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1006 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 122403 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 187562 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 168232 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1111 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44367 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 119988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 124913 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6868 # Number of read requests responded to by this memory +system.physmem.num_reads::total 778555 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 981258 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1186708 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 161630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 277320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 281196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 81473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 249913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 290145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1361276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 161630 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 81473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 243103 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1597338 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 983832 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 165389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 253413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 227312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 162108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 168780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1051935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 165389 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 225337 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1325858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1597777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1597338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 161630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 277759 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 281196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 81473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 249913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 290145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2959053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1009149 # Number of read requests accepted -system.physmem.writeReqs 1850399 # Number of write requests accepted -system.physmem.readBursts 1009149 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1850399 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 64564224 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue -system.physmem.bytesWritten 115242304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 64583224 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 118279760 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 49721 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 115106 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 57845 # Per bank write bursts -system.physmem.perBankRdBursts::1 61929 # Per bank write bursts -system.physmem.perBankRdBursts::2 56818 # Per bank write bursts -system.physmem.perBankRdBursts::3 63723 # Per bank write bursts -system.physmem.perBankRdBursts::4 61880 # Per bank write bursts -system.physmem.perBankRdBursts::5 68171 # Per bank write bursts -system.physmem.perBankRdBursts::6 59739 # Per bank write bursts -system.physmem.perBankRdBursts::7 60869 # Per bank write bursts -system.physmem.perBankRdBursts::8 54876 # Per bank write bursts -system.physmem.perBankRdBursts::9 108415 # Per bank write bursts -system.physmem.perBankRdBursts::10 50407 # Per bank write bursts -system.physmem.perBankRdBursts::11 61358 # Per bank write bursts -system.physmem.perBankRdBursts::12 58228 # Per bank write bursts -system.physmem.perBankRdBursts::13 64090 # Per bank write bursts -system.physmem.perBankRdBursts::14 57873 # Per bank write bursts -system.physmem.perBankRdBursts::15 62595 # Per bank write bursts -system.physmem.perBankWrBursts::0 107469 # Per bank write bursts -system.physmem.perBankWrBursts::1 113594 # Per bank write bursts -system.physmem.perBankWrBursts::2 115011 # Per bank write bursts -system.physmem.perBankWrBursts::3 118413 # Per bank write bursts -system.physmem.perBankWrBursts::4 118243 # Per bank write bursts -system.physmem.perBankWrBursts::5 118449 # Per bank write bursts -system.physmem.perBankWrBursts::6 111339 # Per bank write bursts -system.physmem.perBankWrBursts::7 115322 # Per bank write bursts -system.physmem.perBankWrBursts::8 110047 # Per bank write bursts -system.physmem.perBankWrBursts::9 111027 # Per bank write bursts -system.physmem.perBankWrBursts::10 102767 # Per bank write bursts -system.physmem.perBankWrBursts::11 112058 # Per bank write bursts -system.physmem.perBankWrBursts::12 108184 # Per bank write bursts -system.physmem.perBankWrBursts::13 112341 # Per bank write bursts -system.physmem.perBankWrBursts::14 110504 # Per bank write bursts -system.physmem.perBankWrBursts::15 115893 # Per bank write bursts +system.physmem.bw_write::total 1326292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1325858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 165389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 253847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 227312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 162108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 168780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2378227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 778555 # Number of read requests accepted +system.physmem.writeReqs 1622091 # Number of write requests accepted +system.physmem.readBursts 778555 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1622091 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 49803520 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue +system.physmem.bytesWritten 100652928 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 49825880 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 103669672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49366 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 111816 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 42060 # Per bank write bursts +system.physmem.perBankRdBursts::1 53156 # Per bank write bursts +system.physmem.perBankRdBursts::2 42442 # Per bank write bursts +system.physmem.perBankRdBursts::3 47567 # Per bank write bursts +system.physmem.perBankRdBursts::4 45723 # Per bank write bursts +system.physmem.perBankRdBursts::5 54413 # Per bank write bursts +system.physmem.perBankRdBursts::6 50594 # Per bank write bursts +system.physmem.perBankRdBursts::7 44772 # Per bank write bursts +system.physmem.perBankRdBursts::8 41306 # Per bank write bursts +system.physmem.perBankRdBursts::9 93457 # Per bank write bursts +system.physmem.perBankRdBursts::10 34541 # Per bank write bursts +system.physmem.perBankRdBursts::11 47870 # Per bank write bursts +system.physmem.perBankRdBursts::12 47765 # Per bank write bursts +system.physmem.perBankRdBursts::13 46143 # Per bank write bursts +system.physmem.perBankRdBursts::14 39677 # Per bank write bursts +system.physmem.perBankRdBursts::15 46694 # Per bank write bursts +system.physmem.perBankWrBursts::0 94318 # Per bank write bursts +system.physmem.perBankWrBursts::1 104450 # Per bank write bursts +system.physmem.perBankWrBursts::2 99318 # Per bank write bursts +system.physmem.perBankWrBursts::3 101345 # Per bank write bursts +system.physmem.perBankWrBursts::4 99792 # Per bank write bursts +system.physmem.perBankWrBursts::5 104837 # Per bank write bursts +system.physmem.perBankWrBursts::6 100210 # Per bank write bursts +system.physmem.perBankWrBursts::7 98464 # Per bank write bursts +system.physmem.perBankWrBursts::8 93421 # Per bank write bursts +system.physmem.perBankWrBursts::9 95649 # Per bank write bursts +system.physmem.perBankWrBursts::10 88541 # Per bank write bursts +system.physmem.perBankWrBursts::11 99820 # Per bank write bursts +system.physmem.perBankWrBursts::12 96824 # Per bank write bursts +system.physmem.perBankWrBursts::13 96750 # Per bank write bursts +system.physmem.perBankWrBursts::14 94484 # Per bank write bursts +system.physmem.perBankWrBursts::15 104479 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 251 # Number of times write queue was full causing retry -system.physmem.totGap 47443137361000 # Total gap between requests +system.physmem.numWrRetry 276 # Number of times write queue was full causing retry +system.physmem.totGap 47365944763000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 37 # Read request sizes (log2) +system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1009107 # Read request sizes (log2) +system.physmem.readPktSize::6 778525 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) -system.physmem.writePktSize::3 2601 # Write request sizes (log2) +system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1847796 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 676531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 29357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 26883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 24732 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 22204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 5388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1619517 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 550292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 82276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 20492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 18686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 17057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 12648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -188,169 +188,167 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 43843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 64070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 91575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 102673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 109951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 108175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 103872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 98771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 95896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 92750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 92610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 110859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 98695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 94070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 109570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 97266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 90790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 87057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 6313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 832 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1017757 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 176.667963 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 107.708761 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 246.723752 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 648817 63.75% 63.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 197916 19.45% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48918 4.81% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23519 2.31% 90.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 17229 1.69% 92.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11413 1.12% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8164 0.80% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7432 0.73% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 54349 5.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1017757 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 78960 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.776165 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 140.389446 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 78957 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 40446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 59954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 84735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 94224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 98939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 95817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 91113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 85467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 82456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 78613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 78193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 94725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 83224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 77979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 91163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 80486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 75147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 72304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 873 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 836953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 179.765373 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 108.063876 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 253.948875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 534704 63.89% 63.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 162086 19.37% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38261 4.57% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 18116 2.16% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12763 1.52% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8799 1.05% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6603 0.79% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6067 0.72% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 49554 5.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 836953 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65558 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 11.869901 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 153.975731 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 65556 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 78960 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 78960 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.804724 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.151306 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.211366 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 71201 90.17% 90.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 3689 4.67% 94.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 1610 2.04% 96.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 798 1.01% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 435 0.55% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 299 0.38% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 436 0.55% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 198 0.25% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 63 0.08% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 19 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 61 0.08% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 31 0.04% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 15 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 6 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 4 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 5 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 7 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 4 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 9 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 8 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 9 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 14 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 65558 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65558 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.989475 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.876910 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.036255 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 57911 88.34% 88.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 3625 5.53% 93.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 1537 2.34% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 756 1.15% 97.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 457 0.70% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 339 0.52% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 446 0.68% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 180 0.27% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 59 0.09% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 25 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 57 0.09% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 41 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 16 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 6 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.00% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 7 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 6 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 4 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 12 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 9 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 13 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 20 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 78960 # Writes before turning the bus around for reads -system.physmem.totQLat 36416381887 # Total ticks spent queuing -system.physmem.totMemAccLat 55331681887 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5044080000 # Total ticks spent in databus transfers -system.physmem.avgQLat 36098.14 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 65558 # Writes before turning the bus around for reads +system.physmem.totQLat 24526926504 # Total ticks spent queuing +system.physmem.totMemAccLat 39117801504 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3890900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 31518.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54848.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.36 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.49 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 50268.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing -system.physmem.readRowHits 756126 # Number of row buffer hits during reads -system.physmem.writeRowHits 1035585 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.51 # Row buffer hit rate for writes -system.physmem.avgGap 16591131.66 # Average gap between requests -system.physmem.pageHitRate 63.77 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3944550960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2152284750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3829511400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5947512480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3098754740640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1192681206900 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27419667632250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31726977439380 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.736993 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45614623336779 # Time in different power states -system.physmem_0.memoryStateTime::REF 1584230440000 # Time in different power states +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.72 # Average write queue length when enqueuing +system.physmem.readRowHits 582169 # Number of row buffer hits during reads +system.physmem.writeRowHits 931750 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.24 # Row buffer hit rate for writes +system.physmem.avgGap 19730499.53 # Average gap between requests +system.physmem.pageHitRate 64.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3287730600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1793900625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2969101200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5201632080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1175633111385 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27388306372500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31670904725190 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.643023 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45562569995604 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581652800000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 244280410221 # Time in different power states +system.physmem_0.memoryStateTime::ACT 221716854896 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3749639040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2045934000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4039144200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5720654160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3098754740640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1188668792790 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27423187293750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31726166198580 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.719894 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45620445429017 # Time in different power states -system.physmem_1.memoryStateTime::REF 1584230440000 # Time in different power states +system.physmem_1.actEnergy 3039558480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1658489250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3100125600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4989373200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1167524389710 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27395419294500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31669444107540 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.612186 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45574402608448 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581652800000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 238458431983 # Time in different power states +system.physmem_1.memoryStateTime::ACT 209885438552 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -384,15 +382,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 130059643 # Number of BP lookups -system.cpu0.branchPred.condPredicted 92054393 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5970282 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 98035548 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 70777475 # Number of BTB hits +system.cpu0.branchPred.lookups 133649210 # Number of BP lookups +system.cpu0.branchPred.condPredicted 93568356 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6412350 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 100434532 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 71867706 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.195725 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15296635 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1065115 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.556769 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 16148203 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1115497 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -423,61 +421,67 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 268213 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 268213 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8180 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 73055 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 268213 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 268213 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 268213 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 81235 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 18802.895870 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17058.372218 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 13418.609606 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 80487 99.08% 99.08% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 639 0.79% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 31 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 33 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 28 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 81235 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 281840 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 281840 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8577 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76588 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 281840 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 281840 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 281840 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 85165 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 18850.134868 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17191.967454 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 12262.040349 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 80924 95.02% 95.02% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3552 4.17% 99.19% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 385 0.45% 99.64% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 20 0.02% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 25 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 16 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 85165 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 73055 89.93% 89.93% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 8180 10.07% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 81235 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 268213 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 76588 89.93% 89.93% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8577 10.07% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 85165 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 281840 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 268213 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81235 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 281840 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85165 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81235 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 349448 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85165 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 367005 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 82876233 # DTB read hits -system.cpu0.dtb.read_misses 221834 # DTB read misses -system.cpu0.dtb.write_hits 73950839 # DTB write hits -system.cpu0.dtb.write_misses 46379 # DTB write misses +system.cpu0.dtb.read_hits 86621651 # DTB read hits +system.cpu0.dtb.read_misses 235326 # DTB read misses +system.cpu0.dtb.write_hits 77269391 # DTB write hits +system.cpu0.dtb.write_misses 46514 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 33850 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2174 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9634 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36825 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2231 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9213 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10897 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 83098067 # DTB read accesses -system.cpu0.dtb.write_accesses 73997218 # DTB write accesses +system.cpu0.dtb.perms_faults 11443 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 86856977 # DTB read accesses +system.cpu0.dtb.write_accesses 77315905 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 156827072 # DTB hits -system.cpu0.dtb.misses 268213 # DTB misses -system.cpu0.dtb.accesses 157095285 # DTB accesses +system.cpu0.dtb.hits 163891042 # DTB hits +system.cpu0.dtb.misses 281840 # DTB misses +system.cpu0.dtb.accesses 164172882 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,191 +511,191 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 59559 # Table walker walks requested -system.cpu0.itb.walker.walksLong 59559 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 562 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52025 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 59559 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 59559 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 59559 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 52587 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 21528.762508 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 19318.036298 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 15879.557576 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 47969 91.22% 91.22% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3703 7.04% 98.26% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 280 0.53% 98.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 523 0.99% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 24 0.05% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 24 0.05% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 27 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 16 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 8 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 66347 # Table walker walks requested +system.cpu0.itb.walker.walksLong 66347 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 679 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58898 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 66347 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 66347 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 66347 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 59577 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 21233.631049 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 19420.255520 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 13392.583355 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 54894 92.14% 92.14% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3878 6.51% 98.65% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 278 0.47% 99.12% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 464 0.78% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 21 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 10 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 52587 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 59577 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 52025 98.93% 98.93% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 562 1.07% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 52587 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 58898 98.86% 98.86% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 679 1.14% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 59577 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59559 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59559 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66347 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66347 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52587 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52587 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 112146 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 232580630 # ITB inst hits -system.cpu0.itb.inst_misses 59559 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59577 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59577 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 125924 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 239632917 # ITB inst hits +system.cpu0.itb.inst_misses 66347 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 23871 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26379 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 192056 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 196328 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 232640189 # ITB inst accesses -system.cpu0.itb.hits 232580630 # DTB hits -system.cpu0.itb.misses 59559 # DTB misses -system.cpu0.itb.accesses 232640189 # DTB accesses -system.cpu0.numCycles 928928804 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 239699264 # ITB inst accesses +system.cpu0.itb.hits 239632917 # DTB hits +system.cpu0.itb.misses 66347 # DTB misses +system.cpu0.itb.accesses 239699264 # DTB accesses +system.cpu0.numCycles 955623985 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 429144762 # Number of instructions committed -system.cpu0.committedOps 504441860 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 43734034 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 3788 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93957994041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.164605 # CPI: cycles per instruction -system.cpu0.ipc 0.461978 # IPC: instructions per cycle +system.cpu0.committedInsts 445844997 # Number of instructions committed +system.cpu0.committedOps 524389125 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 43457031 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4220 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93776986984 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.143400 # CPI: cycles per instruction +system.cpu0.ipc 0.466549 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 12678 # number of quiesce instructions executed -system.cpu0.tickCycles 694752800 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 234176004 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5394073 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.331401 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 148625740 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5394584 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.550918 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 5096417500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.331401 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938147 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938147 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 13187 # number of quiesce instructions executed +system.cpu0.tickCycles 717454138 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 238169847 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5506052 # number of replacements +system.cpu0.dcache.tags.tagsinuse 502.001203 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155497940 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5506563 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.238656 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 5093256500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.001203 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980471 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.980471 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 316412315 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 316412315 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75879605 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75879605 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68405292 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 68405292 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 266627 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 266627 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 249000 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 249000 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1685353 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1685353 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1648257 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1648257 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 144284897 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 144284897 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 144551524 # number of overall hits -system.cpu0.dcache.overall_hits::total 144551524 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3254530 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3254530 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2315784 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2315784 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 640707 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 640707 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 788472 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 788472 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 144645 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 144645 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 180684 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 180684 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5570314 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5570314 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6211021 # number of overall misses -system.cpu0.dcache.overall_misses::total 6211021 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 49481056746 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 49481056746 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 45032988844 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 45032988844 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 32697185728 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32697185728 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2134918217 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2134918217 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3848217698 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3848217698 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3587000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3587000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 94514045590 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 94514045590 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 94514045590 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 94514045590 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 79134135 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 79134135 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 70721076 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 70721076 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 907334 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 907334 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1037472 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1037472 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1829998 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1829998 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1828941 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1828941 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 149855211 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 149855211 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 150762545 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 150762545 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041127 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.041127 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032745 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.032745 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.706142 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.706142 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.759994 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.759994 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098792 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098792 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037171 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.037171 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041197 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.041197 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15203.748850 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15203.748850 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19446.109328 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19446.109328 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41469.051188 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41469.051188 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14759.709751 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14759.709751 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21298.054604 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21298.054604 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 330491760 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 330491760 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 79543100 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 79543100 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 71719508 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 71719508 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 278613 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 278613 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 256505 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 256505 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1617523 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1617523 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1589938 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1589938 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 151262608 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 151262608 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 151541221 # number of overall hits +system.cpu0.dcache.overall_hits::total 151541221 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3339841 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3339841 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2311852 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2311852 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 620748 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 620748 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 822680 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 822680 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 157499 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 157499 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 183638 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 183638 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5651693 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5651693 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6272441 # number of overall misses +system.cpu0.dcache.overall_misses::total 6272441 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 49670372012 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 49670372012 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 43497452544 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 43497452544 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 32835554230 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32835554230 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2312206455 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2312206455 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3898320876 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3898320876 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3663000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3663000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 93167824556 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 93167824556 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 93167824556 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 93167824556 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 82882941 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 82882941 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74031360 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74031360 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899361 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 899361 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1079185 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1079185 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1775022 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1775022 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1773576 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1773576 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 156914301 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 156914301 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 157813662 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 157813662 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040296 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.040296 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031228 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.031228 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.690210 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.690210 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.762316 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.762316 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088731 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088731 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103541 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103541 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036018 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.036018 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039746 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.039746 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14872.076848 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14872.076848 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18814.981471 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18814.981471 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 39912.911740 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39912.911740 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14680.769116 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14680.769116 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21228.290855 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21228.290855 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16967.453826 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16967.453826 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15217.151188 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15217.151188 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16484.940806 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16484.940806 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14853.519476 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14853.519476 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -700,155 +704,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3714069 # number of writebacks -system.cpu0.dcache.writebacks::total 3714069 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 414551 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 414551 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 973091 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 973091 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 89 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 89 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40213 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 40213 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 42 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 42 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1387642 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1387642 # 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number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3248500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61545107041 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 61545107041 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75975107148 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 75975107148 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5918601247 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5918601247 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5692373000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5692373000 # 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mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057067 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057067 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098769 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098769 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027911 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027911 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031956 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031956 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13107.428482 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13107.428482 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18113.064869 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18113.064869 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22723.550774 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22723.550774 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39961.754657 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39961.754657 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12955.122865 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12955.122865 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19743.989609 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19743.989609 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3760610 # number of writebacks +system.cpu0.dcache.writebacks::total 3760610 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 413115 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 413115 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 966709 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 966709 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 96 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 96 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 42490 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 42490 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 52 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 52 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1379824 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1379824 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1379824 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1379824 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2926726 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2926726 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1345143 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1345143 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 614981 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 614981 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 822584 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 822584 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 115009 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 115009 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 183586 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 183586 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4271869 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4271869 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4886850 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4886850 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 33259 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33259 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 33163 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33163 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 66422 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 66422 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37662767131 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37662767131 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23537156289 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23537156289 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13208319439 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13208319439 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31592370271 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 31592370271 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1454810141 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1454810141 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3611856094 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3611856094 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3160000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3160000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61199923420 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61199923420 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74408242859 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 74408242859 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5916157251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5916157251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5692664250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5692664250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11608821501 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11608821501 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035312 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035312 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018170 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018170 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.683798 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.683798 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762227 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.762227 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064793 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064793 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103512 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103512 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027224 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027224 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030966 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030966 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12868.566149 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12868.566149 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17497.884083 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17497.884083 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21477.605713 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21477.605713 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38406.254280 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 38406.254280 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12649.533002 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12649.533002 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19673.919003 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19673.919003 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14714.303928 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14714.303928 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15770.008558 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15770.008558 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14326.264083 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14326.264083 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15226.217882 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15226.217882 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177881.393036 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177881.393036 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171657.095257 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171657.095257 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174773.742149 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174773.742149 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 9298569 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.930207 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 223083541 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9299081 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 23.989848 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 24039613250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930207 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 9994306 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.930109 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 229434949 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9994818 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 22.955390 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 24035147250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930109 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999863 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 423 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 474064354 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 474064354 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 223083541 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 223083541 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 223083541 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 223083541 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 223083541 # number of overall hits -system.cpu0.icache.overall_hits::total 223083541 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9299091 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9299091 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9299091 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9299091 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9299091 # number of overall misses -system.cpu0.icache.overall_misses::total 9299091 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92099739258 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 92099739258 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 92099739258 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 92099739258 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 92099739258 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 92099739258 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 232382632 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 232382632 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 232382632 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 232382632 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 232382632 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 232382632 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040016 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.040016 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040016 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.040016 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040016 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.040016 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9904.165822 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9904.165822 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9904.165822 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9904.165822 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9904.165822 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9904.165822 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 488854379 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 488854379 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 229434949 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 229434949 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 229434949 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 229434949 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 229434949 # number of overall hits +system.cpu0.icache.overall_hits::total 229434949 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9994827 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9994827 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9994827 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9994827 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9994827 # number of overall misses +system.cpu0.icache.overall_misses::total 9994827 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 98560798487 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 98560798487 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 98560798487 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 98560798487 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 98560798487 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 98560798487 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 239429776 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 239429776 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 239429776 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 239429776 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 239429776 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 239429776 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.041744 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.041744 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.041744 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.041744 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.041744 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.041744 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9861.181038 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9861.181038 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9861.181038 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9861.181038 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9861.181038 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9861.181038 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -857,464 +867,467 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9299091 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9299091 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9299091 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9299091 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9299091 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9299091 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 82773169690 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 82773169690 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 82773169690 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 82773169690 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 82773169690 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 82773169690 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9994827 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9994827 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9994827 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9994827 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9994827 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9994827 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52307 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 52307 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52307 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 52307 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 88537189453 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 88537189453 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88537189453 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 88537189453 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 88537189453 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 88537189453 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040016 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040016 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040016 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.040016 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040016 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.040016 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8901.210848 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8901.210848 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8901.210848 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8901.210848 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8901.210848 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8901.210848 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.041744 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.041744 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.041744 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8858.301345 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8858.301345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8858.301345 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92413.964670 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92413.964670 # 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number of replacements -system.cpu0.l2cache.tags.tagsinuse 15991.413435 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 14807300 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2641343 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.605974 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5822698500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4879.764539 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 24.400359 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 12.549912 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 6476.155414 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3443.547426 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1154.995785 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.297837 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001489 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000766 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.395273 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.210177 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.070495 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.976038 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 899 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 100 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14803 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 9 # 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mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079621 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256397 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231279 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231279 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252041 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.130125 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252041 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.181983 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27403.946250 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25858.743437 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46843.898684 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43693.358009 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43693.358009 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20356.764149 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20356.764149 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14871.267151 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14871.267151 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 907166 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 907166 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39927.981557 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39927.981557 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30115.739692 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27728.591352 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30115.739692 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 32724.888480 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.174466 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26070.333025 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24914.421505 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39284.329024 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 39284.329024 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42944.709754 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42944.709754 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20269.613166 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20269.613166 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14936.844150 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14936.844150 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 441333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 441333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 37752.863775 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 37752.863775 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28603.508173 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26584.661076 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28603.508173 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39284.329024 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 29812.315639 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169879.438648 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117349.075567 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164156.605253 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164156.605253 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 167022.157568 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130423.203261 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 16236238 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 13810704 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33172 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33172 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3714064 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1025800 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1145042 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 786829 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 475552 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 336189 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 478151 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1267323 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1138296 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18702794 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15835764 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 326673 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1038123 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 35903354 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 598489344 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 596885449 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190176 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3791640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1200356609 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4763261 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 24114639 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.184867 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.388190 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 16764997 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14635279 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33163 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3760609 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 997781 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1159753 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 821059 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 475624 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 336764 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 482191 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1257493 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1141567 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20094267 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16118866 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1099589 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 37679488 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 643016512 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 607271415 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1349104 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4039944 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1255676975 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4414025 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 24791334 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.197604 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.398192 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 19656632 81.51% 81.51% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 4458007 18.49% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 19892474 80.24% 80.24% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4898860 19.76% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 24114639 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14405309409 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 24791334 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14940946397 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 207723992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 210442490 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14053020534 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 15097277267 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7776245419 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7911607131 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 178137962 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 198319454 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 564500428 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 594828175 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 140284857 # Number of BP lookups -system.cpu1.branchPred.condPredicted 99939687 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6358953 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 105820632 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 77032296 # Number of BTB hits +system.cpu1.branchPred.lookups 123549187 # Number of BP lookups +system.cpu1.branchPred.condPredicted 87841692 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5708078 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 93157119 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 67436708 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.795158 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16359380 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1035022 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.390289 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 14460012 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 934859 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1344,61 +1357,65 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 298079 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 298079 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11270 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91179 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 298079 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 298079 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 298079 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 102449 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 19055.295776 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17104.036055 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15328.339502 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 101103 98.69% 98.69% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1144 1.12% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 36 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 73 0.07% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 102449 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1267166444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1267166444 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1267166444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 91179 89.00% 89.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11270 11.00% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 102449 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 298079 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 259362 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 259362 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8416 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76621 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 259362 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 259362 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 259362 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 85037 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 18225.042946 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 16628.571422 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 11774.469557 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 81545 95.89% 95.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2790 3.28% 99.17% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 403 0.47% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 25 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 11 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 9 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 14 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 11 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 85037 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1261494444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1261494444 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1261494444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 76621 90.10% 90.10% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8416 9.90% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 85037 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259362 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 298079 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102449 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259362 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85037 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102449 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 400528 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85037 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 344399 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91176680 # DTB read hits -system.cpu1.dtb.read_misses 248433 # DTB read misses -system.cpu1.dtb.write_hits 79002879 # DTB write hits -system.cpu1.dtb.write_misses 49646 # DTB write misses +system.cpu1.dtb.read_hits 80542266 # DTB read hits +system.cpu1.dtb.read_misses 214982 # DTB read misses +system.cpu1.dtb.write_hits 69249357 # DTB write hits +system.cpu1.dtb.write_misses 44380 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 41482 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 884 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7879 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 35601 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 736 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6438 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11586 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91425113 # DTB read accesses -system.cpu1.dtb.write_accesses 79052525 # DTB write accesses +system.cpu1.dtb.perms_faults 9960 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 80757248 # DTB read accesses +system.cpu1.dtb.write_accesses 69293737 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 170179559 # DTB hits -system.cpu1.dtb.misses 298079 # DTB misses -system.cpu1.dtb.accesses 170477638 # DTB accesses +system.cpu1.dtb.hits 149791623 # DTB hits +system.cpu1.dtb.misses 259362 # DTB misses +system.cpu1.dtb.accesses 150050985 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1428,194 +1445,191 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 68407 # Table walker walks requested -system.cpu1.itb.walker.walksLong 68407 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 609 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58709 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 68407 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 68407 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 68407 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 59318 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 21639.401767 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 18915.934077 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18524.659910 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 54668 92.16% 92.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 3100 5.23% 97.39% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 594 1.00% 98.39% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 801 1.35% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 32 0.05% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.02% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 58 0.10% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 60478 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60478 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 478 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50972 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60478 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60478 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60478 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 51450 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 20568.513975 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 18499.951285 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 14805.800668 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 47723 92.76% 92.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2940 5.71% 98.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 278 0.54% 99.01% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 425 0.83% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 16 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 27 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 59318 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1266435944 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1266435944 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1266435944 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 58709 98.97% 98.97% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 609 1.03% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 59318 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 51450 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1260837944 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1260837944 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1260837944 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 50972 99.07% 99.07% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 478 0.93% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 51450 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68407 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68407 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60478 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60478 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59318 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59318 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 127725 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 251160195 # ITB inst hits -system.cpu1.itb.inst_misses 68407 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 111928 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 220701471 # ITB inst hits +system.cpu1.itb.inst_misses 60478 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 30244 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25765 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 224879 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 203408 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 251228602 # ITB inst accesses -system.cpu1.itb.hits 251160195 # DTB hits -system.cpu1.itb.misses 68407 # DTB misses -system.cpu1.itb.accesses 251228602 # DTB accesses -system.cpu1.numCycles 937856787 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 220761949 # ITB inst accesses +system.cpu1.itb.hits 220701471 # DTB hits +system.cpu1.itb.misses 60478 # DTB misses +system.cpu1.itb.accesses 220761949 # DTB accesses +system.cpu1.numCycles 819495419 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 461578271 # Number of instructions committed -system.cpu1.committedOps 543115841 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 48137471 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5811 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93949323576 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.031848 # CPI: cycles per instruction -system.cpu1.ipc 0.492163 # IPC: instructions per cycle +system.cpu1.committedInsts 407174795 # Number of instructions committed +system.cpu1.committedOps 478812576 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 42038613 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5231 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93913157476 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.012638 # CPI: cycles per instruction +system.cpu1.ipc 0.496860 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5892 # number of quiesce instructions executed -system.cpu1.tickCycles 744774671 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 193082116 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5501509 # number of replacements -system.cpu1.dcache.tags.tagsinuse 462.401458 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 161882040 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5502021 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.422287 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8380046591500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 462.401458 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.903128 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.903128 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 5271 # number of quiesce instructions executed +system.cpu1.tickCycles 656184177 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 163311242 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 4776829 # number of replacements +system.cpu1.dcache.tags.tagsinuse 427.655512 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 142582647 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4777341 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.845608 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8380053198500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 427.655512 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.835265 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.835265 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 343173973 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 343173973 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 83605080 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 83605080 # 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number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141121 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195959 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 195959 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4543232 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4543232 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5201394 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5201394 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41952700254 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41952700254 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21819340170 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21819340170 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13178817169 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13178817169 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11885329605 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11885329605 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1778237950 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1778237950 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3771476218 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3771476218 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2255500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2255500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63772040424 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 63772040424 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 76950857593 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 76950857593 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 517375000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 517375000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 587265498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 587265498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1104640498 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1104640498 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036585 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036585 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017778 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017778 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.737066 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.737066 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.858147 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.858147 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096605 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096605 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027820 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027820 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031677 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031677 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.908562 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13150.908562 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16125.052135 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16125.052135 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20023.667682 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20023.667682 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26013.319512 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26013.319512 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12600.803211 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12600.803211 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19246.251604 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19246.251604 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3038485 # number of writebacks +system.cpu1.dcache.writebacks::total 3038485 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 341138 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 341138 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 817934 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 817934 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 47 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 47 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39869 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39869 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 63 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 63 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1159072 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1159072 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1159072 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1159072 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2781911 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2781911 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1183858 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1183858 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 559909 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 559909 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 418667 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 418667 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119029 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119029 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 187786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 3965769 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 3965769 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4525678 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4525678 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5083 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5083 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5087 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5087 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10170 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10170 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34163110205 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34163110205 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 18897365962 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18897365962 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10922522145 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 10922522145 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10687856416 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10687856416 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1507570159 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1507570159 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640144702 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640144702 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2571500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2571500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 53060476167 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 53060476167 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 63982998312 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 63982998312 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 518115500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 518115500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 583373999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 583373999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1101489499 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1101489499 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036120 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036120 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017767 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017767 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.732184 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.732184 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.860810 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.860810 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064579 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064579 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101958 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101958 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027607 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027607 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031338 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031338 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12280.446860 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12280.446860 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15962.527568 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15962.527568 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19507.673827 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19507.673827 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25528.299140 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25528.299140 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12665.570231 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12665.570231 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19384.537197 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19384.537197 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14036.712284 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14036.712284 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14794.275841 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14794.275841 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13379.618472 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13379.618472 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14137.770807 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14137.770807 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 101931.044659 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 101931.044659 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114679.378612 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 114679.378612 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 108307.718682 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 108307.718682 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 9531492 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.211334 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 241397065 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9532004 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.324902 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8370013399000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.211334 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990647 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990647 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 8549825 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.203595 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 211942190 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8550337 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 24.787583 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8370006207500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.203595 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990632 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990632 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 511390144 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 511390144 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 241397065 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 241397065 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 241397065 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 241397065 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 241397065 # number of overall hits -system.cpu1.icache.overall_hits::total 241397065 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 9532005 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 9532005 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 9532005 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 9532005 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 9532005 # number of overall misses -system.cpu1.icache.overall_misses::total 9532005 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 94727843232 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 94727843232 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 94727843232 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 94727843232 # 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average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1781,236 +1801,241 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9532005 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9532005 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9532005 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 9532005 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 9532005 # 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average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8935.194612 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8935.194612 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8935.194612 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8550338 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 8550338 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 8550338 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 75495426368 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 75495426368 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 75495426368 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8549000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8549000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8549000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8549000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038778 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.038778 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.038778 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8829.525379 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8829.525379 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8829.525379 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94988.888889 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94988.888889 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94988.888889 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94988.888889 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7632700 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7634373 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 1426 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6602862 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6604361 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 1239 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 974619 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2493350 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13598.009718 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 15504995 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2509448 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.178648 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9806309185500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5002.427380 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 85.119837 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.520686 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4382.194744 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3239.455000 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 801.292071 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.305324 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005195 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005342 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.267468 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.197721 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048907 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.829957 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1340 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14690 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 958 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 41 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 38 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 27 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1230 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4980 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7916 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 444 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.081787 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.896606 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 320697996 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 320697996 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 533308 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 157578 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 8712936 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2963890 # 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average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22440.200456 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27479.472783 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45129.323351 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30546.227697 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # 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average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 714333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 714333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30079.764078 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30079.764078 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23912.802013 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22970.037902 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23912.802013 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32251.883341 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25257.109948 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86577.777778 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 93929.077317 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 93801.179200 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 107178.494397 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 107178.494397 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86577.777778 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 100556.391445 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 100433.772027 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 16743915 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 14472665 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5158 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5158 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3514312 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1035959 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1137929 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 455738 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 448749 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 344575 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 466415 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 78 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1299611 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1147815 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 19064189 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15671741 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370835 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1205745 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 36312510 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 610054016 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 588145619 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1332264 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4367048 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1203898947 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4911557 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 24519969 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.188170 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.390848 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 15242466 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 12851003 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5087 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3038484 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 900400 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105427 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 417532 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 439071 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337307 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 446846 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1140783 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 991898 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17100855 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13710565 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 326713 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1037575 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 32175708 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 547227328 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 511521449 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1168464 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3734152 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1063651393 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4928167 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 22242259 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.242416 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.428544 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 19906035 81.18% 81.18% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 4613934 18.82% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 16850390 75.76% 75.76% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 5391869 24.24% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 24519969 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 13930930666 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 22242259 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 12259577677 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 160378480 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 163507981 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 14310919255 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 12835259097 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8198844119 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7129308669 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 204674963 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 180853196 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 660298903 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 571040175 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40379 # Transaction distribution -system.iobus.trans_dist::ReadResp 40379 # Transaction distribution -system.iobus.trans_dist::WriteReq 136954 # Transaction distribution -system.iobus.trans_dist::WriteResp 29970 # Transaction distribution +system.iobus.trans_dist::ReadReq 40383 # Transaction distribution +system.iobus.trans_dist::ReadResp 40383 # Transaction distribution +system.iobus.trans_dist::WriteReq 136956 # Transaction distribution +system.iobus.trans_dist::WriteResp 29972 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106984 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47768 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2240,13 +2268,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122846 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122858 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231740 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 231740 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354666 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354678 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47788 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2261,13 +2289,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155896 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355312 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 7355312 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513282 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36279000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513294 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36287000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2295,29 +2323,29 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 609062244 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 608916622 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92879000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92889000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148791282 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148804483 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 171000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115866 # number of replacements -system.iocache.tags.tagsinuse 11.306200 # Cycle average of tags in use +system.iocache.tags.replacements 115850 # number of replacements +system.iocache.tags.tagsinuse 11.297267 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115882 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115866 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9129676346000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.405197 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.901004 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.462825 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.243813 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706638 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9129662020000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.840346 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.456922 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240022 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466058 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706079 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1043187 # Number of tag accesses system.iocache.tags.data_accesses 1043187 # Number of data accesses @@ -2334,19 +2362,19 @@ system.iocache.demand_misses::total 8926 # nu system.iocache.overall_misses::realview.ethernet 40 # number of overall misses system.iocache.overall_misses::realview.ide 8886 # number of overall misses system.iocache.overall_misses::total 8926 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5190000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1626687073 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1631877073 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ethernet 5219500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1645546182 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1650765682 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19941362889 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19941362889 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5559000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1626687073 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1632246073 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5559000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1626687073 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1632246073 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19952013957 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19952013957 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5588500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1645546182 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1651134682 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5588500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1645546182 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1651134682 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) @@ -2373,29 +2401,29 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140270.270270 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183061.790795 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182884.352012 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141067.567568 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 185184.130317 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 185001.197131 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186395.749729 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 186395.749729 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 138975 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 183061.790795 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 182864.225073 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 138975 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 183061.790795 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 182864.225073 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 111964 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186495.307308 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186495.307308 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 184980.358727 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 184980.358727 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 111929 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16416 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16372 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.820419 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.836611 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106950 # number of writebacks -system.iocache.writebacks::total 106950 # number of writebacks +system.iocache.writebacks::writebacks 106949 # number of writebacks +system.iocache.writebacks::total 106949 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses @@ -2409,19 +2437,19 @@ system.iocache.demand_mshr_misses::total 8926 # nu system.iocache.overall_mshr_misses::realview.ethernet 40 # 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number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3507500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1182279102 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1185786602 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3507500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1182279102 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1185786602 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2435,628 +2463,643 @@ system.iocache.demand_mshr_miss_rate::total 1 # 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average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134395.152107 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134395.152107 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 86925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 130926.803174 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 130729.618306 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 86925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 130926.803174 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 130729.618306 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134494.877767 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134494.877767 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87687.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 133049.640108 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 132846.359175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87687.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 133049.640108 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 132846.359175 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1418934 # number of replacements -system.l2c.tags.tagsinuse 64475.403646 # Cycle average of tags in use -system.l2c.tags.total_refs 4887849 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1480275 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.301987 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8811587000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 16720.464314 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.676845 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 2.082484 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3893.344537 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5310.090712 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3772.998059 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 379.879752 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 518.261056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4648.220337 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11740.962883 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17479.422666 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.255134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000148 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059408 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.081026 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.057571 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005797 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.007908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.070926 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.179153 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.266715 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983817 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9966 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 213 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 51162 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 69 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 272 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1682 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 7941 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 195 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1978 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 11118 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 37794 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.152069 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003250 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.780670 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 63367915 # Number of tag accesses -system.l2c.tags.data_accesses 63367915 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6326 # 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number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 298336 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6350 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4103 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 758519 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 635563 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 311165 # number of demand (read+write) hits -system.l2c.demand_hits::total 3303277 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6326 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4773 # number of overall hits -system.l2c.overall_hits::cpu0.inst 672724 # number of overall hits -system.l2c.overall_hits::cpu0.data 605418 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 298336 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6350 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4103 # number of overall hits -system.l2c.overall_hits::cpu1.inst 758519 # number of overall hits -system.l2c.overall_hits::cpu1.data 635563 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 311165 # number of overall hits -system.l2c.overall_hits::total 3303277 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1746 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1432 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 67682 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 130428 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 208623 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2332 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2285 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 60547 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 132466 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 215131 # number of ReadReq misses -system.l2c.ReadReq_misses::total 822672 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 442954 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 116624 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 559578 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 45697 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 44658 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 90355 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 8940 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 8873 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 17813 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 77535 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 55004 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.175937 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.338826 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.155189 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.207638 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.060953 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.130100 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.291814 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.162828 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.748792 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.429465 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.657768 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.605841 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.619726 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.612520 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.591069 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.582704 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.587323 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.552807 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.476750 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.520860 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.131728 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.167891 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.089190 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.235600 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.338826 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155189 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.207638 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.060953 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.176373 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.291814 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.182720 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.131728 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.167891 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.089190 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.235600 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.338826 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155189 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.207638 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.060953 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.176373 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.291814 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.182720 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 77530.939959 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75096.383201 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 93115.223128 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33593.299323 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31988.946630 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33294.710494 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17811.639681 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17792.369934 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17802.261793 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17820.316999 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17806.465496 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17814.164007 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76820.995171 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69205.261160 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73892.985025 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77267.222173 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72970.748431 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 90070.760890 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77267.222173 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72970.748431 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 90070.760890 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 150351.356024 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63611.111111 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 74287.640228 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 94467.846634 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145636.010011 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88614.605858 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138052.535948 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147997.090572 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63611.111111 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81455.350118 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 107392.516300 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 921958 # Transaction distribution -system.membus.trans_dist::ReadResp 921958 # Transaction distribution -system.membus.trans_dist::WriteReq 38330 # Transaction distribution -system.membus.trans_dist::WriteResp 38330 # Transaction distribution -system.membus.trans_dist::Writeback 1184105 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 663691 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 663691 # Transaction distribution -system.membus.trans_dist::UpgradeReq 435500 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 292205 # Transaction distribution -system.membus.trans_dist::UpgradeResp 115129 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution -system.membus.trans_dist::ReadExReq 144960 # Transaction distribution -system.membus.trans_dist::ReadExResp 128452 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122846 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 709274 # Transaction distribution +system.membus.trans_dist::ReadResp 709274 # Transaction distribution +system.membus.trans_dist::WriteReq 38250 # Transaction distribution +system.membus.trans_dist::WriteResp 38250 # Transaction distribution +system.membus.trans_dist::Writeback 981258 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 638260 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 638259 # Transaction distribution +system.membus.trans_dist::UpgradeReq 441618 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 290995 # Transaction distribution +system.membus.trans_dist::UpgradeResp 111840 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 38 # Transaction distribution +system.membus.trans_dist::ReadExReq 127489 # Transaction distribution +system.membus.trans_dist::ReadExResp 110378 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122858 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25278 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5060662 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5208838 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5545416 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4347669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4495681 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336711 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336711 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4832392 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155896 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168740232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 168947996 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14122752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14122752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 183070748 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 632037 # Total snoops (count) -system.membus.snoop_fanout::samples 3551920 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139364352 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 139571776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14131264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14131264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 153703040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 640714 # Total snoops (count) +system.membus.snoop_fanout::samples 3227461 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3551920 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3227461 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3551920 # Request fanout histogram -system.membus.reqLayer0.occupancy 109974000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3227461 # Request fanout histogram +system.membus.reqLayer0.occupancy 110051499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21181500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20984500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 10917620106 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9462597488 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6186347625 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4943193797 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 152234718 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 152223017 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3100,45 +3143,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 4966231 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4959010 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38330 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38330 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2396374 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 933256 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 826108 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 485771 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 304174 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 789945 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 119 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295867 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295867 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7796872 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6899953 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 14696825 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 260005833 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 222466259 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 482472092 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1634381 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9291173 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012493 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.111071 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4701983 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4694752 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38250 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2214381 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 919435 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 812281 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 489803 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 302708 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 792511 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 280473 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 280473 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7857713 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6052239 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 13909952 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 261128039 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 189974361 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 451102400 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1657293 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8947338 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012974 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.113161 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9175099 98.75% 98.75% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 116074 1.25% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 8831258 98.70% 98.70% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 116080 1.30% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9291173 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8184497542 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8947338 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 7728831785 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2554500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2539500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4445775595 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4493592227 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4394903352 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3891101888 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |