diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt | 5324 |
1 files changed, 2654 insertions, 2670 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 9d627bc78..27dee726c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.573912 # Number of seconds simulated -sim_ticks 47573912126000 # Number of ticks simulated -final_tick 47573912126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.381663 # Number of seconds simulated +sim_ticks 47381662864000 # Number of ticks simulated +final_tick 47381662864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125865 # Simulator instruction rate (inst/s) -host_op_rate 148024 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6578075559 # Simulator tick rate (ticks/s) -host_mem_usage 723980 # Number of bytes of host memory used -host_seconds 7232.19 # Real time elapsed on the host -sim_insts 910282032 # Number of instructions simulated -sim_ops 1070541696 # Number of ops (including micro ops) simulated +host_inst_rate 174071 # Simulator instruction rate (inst/s) +host_op_rate 204726 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9833457902 # Simulator tick rate (ticks/s) +host_mem_usage 805560 # Number of bytes of host memory used +host_seconds 4818.41 # Real time elapsed on the host +sim_insts 838745469 # Number of instructions simulated +sim_ops 986455629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 153088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 136640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7678784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 42964232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 17895808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 154176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 129664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3679616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 16152336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 14975872 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 446400 # Number of bytes read from this memory -system.physmem.bytes_read::total 104366616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7678784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3679616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11358400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 83323200 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 42368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 41792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 6976384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 35367624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 9096640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 59520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 61888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3056960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12429456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 7583744 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 432640 # Number of bytes read from this memory +system.physmem.bytes_read::total 75149016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 6976384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3056960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10033344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 59523200 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 83343784 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2392 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2135 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 119981 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 671329 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 279622 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2409 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2026 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 57494 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 252393 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 233998 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6975 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1630754 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1301925 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 59543784 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 653 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 109006 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 552632 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 142135 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 930 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 967 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 47765 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 194223 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 118496 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6760 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1174229 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 930050 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1304499 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 161407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 903105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 376169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 77345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 339521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 314792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2193778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 161407 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 77345 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 238753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1751447 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 932624 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 147238 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 746441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 191987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 262326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 160057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1586036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 147238 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 211756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1256250 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1751880 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1751447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 161407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 903537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 376169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 77345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 339521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 314792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3945658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1630754 # Number of read requests accepted -system.physmem.writeReqs 1304499 # Number of write requests accepted -system.physmem.readBursts 1630754 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1304499 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 104327040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 41216 # Total number of bytes read from write queue -system.physmem.bytesWritten 83343168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 104366616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 83343784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 644 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 221732 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 95834 # Per bank write bursts -system.physmem.perBankRdBursts::1 103052 # Per bank write bursts -system.physmem.perBankRdBursts::2 97330 # Per bank write bursts -system.physmem.perBankRdBursts::3 103782 # Per bank write bursts -system.physmem.perBankRdBursts::4 100129 # Per bank write bursts -system.physmem.perBankRdBursts::5 106515 # Per bank write bursts -system.physmem.perBankRdBursts::6 99389 # Per bank write bursts -system.physmem.perBankRdBursts::7 99717 # Per bank write bursts -system.physmem.perBankRdBursts::8 91352 # Per bank write bursts -system.physmem.perBankRdBursts::9 148680 # Per bank write bursts -system.physmem.perBankRdBursts::10 90509 # Per bank write bursts -system.physmem.perBankRdBursts::11 96337 # Per bank write bursts -system.physmem.perBankRdBursts::12 96747 # Per bank write bursts -system.physmem.perBankRdBursts::13 106196 # Per bank write bursts -system.physmem.perBankRdBursts::14 95843 # Per bank write bursts -system.physmem.perBankRdBursts::15 98698 # Per bank write bursts -system.physmem.perBankWrBursts::0 79474 # Per bank write bursts -system.physmem.perBankWrBursts::1 83004 # Per bank write bursts -system.physmem.perBankWrBursts::2 79696 # Per bank write bursts -system.physmem.perBankWrBursts::3 83932 # Per bank write bursts -system.physmem.perBankWrBursts::4 80263 # Per bank write bursts -system.physmem.perBankWrBursts::5 85902 # Per bank write bursts -system.physmem.perBankWrBursts::6 82233 # Per bank write bursts -system.physmem.perBankWrBursts::7 81457 # Per bank write bursts -system.physmem.perBankWrBursts::8 76873 # Per bank write bursts -system.physmem.perBankWrBursts::9 82502 # Per bank write bursts -system.physmem.perBankWrBursts::10 77306 # Per bank write bursts -system.physmem.perBankWrBursts::11 81622 # Per bank write bursts -system.physmem.perBankWrBursts::12 79893 # Per bank write bursts -system.physmem.perBankWrBursts::13 86888 # Per bank write bursts -system.physmem.perBankWrBursts::14 78601 # Per bank write bursts -system.physmem.perBankWrBursts::15 82591 # Per bank write bursts +system.physmem.bw_write::total 1256684 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1256250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 147238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 746876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 191987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 262326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 160057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2842720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1174229 # Number of read requests accepted +system.physmem.writeReqs 932624 # Number of write requests accepted +system.physmem.readBursts 1174229 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 932624 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 75113152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37504 # Total number of bytes read from write queue +system.physmem.bytesWritten 59543040 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 75149016 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 59543784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 586 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 448232 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 71067 # Per bank write bursts +system.physmem.perBankRdBursts::1 73380 # Per bank write bursts +system.physmem.perBankRdBursts::2 69314 # Per bank write bursts +system.physmem.perBankRdBursts::3 74537 # Per bank write bursts +system.physmem.perBankRdBursts::4 66547 # Per bank write bursts +system.physmem.perBankRdBursts::5 79030 # Per bank write bursts +system.physmem.perBankRdBursts::6 66275 # Per bank write bursts +system.physmem.perBankRdBursts::7 68082 # Per bank write bursts +system.physmem.perBankRdBursts::8 68948 # Per bank write bursts +system.physmem.perBankRdBursts::9 127738 # Per bank write bursts +system.physmem.perBankRdBursts::10 63222 # Per bank write bursts +system.physmem.perBankRdBursts::11 73993 # Per bank write bursts +system.physmem.perBankRdBursts::12 67075 # Per bank write bursts +system.physmem.perBankRdBursts::13 69321 # Per bank write bursts +system.physmem.perBankRdBursts::14 63089 # Per bank write bursts +system.physmem.perBankRdBursts::15 72025 # Per bank write bursts +system.physmem.perBankWrBursts::0 57427 # Per bank write bursts +system.physmem.perBankWrBursts::1 61393 # Per bank write bursts +system.physmem.perBankWrBursts::2 59144 # Per bank write bursts +system.physmem.perBankWrBursts::3 61303 # Per bank write bursts +system.physmem.perBankWrBursts::4 56823 # Per bank write bursts +system.physmem.perBankWrBursts::5 63517 # Per bank write bursts +system.physmem.perBankWrBursts::6 54876 # Per bank write bursts +system.physmem.perBankWrBursts::7 56576 # Per bank write bursts +system.physmem.perBankWrBursts::8 56101 # Per bank write bursts +system.physmem.perBankWrBursts::9 62480 # Per bank write bursts +system.physmem.perBankWrBursts::10 54750 # Per bank write bursts +system.physmem.perBankWrBursts::11 61148 # Per bank write bursts +system.physmem.perBankWrBursts::12 54574 # Per bank write bursts +system.physmem.perBankWrBursts::13 57375 # Per bank write bursts +system.physmem.perBankWrBursts::14 53605 # Per bank write bursts +system.physmem.perBankWrBursts::15 59268 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 61 # Number of times write queue was full causing retry -system.physmem.totGap 47573910147500 # Total gap between requests +system.physmem.numWrRetry 30 # Number of times write queue was full causing retry +system.physmem.totGap 47381660751500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1630724 # Read request sizes (log2) +system.physmem.readPktSize::6 1174199 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1301925 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 998903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 383381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 53687 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 39143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 33585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 31320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 28483 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 22337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 5097 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1220 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 81 # What read queue length does an incoming req see +system.physmem.writePktSize::6 930050 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 756841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 295232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 26539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 15837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 14079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 12670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10425 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -188,162 +188,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 18448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 20938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 64725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 69469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 74724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 78159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 81831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 83061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 84591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 90322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 87643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 87918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 95292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 88789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 82985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 78170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 169 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1008532 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 186.082044 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 114.846498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 242.592795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 603416 59.83% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 198742 19.71% 79.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 66381 6.58% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35101 3.48% 89.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 23988 2.38% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 15328 1.52% 93.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10269 1.02% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9973 0.99% 95.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 45334 4.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1008532 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 74360 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.921678 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 319.874978 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 74357 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 16213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 18671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 45390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 50223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 52287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 55018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 55938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 58169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 58483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 59754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 64501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 59690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 64110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 58190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 54561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 52990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 709891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 189.684557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 114.673344 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 252.164844 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 431942 60.85% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 132623 18.68% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44376 6.25% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24102 3.40% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15088 2.13% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9957 1.40% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7669 1.08% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7642 1.08% 94.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 36492 5.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 709891 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 51534 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.773974 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 380.344580 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 51531 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 74360 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 74360 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.512601 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.043743 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.433062 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 70224 94.44% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1905 2.56% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 313 0.42% 97.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 309 0.42% 97.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 95 0.13% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 310 0.42% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 189 0.25% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 82 0.11% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 85 0.11% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 110 0.15% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 46 0.06% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 59 0.08% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 410 0.55% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 26 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 24 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 107 0.14% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 51534 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 51534 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.053324 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.386136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.764507 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 48029 93.20% 93.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1359 2.64% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 210 0.41% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 316 0.61% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 77 0.15% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 304 0.59% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 196 0.38% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 89 0.17% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 103 0.20% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 90 0.17% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 42 0.08% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 57 0.11% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 406 0.79% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 44 0.09% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 34 0.07% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 103 0.20% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 21 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 20 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 74360 # Writes before turning the bus around for reads -system.physmem.totQLat 52515283986 # Total ticks spent queuing -system.physmem.totMemAccLat 83079846486 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8150550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32215.79 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 51534 # Writes before turning the bus around for reads +system.physmem.totQLat 26583019130 # Total ticks spent queuing +system.physmem.totMemAccLat 48588825380 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5868215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22650.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 50965.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.75 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41400.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.59 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing -system.physmem.readRowHits 1305984 # Number of row buffer hits during reads -system.physmem.writeRowHits 617830 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.44 # Row buffer hit rate for writes -system.physmem.avgGap 16207771.58 # Average gap between requests -system.physmem.pageHitRate 65.61 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3848576760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2099917875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6284834400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4250627280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3107296514400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1215004983300 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27478552093500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31817337547515 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.798037 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45712218150079 # Time in different power states -system.physmem_0.memoryStateTime::REF 1588597400000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.83 # Average write queue length when enqueuing +system.physmem.readRowHits 952385 # Number of row buffer hits during reads +system.physmem.writeRowHits 441721 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.48 # Row buffer hit rate for writes +system.physmem.avgGap 22489305.50 # Average gap between requests +system.physmem.pageHitRate 66.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2710380960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1478878500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4432209600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3052442880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3094739659440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1177500235590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27396100823250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31680014630220 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.613444 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45575607610794 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582177740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 273094361171 # Time in different power states +system.physmem_0.memoryStateTime::ACT 223874273456 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3775925160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2060276625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6429961200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4187868480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3107296514400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1217449094850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27476408136000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31817607776715 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.803717 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45708592383178 # Time in different power states -system.physmem_1.memoryStateTime::REF 1588597400000 # Time in different power states +system.physmem_1.actEnergy 2656364760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1449405375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4722003000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2976166800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3094739659440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1182079758375 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27392083725750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31680707083500 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.628058 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45568857815114 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582177740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 276721037822 # Time in different power states +system.physmem_1.memoryStateTime::ACT 230624127636 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -374,18 +376,18 @@ system.realview.nvmem.bw_total::total 28 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 141076080 # Number of BP lookups -system.cpu0.branchPred.condPredicted 100250771 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6354710 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 105662880 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 77608899 # Number of BTB hits +system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 125258409 # Number of BP lookups +system.cpu0.branchPred.condPredicted 88001025 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5802079 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 93100413 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 67841086 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.449540 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16417680 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1072595 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.868727 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15085862 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1028654 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -416,63 +418,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 302583 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 302583 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11677 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91984 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 302583 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 302583 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 302583 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 103661 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22488.718033 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 20252.846239 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 20697.815033 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 102356 98.74% 98.74% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 167 0.16% 98.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 962 0.93% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 38 0.04% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 45 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 22 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 45 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 103661 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -910187592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -910187592 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -910187592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 91984 88.74% 88.74% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11677 11.26% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 103661 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302583 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 252652 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 252652 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 7537 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 66702 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 252652 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 252652 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 252652 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 74239 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22181.016716 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 20809.120487 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 13879.929548 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 73678 99.24% 99.24% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 179 0.24% 99.49% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 332 0.45% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 14 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 15 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 74239 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 66702 89.85% 89.85% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 7537 10.15% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 74239 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 252652 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302583 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 103661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 252652 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 74239 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 103661 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 406244 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 74239 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 326891 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91224751 # DTB read hits -system.cpu0.dtb.read_misses 252123 # DTB read misses -system.cpu0.dtb.write_hits 79969156 # DTB write hits -system.cpu0.dtb.write_misses 50460 # DTB write misses +system.cpu0.dtb.read_hits 81678885 # DTB read hits +system.cpu0.dtb.read_misses 209727 # DTB read misses +system.cpu0.dtb.write_hits 70936828 # DTB write hits +system.cpu0.dtb.write_misses 42925 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 39295 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 989 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 11229 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 33720 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8048 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11007 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 91476874 # DTB read accesses -system.cpu0.dtb.write_accesses 80019616 # DTB write accesses +system.cpu0.dtb.perms_faults 9709 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 81888612 # DTB read accesses +system.cpu0.dtb.write_accesses 70979753 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 171193907 # DTB hits -system.cpu0.dtb.misses 302583 # DTB misses -system.cpu0.dtb.accesses 171496490 # DTB accesses +system.cpu0.dtb.hits 152615713 # DTB hits +system.cpu0.dtb.misses 252652 # DTB misses +system.cpu0.dtb.accesses 152868365 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -502,187 +502,191 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 69790 # Table walker walks requested -system.cpu0.itb.walker.walksLong 69790 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 704 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58261 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 69790 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 69790 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 69790 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 58965 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25666.514034 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 22346.910344 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 25122.368024 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 57570 97.63% 97.63% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 8 0.01% 97.65% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1255 2.13% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 40 0.07% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 50 0.08% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 25 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 12 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 58965 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -911302092 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -911302092 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -911302092 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 58261 98.81% 98.81% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 704 1.19% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 58965 # Table walker page sizes translated +system.cpu0.itb.walker.walks 57977 # Table walker walks requested +system.cpu0.itb.walker.walksLong 57977 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 503 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 46742 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 57977 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 57977 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 57977 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 47245 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 24873.087099 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23068.832563 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17067.215870 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 43882 92.88% 92.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2853 6.04% 98.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 11 0.02% 98.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 288 0.61% 99.55% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 169 0.36% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 7 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 4 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 13 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 47245 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 46742 98.94% 98.94% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 503 1.06% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 47245 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 69790 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 69790 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57977 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57977 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58965 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58965 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 128755 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 253370493 # ITB inst hits -system.cpu0.itb.inst_misses 69790 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 47245 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 47245 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 105222 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 224840362 # ITB inst hits +system.cpu0.itb.inst_misses 57977 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28357 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24328 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 216294 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 193753 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 253440283 # ITB inst accesses -system.cpu0.itb.hits 253370493 # DTB hits -system.cpu0.itb.misses 69790 # DTB misses -system.cpu0.itb.accesses 253440283 # DTB accesses -system.cpu0.numCycles 1081338531 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 224898339 # ITB inst accesses +system.cpu0.itb.hits 224840362 # DTB hits +system.cpu0.itb.misses 57977 # DTB misses +system.cpu0.itb.accesses 224898339 # DTB accesses +system.cpu0.numCycles 954325944 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 467223626 # Number of instructions committed -system.cpu0.committedOps 548903732 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 48040966 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 5433 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 94067362325 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.314392 # CPI: cycles per instruction -system.cpu0.ipc 0.432079 # IPC: instructions per cycle +system.cpu0.committedInsts 417810947 # Number of instructions committed +system.cpu0.committedOps 490605107 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 41344261 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4694 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93809718025 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.284109 # CPI: cycles per instruction +system.cpu0.ipc 0.437807 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5510 # number of quiesce instructions executed -system.cpu0.tickCycles 755200178 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 326138353 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5943709 # number of replacements -system.cpu0.dcache.tags.tagsinuse 508.631098 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 162232873 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5944219 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.292546 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 7690193000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.631098 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993420 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.993420 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 345517845 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 345517845 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 83485003 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83485003 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 74196086 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 74196086 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 250296 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 250296 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 125849 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 125849 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1837182 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1837182 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1810329 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1810329 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 157681089 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 157681089 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 157931385 # number of overall hits -system.cpu0.dcache.overall_hits::total 157931385 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3676950 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3676950 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2497111 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2497111 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 700297 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 700297 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 789920 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 789920 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172643 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 172643 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197460 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 197460 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6174061 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6174061 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6874358 # number of overall misses -system.cpu0.dcache.overall_misses::total 6874358 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 65602264000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 65602264000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59773944000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 59773944000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 75379073500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 75379073500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2981608500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2981608500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4714245500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4714245500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5404500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5404500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 125376208000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125376208000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 125376208000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125376208000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87161953 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 87161953 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 76693197 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 76693197 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 950593 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 950593 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 915769 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 915769 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2009825 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2009825 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2007789 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2007789 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 163855150 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 163855150 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164805743 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 164805743 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.042185 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.042185 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032560 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.032560 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.736695 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.736695 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.862576 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.862576 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085900 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085900 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098347 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098347 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037680 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.037680 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041712 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.041712 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17841.489278 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17841.489278 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23937.239474 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23937.239474 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 95426.212148 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 95426.212148 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17270.370070 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17270.370070 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23874.432797 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23874.432797 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 4756 # number of quiesce instructions executed +system.cpu0.tickCycles 674001287 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 280324657 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5190067 # number of replacements +system.cpu0.dcache.tags.tagsinuse 482.757722 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 144829115 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5190578 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.902310 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.757722 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.942886 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.942886 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 307937411 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 307937411 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 74836049 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 74836049 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 65744025 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 65744025 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 248898 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 248898 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 135683 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 135683 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1688860 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1688860 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1659238 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1659238 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 140580074 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 140580074 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 140828972 # number of overall hits +system.cpu0.dcache.overall_hits::total 140828972 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3204136 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3204136 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2171939 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2171939 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 583430 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 583430 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 728874 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 728874 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 150550 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 150550 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 178568 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 178568 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5376075 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5376075 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5959505 # number of overall misses +system.cpu0.dcache.overall_misses::total 5959505 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 51043675000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 51043675000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55065851500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 55065851500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 67163849000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 67163849000 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2254990500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2254990500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5008928500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5008928500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5076500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5076500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 106109526500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 106109526500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 106109526500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 106109526500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78040185 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78040185 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 67915964 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 67915964 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 832328 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 832328 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 864557 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 864557 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1839410 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1839410 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1837806 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1837806 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 145956149 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 145956149 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 146788477 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 146788477 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041058 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.041058 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031980 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.031980 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.700962 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.700962 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843061 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.843061 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.081847 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.081847 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097164 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097164 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036833 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.036833 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040599 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.040599 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15930.558191 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15930.558191 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25353.314020 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25353.314020 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 92147.406822 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 92147.406822 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14978.349386 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14978.349386 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28050.538170 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28050.538170 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20306.927321 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20306.927321 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18238.242466 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18238.242466 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19737.359784 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19737.359784 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17805.090607 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17805.090607 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,161 +695,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3994886 # number of writebacks -system.cpu0.dcache.writebacks::total 3994886 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 471328 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 471328 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1040644 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1040644 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 61 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 61 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43748 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43748 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 50 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 50 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1511972 # 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number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 74583001500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1907396500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1907396500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4514361000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4514361000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5031000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5031000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 85306731000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 85306731000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103835408500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 103835408500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2448224000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2448224000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2535196500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2535196500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4983420500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4983420500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036778 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036778 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018991 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018991 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.730812 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.730812 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.862509 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.862509 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064132 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064132 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098322 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098322 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028453 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028453 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032504 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032504 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16015.338365 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16015.338365 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 23321.922158 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 23321.922158 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26671.288533 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26671.288533 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 94425.715856 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 94425.715856 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14798.064316 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14798.064316 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22867.944886 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22867.944886 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5190079 # number of writebacks +system.cpu0.dcache.writebacks::total 5190079 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 389569 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 389569 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 893829 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 893829 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 64 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 64 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40085 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 40085 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 63 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 63 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1283398 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1283398 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1283398 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1283398 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2814567 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2814567 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1278110 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1278110 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 581694 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 581694 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 728810 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 728810 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 110465 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 110465 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 178505 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 178505 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4092677 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4092677 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4674371 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4674371 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16748 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16748 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18251 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18251 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34999 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34999 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40095557000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40095557000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32063318500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 32063318500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14032843000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14032843000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 66427837000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 66427837000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1488538500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1488538500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4826102000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4826102000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4518500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4518500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 72158875500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 72158875500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 86191718500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 86191718500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3021431000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3021431000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3257996500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3257996500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6279427500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6279427500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036066 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036066 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018819 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018819 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.698876 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.698876 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.842987 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.842987 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060055 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060055 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097129 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097129 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028040 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028040 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031844 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031844 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14245.728384 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14245.728384 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25086.509377 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25086.509377 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24124.097893 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.097893 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 91145.616827 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 91145.616827 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13475.204816 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13475.204816 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27036.228677 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27036.228677 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18297.962780 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18297.962780 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19383.871864 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19383.871864 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166693.266154 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166693.266154 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162898.959070 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162898.959070 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 164741.173554 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 164741.173554 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17631.216805 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17631.216805 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18439.212142 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18439.212142 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180405.481251 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180405.481251 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178510.574763 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 178510.574763 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179417.340495 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179417.340495 # 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Cycle average of tags in use +system.cpu0.icache.tags.total_refs 215729294 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 8911968 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.206695 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40343615000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890744 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999787 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 515987824 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 515987824 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 243455405 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 243455405 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 243455405 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 243455405 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 243455405 # number of overall hits -system.cpu0.icache.overall_hits::total 243455405 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9692338 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9692338 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9692338 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9692338 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9692338 # number of overall misses -system.cpu0.icache.overall_misses::total 9692338 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 102847685000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 102847685000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 102847685000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 102847685000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 102847685000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 102847685000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 253147743 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 253147743 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 253147743 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 253147743 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 253147743 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 253147743 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038287 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.038287 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038287 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.038287 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038287 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.038287 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10611.235906 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10611.235906 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10611.235906 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10611.235906 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10611.235906 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10611.235906 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 458194521 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 458194521 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 215729294 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 215729294 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 215729294 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 215729294 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10111.235906 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10111.235906 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141723.240743 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141723.240743 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 88026353500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 88026353500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88026353500 # 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mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.039672 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039672 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.039672 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9877.308214 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9877.308214 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9877.308214 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7930582 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7930908 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 287 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7009428 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7009488 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 54 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1050332 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2927796 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16250.045097 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 27328553 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2943246 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.285175 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 38485430000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6649.492221 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 85.492855 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 83.778044 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4952.378154 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3516.424447 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 962.479377 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.405853 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005218 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005113 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.302269 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.214626 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.058745 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.991824 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1206 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 86 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14158 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 762 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 258 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 60 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4796 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6589 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2552 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.073608 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005249 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.864136 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 526684633 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 526684633 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 557343 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 169839 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 727182 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3994885 # 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number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4938499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4938499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 19118794000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 19118794000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 30594179000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 30594179000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 46332518496 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 46332518496 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 71985941000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 71985941000 # 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number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 569957 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 178629 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 748586 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3994886 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3994886 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 245729 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 245729 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 197402 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 197402 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # 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miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.028593 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.552649 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.552649 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.816952 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.816952 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.prefetcher.pfSpanPage 921168 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2475518 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16200.233462 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 22065601 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2491662 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 8.855776 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 9049945000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15248.600129 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 44.173698 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 44.219033 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 863.240603 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.930701 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002696 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002699 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.052688 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.988784 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1264 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14832 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 796 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 176 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 279 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 32 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # 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number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 178501 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 178501 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1043542 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1043542 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 8911977 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 8911977 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3506424 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 3506424 # 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number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6008334000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 13004489000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027689 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.552649 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.552649 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.816952 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.816952 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999527 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999527 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.215996 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.215996 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.084825 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.266802 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.266802 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.750042 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.750042 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022130 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049197 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.254979 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.139080 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022130 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049197 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.254979 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.239772 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.239772 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.074243 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.256623 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.256623 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772261 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772261 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252758 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.129745 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252758 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187852 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44339.119667 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 70126.299396 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35057.911511 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35057.911511 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18692.313416 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18692.313416 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 571562.375000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 571562.375000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60685.103586 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60685.103586 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31211.654222 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36995.024259 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36995.024259 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 115692.637341 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 115692.637341 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41665.193013 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37753.359129 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41665.193013 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46158.314401 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158689.861783 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139196.474416 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155397.770353 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155397.770353 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 156996.148760 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 142250.542037 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.178601 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26106.536022 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41102.047113 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30802.220271 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30802.220271 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19512.736623 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19512.736623 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1031874.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1031874.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55487.890257 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.890257 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31490.545606 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30754.680317 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30754.680317 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108194.184996 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108194.184996 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36135.828071 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34358.895348 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36135.828071 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36203.474366 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172394.345594 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143119.676499 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171008.355707 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171008.355707 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171671.590617 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 148949.569341 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 32152230 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16420555 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 569005 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 568969 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 36 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 939547 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14756064 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15563 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15563 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 5525670 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 13869690 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1023479 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 455350 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 356742 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 509038 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1302016 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1231079 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9692338 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5147566 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 792720 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 788675 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29179671 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19139148 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 387023 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1234112 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 49939954 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 623657344 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 598500446 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1429032 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4559656 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1228146478 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6651761 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 39123003 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.023394 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.151159 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 29004574 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14815953 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2223 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1990994 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1990568 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 426 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 781840 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 13286786 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 18251 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 18251 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4847792 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 10690718 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2645908 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 891756 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 444613 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 320296 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 480335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 85 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1119465 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1052013 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 8911978 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4503059 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 735449 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 726880 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 26838850 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16809682 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 328338 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1022103 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 44998973 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1143972032 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 629474552 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1241512 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3859768 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1778547864 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6630650 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 21811897 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.104823 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.306390 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 38207781 97.66% 97.66% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 915186 2.34% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 36 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 19525925 89.52% 89.52% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2285546 10.48% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 426 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 39123003 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 20385491499 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 189810874 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 21811897 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 28866629481 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 172367004 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14619906616 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 13449935466 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8517245437 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7428549534 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 208413461 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 173196405 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 664225858 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 539756748 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 135994038 # Number of BP lookups -system.cpu1.branchPred.condPredicted 97681271 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5923294 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 101767942 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 74881085 # Number of BTB hits +system.cpu1.branchPred.lookups 127068265 # Number of BP lookups +system.cpu1.branchPred.condPredicted 89752795 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6099791 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 94409743 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 68319168 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.580229 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 15572056 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1048784 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.364531 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15069899 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 999135 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1383,62 +1380,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 278179 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 278179 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9856 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80934 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 278179 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 278179 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 278179 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 90790 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 21983.114880 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 19433.562361 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 21494.492882 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 89574 98.66% 98.66% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 162 0.18% 98.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 899 0.99% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.02% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 47 0.05% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 21 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 36 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 16 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 90790 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1613488760 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1613488760 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1613488760 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 80934 89.14% 89.14% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9856 10.86% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 90790 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 278179 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 271482 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 271482 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7964 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78105 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 271482 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 271482 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 271482 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 86069 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22755.010515 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21243.396519 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15660.005020 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 85331 99.14% 99.14% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 168 0.20% 99.34% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 495 0.58% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 14 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 20 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 22 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 86069 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 527505760 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 527505760 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 527505760 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 78105 90.75% 90.75% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 7964 9.25% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 86069 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 271482 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 278179 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90790 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 271482 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86069 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90790 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 368969 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86069 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 357551 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 86408994 # DTB read hits -system.cpu1.dtb.read_misses 229031 # DTB read misses -system.cpu1.dtb.write_hits 76265809 # DTB write hits -system.cpu1.dtb.write_misses 49148 # DTB write misses +system.cpu1.dtb.read_hits 82675138 # DTB read hits +system.cpu1.dtb.read_misses 225741 # DTB read misses +system.cpu1.dtb.write_hits 73180273 # DTB write hits +system.cpu1.dtb.write_misses 45741 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36480 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1565 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7972 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 37272 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1666 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8268 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11612 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 86638025 # DTB read accesses -system.cpu1.dtb.write_accesses 76314957 # DTB write accesses +system.cpu1.dtb.perms_faults 11369 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 82900879 # DTB read accesses +system.cpu1.dtb.write_accesses 73226014 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 162674803 # DTB hits -system.cpu1.dtb.misses 278179 # DTB misses -system.cpu1.dtb.accesses 162952982 # DTB accesses +system.cpu1.dtb.hits 155855411 # DTB hits +system.cpu1.dtb.misses 271482 # DTB misses +system.cpu1.dtb.accesses 156126893 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1468,189 +1465,186 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 61280 # Table walker walks requested -system.cpu1.itb.walker.walksLong 61280 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 546 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52744 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 61280 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 61280 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 61280 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 53290 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25110.649278 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21594.032296 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 25562.060343 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 52075 97.72% 97.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 7 0.01% 97.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1075 2.02% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 37 0.07% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 53 0.10% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 27 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 12 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 69604 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69604 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 666 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61994 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 69604 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69604 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69604 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 62660 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25321.249601 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23483.555874 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17582.582178 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 61881 98.76% 98.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 12 0.02% 98.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 712 1.14% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 23 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 53290 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1612594260 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1612594260 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1612594260 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 52744 98.98% 98.98% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 546 1.02% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 53290 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 62660 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 526611260 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 526611260 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 526611260 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61994 98.94% 98.94% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 666 1.06% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 62660 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61280 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61280 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69604 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69604 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53290 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53290 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 114570 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 242169117 # ITB inst hits -system.cpu1.itb.inst_misses 61280 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62660 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62660 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 132264 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 226404999 # ITB inst hits +system.cpu1.itb.inst_misses 69604 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25722 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26762 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 205735 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 203402 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 242230397 # ITB inst accesses -system.cpu1.itb.hits 242169117 # DTB hits -system.cpu1.itb.misses 61280 # DTB misses -system.cpu1.itb.accesses 242230397 # DTB accesses -system.cpu1.numCycles 953928196 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 226474603 # ITB inst accesses +system.cpu1.itb.hits 226404999 # DTB hits +system.cpu1.itb.misses 69604 # DTB misses +system.cpu1.itb.accesses 226474603 # DTB accesses +system.cpu1.numCycles 896249910 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 443058406 # Number of instructions committed -system.cpu1.committedOps 521637964 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 48259182 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4720 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 94194636881 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.153053 # CPI: cycles per instruction -system.cpu1.ipc 0.464457 # IPC: instructions per cycle +system.cpu1.committedInsts 420934522 # Number of instructions committed +system.cpu1.committedOps 495850522 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 42911431 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4588 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93867828238 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.129191 # CPI: cycles per instruction +system.cpu1.ipc 0.469662 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13665 # number of quiesce instructions executed -system.cpu1.tickCycles 720990302 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 232937894 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5271409 # number of replacements -system.cpu1.dcache.tags.tagsinuse 430.049497 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 154587010 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5271921 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.322710 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8389845325000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.049497 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.839940 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.839940 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 13511 # number of quiesce instructions executed +system.cpu1.tickCycles 680922299 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 215327611 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 4921419 # number of replacements +system.cpu1.dcache.tags.tagsinuse 458.899025 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 148299852 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4921931 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.130421 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8388824602000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.899025 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.896287 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.896287 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 327906694 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 327906694 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 79069141 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 79069141 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 70951579 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 70951579 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 254478 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 254478 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 200049 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 200049 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1835496 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1835496 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1797284 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1797284 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 150020720 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 150020720 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 150275198 # number of overall hits -system.cpu1.dcache.overall_hits::total 150275198 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3348164 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3348164 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2321727 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2321727 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 675333 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 675333 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 453842 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 453842 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 163069 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 163069 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199393 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 199393 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5669891 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5669891 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6345224 # number of overall misses -system.cpu1.dcache.overall_misses::total 6345224 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55281073500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 55281073500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 48428743000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 48428743000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20617335000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 20617335000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2629405000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2629405000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4686368500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4686368500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4186500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4186500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 103709816500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 103709816500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 103709816500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 103709816500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82417305 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82417305 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 73273306 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 73273306 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 929811 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 929811 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 653891 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 653891 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1998565 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1998565 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1996677 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1996677 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 155690611 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 155690611 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 156620422 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 156620422 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040625 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.040625 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031686 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.031686 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.726312 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.726312 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.694064 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.694064 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081593 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081593 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099862 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099862 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036418 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.036418 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040513 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040513 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16510.861923 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16510.861923 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20858.930873 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20858.930873 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45428.442057 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45428.442057 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16124.493313 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16124.493313 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23503.174635 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23503.174635 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 313981831 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 313981831 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 76035057 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 76035057 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68321160 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 68321160 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 232478 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 232478 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 184182 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 184182 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1549703 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1549703 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1524262 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1524262 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 144356217 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 144356217 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 144588695 # number of overall hits +system.cpu1.dcache.overall_hits::total 144588695 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3124160 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3124160 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2104338 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2104338 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 561771 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 561771 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 510720 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 510720 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 156544 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 156544 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 180437 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 180437 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5228498 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5228498 # 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number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5104015500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 7589000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 7589000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 92781043500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 92781043500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 92781043500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 92781043500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 79159217 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 79159217 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 70425498 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 70425498 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 794249 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 794249 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 694902 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 694902 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1706247 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1706247 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1704699 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1704699 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 149584715 # 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average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18291.324560 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16344.547726 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16344.547726 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17745.257529 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17745.257529 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16023.615397 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16023.615397 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1659,161 +1653,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # 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average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 4921438 # number of writebacks +system.cpu1.dcache.writebacks::total 4921438 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 336855 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 336855 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 865157 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 865157 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 99 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 99 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39963 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39963 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 44 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 44 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 65275568000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 77920489000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 77920489000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3868216000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3868216000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3618681000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3618681000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7486897000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7486897000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035211 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035211 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017596 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017596 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.706717 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.706717 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.734810 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.734810 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068326 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068326 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105821 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105821 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026918 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026918 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030508 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030508 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13935.147930 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13935.147930 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21331.880089 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21331.880089 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22527.557905 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22527.557905 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36784.885463 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36784.885463 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13457.381563 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13457.381563 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27277.139357 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27277.139357 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16632.938178 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16632.938178 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17622.766981 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17622.766981 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172421.456509 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172421.456509 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174340.986810 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174340.986810 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173360.270640 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173360.270640 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16211.547240 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16211.547240 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16984.300519 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16984.300519 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185064.395752 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185064.395752 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187379.919221 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187379.919221 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186176.381360 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186176.381360 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 9020173 # number of replacements -system.cpu1.icache.tags.tagsinuse 506.865133 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 232936753 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9020685 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.822513 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8389731746000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.865133 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989971 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.989971 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 9409188 # number of replacements +system.cpu1.icache.tags.tagsinuse 506.684863 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 216784534 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9409700 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 23.038411 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8388652871500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.684863 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989619 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.989619 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 492935590 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 492935590 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 232936753 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 232936753 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 232936753 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 232936753 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 232936753 # number of overall hits -system.cpu1.icache.overall_hits::total 232936753 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 9020695 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 9020695 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 9020695 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 9020695 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 9020695 # number of overall misses -system.cpu1.icache.overall_misses::total 9020695 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 95573427500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 95573427500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 95573427500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 95573427500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 95573427500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 95573427500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 241957448 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 241957448 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 241957448 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 241957448 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 241957448 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 241957448 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037282 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.037282 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037282 # 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Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 216784534 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 216784534 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 216784534 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 216784534 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 216784534 # number of overall hits +system.cpu1.icache.overall_hits::total 216784534 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 9409700 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 9409700 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 9409700 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 9409700 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 9409700 # number of overall misses +system.cpu1.icache.overall_misses::total 9409700 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 95979801000 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10200.091501 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1822,257 +1816,254 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9020695 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9020695 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9020695 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 9020695 # 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average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10094.907377 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10094.907377 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10094.907377 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10094.907377 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136086.956522 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136086.956522 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91274951000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 91274951000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91274951000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 91274951000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91274951000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 91274951000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12950500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12950500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12950500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 12950500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.041600 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.041600 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.041600 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9700.091501 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9700.091501 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9700.091501 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7367099 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7368207 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6599308 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6600409 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 970 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 915185 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2451047 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13486.856931 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 25401363 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2467204 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 10.295607 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9750772511500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5534.671535 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 72.865878 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 75.759865 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3715.594887 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3131.532678 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 956.432088 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.337810 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004447 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004624 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.226782 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.191134 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.058376 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.823172 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1547 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14551 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 27 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 141 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 670 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 709 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1114 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2381 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4908 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6029 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.094421 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.888123 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 480485557 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 480485557 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 478608 # 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number of overall hits -system.cpu1.l2cache.overall_hits::total 12507900 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12194 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8418 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 20612 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 132767 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 132767 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 161216 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 161216 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # 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number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3766406500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3914500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3914500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 14165693998 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 14165693998 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 28461637500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 28461637500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 38316841993 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 38316841993 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18196585000 # 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number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 82003704991 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 490802 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149472 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 640274 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3447608 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3447608 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 209600 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 209600 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199324 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 199324 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1149880 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1149880 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9020695 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 9020695 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3765589 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3765589 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 452056 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 452056 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 490802 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149472 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 9020695 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4915469 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 14576438 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 490802 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149472 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 9020695 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4915469 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 14576438 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024845 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.056318 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.032192 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.633430 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.633430 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.808814 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.808814 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 793623 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2151198 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13377.061252 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 23203065 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2166951 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 10.707702 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9986150274500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 12523.259690 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.377906 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 74.184237 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 713.239419 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.764359 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004051 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004528 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 46 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1249 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4750 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8044 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 438 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.060120 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006653 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.894714 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 482635734 # 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number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3473788500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12214500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7174681000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7186895500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025312 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.633430 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.633430 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.808814 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.808814 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999031 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999031 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.208501 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.208501 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087133 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087133 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.268660 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.268660 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.595440 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.595440 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024845 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.056312 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087133 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.254587 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.141188 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024845 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.056312 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087133 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.254587 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226292 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226292 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073464 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248519 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248519 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.523368 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.523368 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243392 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.123409 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243392 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191657 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 45405.487361 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62763.794851 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 33876.592015 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 33876.592015 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18404.479084 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18404.479084 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3584500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3584500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47001.856084 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47001.856084 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30210.657025 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31801.599439 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31801.599439 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 61599.092773 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 61599.092773 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34713.726625 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33100.996437 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34713.726625 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40912.032789 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164418.990732 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164277.441348 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166840.276236 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166840.276236 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 165603.205978 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 165528.386551 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.169835 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30203.043311 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36118.703029 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32496.215800 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32496.215800 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19755.934430 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19755.934430 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1303599.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1303599.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 40767.089256 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 40767.089256 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29425.314202 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29525.390105 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29525.390105 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55213.942832 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55213.942832 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31936.723887 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30957.803939 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31936.723887 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32368.597869 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177059.252703 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176865.151948 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179877.200704 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179877.200704 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178412.518029 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178308.328785 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 29416501 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15028447 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2391 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 554511 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 554502 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 9 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 803941 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13684916 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 22517 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 22517 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 4553047 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 13043260 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 982334 # Transaction distribution +system.cpu1.toL2Bus.snoop_filter.tot_requests 29428527 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15006964 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2768 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1972954 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1972589 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 365 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 814249 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13775310 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 19312 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 19312 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4142105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 11232116 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2703238 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 874176 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 414162 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 358438 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 473685 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1229561 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1158646 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9020695 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4893253 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 460729 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 452056 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27060072 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17084009 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332493 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1088108 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 45564682 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 577330304 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 542008212 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1195776 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3926416 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1124460708 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6177589 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 35784390 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.024790 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.155485 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeReq 401941 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 322763 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 444037 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1114947 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1047219 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9409700 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4456605 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 514166 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 508289 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28226960 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15947748 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 397923 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1113211 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 45685842 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1204298752 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 609360975 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1520224 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4222808 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1819402759 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6269077 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 21677519 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.104647 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.306153 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 34897315 97.52% 97.52% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 887066 2.48% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 9 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 19409393 89.54% 89.54% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2267761 10.46% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 365 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 35784390 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 18416469994 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 187934075 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 21677519 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 29325134974 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 172530424 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13533732383 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 14118247362 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7841048470 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7236066136 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 183047447 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 207955878 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 597345920 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 585496227 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40341 # Transaction distribution -system.iobus.trans_dist::ReadResp 40341 # Transaction distribution -system.iobus.trans_dist::WriteReq 136603 # Transaction distribution -system.iobus.trans_dist::WriteResp 136603 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47670 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40404 # Transaction distribution +system.iobus.trans_dist::ReadResp 40404 # Transaction distribution +system.iobus.trans_dist::WriteReq 136972 # Transaction distribution +system.iobus.trans_dist::WriteResp 136972 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47770 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2327,18 +2310,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122552 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231760 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231760 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47690 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354752 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47790 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2348,797 +2331,798 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155927 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355392 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36193000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513405 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47202500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25874502 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 168500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 36406501 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 123500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 566159223 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 566812397 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92680000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92927000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147952000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148200000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115609 # number of replacements -system.iocache.tags.tagsinuse 11.261931 # Cycle average of tags in use -system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115625 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9146785142000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.823570 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.438361 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.238973 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.464898 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.703871 # Average percentage of cache occupancy +system.iocache.tags.replacements 115872 # number of replacements +system.iocache.tags.tagsinuse 11.264501 # Cycle average of tags in use +system.iocache.tags.total_refs 6 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115888 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000052 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 9145998133000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.414921 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.849581 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463433 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.240599 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.704031 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041009 # Number of tag accesses -system.iocache.tags.data_accesses 1041009 # Number of data accesses +system.iocache.tags.tag_accesses 1043272 # Number of tag accesses +system.iocache.tags.data_accesses 1043272 # Number of data accesses +system.iocache.WriteLineReq_hits::realview.ide 2 # number of WriteLineReq hits +system.iocache.WriteLineReq_hits::total 2 # number of WriteLineReq hits system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8900 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8937 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8896 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8933 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106982 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106982 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8900 # number of demand (read+write) misses -system.iocache.demand_misses::total 8940 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8896 # number of demand (read+write) misses +system.iocache.demand_misses::total 8936 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8900 # number of overall misses -system.iocache.overall_misses::total 8940 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1696302972 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1701497972 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8896 # number of overall misses +system.iocache.overall_misses::total 8936 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5261000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1700094991 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1705355991 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13913628251 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13913628251 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1696302972 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1701866972 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1696302972 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1701866972 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 14013428406 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 14013428406 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5630000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1700094991 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1705724991 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5630000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1700094991 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1705724991 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8900 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8937 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8896 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8933 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8900 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8940 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8896 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8936 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8900 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8940 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8896 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8936 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 0.999981 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 0.999981 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 190595.839551 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190388.046548 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142189.189189 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 191107.800247 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 190905.182022 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130365.304803 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130365.304803 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 190595.839551 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 190365.433110 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 190595.839551 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 190365.433110 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34247 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130988.656092 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130988.656092 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 140750 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 191107.800247 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 190882.384848 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 140750 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 191107.800247 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 190882.384848 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 36149 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3593 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3721 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.531589 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.714862 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106948 # number of writebacks +system.iocache.writebacks::total 106948 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8900 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8937 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8896 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8933 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106982 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106982 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8900 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8940 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8896 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8936 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8900 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8940 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1251302972 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1254647972 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8896 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8936 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3411000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1255294991 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1258705991 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8577228251 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8577228251 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1251302972 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1254866972 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1251302972 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1254866972 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8664328406 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8664328406 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3630000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1255294991 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1258924991 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3630000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1255294991 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1258924991 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999981 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.999981 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140595.839551 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 140388.046548 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92189.189189 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141107.800247 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 140905.182022 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80365.304803 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80365.304803 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 140595.839551 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 140365.433110 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 140595.839551 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 140365.433110 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80988.656092 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80988.656092 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90750 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 141107.800247 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 140882.384848 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90750 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 141107.800247 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 140882.384848 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1566664 # number of replacements -system.l2c.tags.tagsinuse 63931.901156 # Cycle average of tags in use -system.l2c.tags.total_refs 6426547 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1627093 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.949711 # Average number of references to valid blocks. +system.l2c.tags.replacements 1047057 # number of replacements +system.l2c.tags.tagsinuse 63052.180525 # Cycle average of tags in use +system.l2c.tags.total_refs 6067910 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1106756 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.482609 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17340.299819 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 183.189406 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 209.040410 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5130.513561 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 11368.638005 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11382.688685 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 175.831777 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 202.455245 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3752.541531 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4974.040380 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9212.662336 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.264592 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002795 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003190 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.078285 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.173472 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.173686 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002683 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003089 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.057259 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.075898 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.140574 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.975523 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9887 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 204 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50338 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 102 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 389 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9395 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 202 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1895 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5328 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 42935 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.150864 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.768097 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 77438610 # Number of tag accesses -system.l2c.tags.data_accesses 77438610 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2557006 # number of Writeback hits -system.l2c.Writeback_hits::total 2557006 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 27501 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 32544 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 60045 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6218 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5959 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12177 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 161499 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 176783 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 338282 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6423 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4133 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 754192 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 613728 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 292319 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6682 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4427 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 728293 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 606746 # 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.102569 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.085400 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.080939 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002114 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003153 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.082688 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.101497 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.110294 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.962100 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 9310 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 176 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50213 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 61 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 427 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 684 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1579 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 6559 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 158 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2614 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 11152 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 36045 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.142059 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.002686 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.766190 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 72230268 # Number of tag accesses +system.l2c.tags.data_accesses 72230268 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 2478146 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2478146 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 154381 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 128604 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 282985 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 37860 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 40612 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 129626.836307 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 142108.606976 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124676.223818 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 134230.283373 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125219.539809 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 129626.836307 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 142108.606976 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 140688.023422 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146431.271259 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 126000.342133 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138396.453126 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149839.721100 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145162.946429 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139509.057851 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148098.366531 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 131670.738530 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.283558 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.311704 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.296629 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.222890 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.219180 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.220975 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.735273 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.389634 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.622169 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.103583 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.142888 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.085730 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.143630 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.313127 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.124332 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.165497 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.068977 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.127885 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.262921 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.152296 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.103583 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.142888 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.085730 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.435394 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.313127 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.124332 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.165497 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068977 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.214194 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.262921 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.250397 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.103583 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.142888 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.085730 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.435394 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.313127 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.124332 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.165497 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068977 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.214194 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.262921 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.250397 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73405.101388 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73447.407332 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73425.747080 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76522.838199 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76478.421053 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76500.089851 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129078.519295 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124079.362956 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 128054.050765 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122985.737708 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126097.370539 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123319.428715 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 126467.494956 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 136875.285945 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122985.737708 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 128580.058033 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123319.428715 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125035.044479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 132299.122166 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122985.737708 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 128580.058033 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123319.428715 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125035.044479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 132299.122166 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154383.299498 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159070.933014 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131241.202012 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153993.698975 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162871.815452 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158558.142321 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154180.133718 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160896.324480 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 139282.030687 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 90608 # Transaction distribution -system.membus.trans_dist::ReadResp 1019089 # Transaction distribution -system.membus.trans_dist::WriteReq 38080 # Transaction distribution -system.membus.trans_dist::WriteResp 38080 # Transaction distribution -system.membus.trans_dist::Writeback 1301925 # Transaction distribution -system.membus.trans_dist::CleanEvict 271570 # Transaction distribution -system.membus.trans_dist::UpgradeReq 429176 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 310200 # Transaction distribution -system.membus.trans_dist::UpgradeResp 115027 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 674063 # Transaction distribution -system.membus.trans_dist::ReadExResp 652544 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 928481 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122552 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 90049 # Transaction distribution +system.membus.trans_dist::ReadResp 640443 # Transaction distribution +system.membus.trans_dist::WriteReq 37563 # Transaction distribution +system.membus.trans_dist::WriteResp 37563 # Transaction distribution +system.membus.trans_dist::WritebackDirty 930050 # Transaction distribution +system.membus.trans_dist::CleanEvict 190296 # Transaction distribution +system.membus.trans_dist::UpgradeReq 413026 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 280293 # Transaction distribution +system.membus.trans_dist::UpgradeResp 150977 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 593740 # Transaction distribution +system.membus.trans_dist::ReadExResp 574320 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 550394 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106981 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106981 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24802 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5589312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5736718 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342877 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342877 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6079595 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155682 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 22290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4211327 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4356581 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 343179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4699760 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155927 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49604 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 180435584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 180642194 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7274816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7274816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 187917010 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 648574 # Total snoops (count) -system.membus.snoop_fanout::samples 4152999 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 44580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 127415488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 127617319 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7277312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7277312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 134894631 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 564682 # Total snoops (count) +system.membus.snoop_fanout::samples 3194785 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4152999 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3194785 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4152999 # Request fanout histogram -system.membus.reqLayer0.occupancy 109607499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3194785 # Request fanout histogram +system.membus.reqLayer0.occupancy 109901497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20503498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 18632000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9125026082 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6680198838 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8873044520 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6549107858 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 230408874 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229362666 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3149,11 +3133,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -3192,52 +3176,52 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 12411375 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6308416 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2241470 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 182770 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 168316 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 14454 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 90610 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5207811 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38080 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38080 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3858986 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1729776 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 481704 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 322377 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 804081 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1151274 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1151274 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 5124442 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9065091 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7602046 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16667137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 281816078 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 221579908 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 503395986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3440017 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 14338060 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.337750 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.475069 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 11369480 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6166084 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1983565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 99756 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 89163 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 10593 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 90051 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4379282 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 37563 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 37563 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3408225 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1479469 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 686639 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 358765 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1045403 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1072017 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1072017 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4296486 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106981 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8273345 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7109938 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15383283 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 249443752 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200422911 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 449866663 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2689125 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7811601 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.375584 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.487066 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9509841 66.33% 66.33% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4813765 33.57% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 14454 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4888281 62.58% 62.58% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2912727 37.29% 99.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 10593 0.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 14338060 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9248164097 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7811601 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8585712934 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2627637 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2584443 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5363594791 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4648327252 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4586237114 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4065319209 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |