diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual')
4 files changed, 2765 insertions, 2765 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini index f4750f909..30060be32 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini @@ -12,14 +12,15 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false @@ -28,7 +29,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -43,7 +44,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +87,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -188,7 +189,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -649,7 +649,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=1 is_read_only=true max_miss_count=0 @@ -762,7 +761,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_excl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=12 is_read_only=false max_miss_count=0 @@ -822,6 +820,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 @@ -933,7 +932,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -1394,7 +1392,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=1 is_read_only=true max_miss_count=0 @@ -1507,7 +1504,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_excl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=12 is_read_only=false max_miss_count=0 @@ -1567,6 +1563,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 @@ -1629,7 +1626,6 @@ clk_domain=system.clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 @@ -1666,7 +1662,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -1701,6 +1696,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -2590,6 +2586,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout index 207c42573..9920acce4 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 12:36:35 -gem5 executing on e104799-lin, pid 5221 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual +gem5 compiled Mar 15 2016 21:26:42 +gem5 started Mar 15 2016 21:34:31 +gem5 executing on phenom, pid 15970 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47381683294000 because m5_exit instruction encountered +Exiting @ tick 47454492026000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 83d2eea36..cfb87def9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.496138 # Number of seconds simulated -sim_ticks 47496138032000 # Number of ticks simulated -final_tick 47496138032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.454492 # Number of seconds simulated +sim_ticks 47454492026000 # Number of ticks simulated +final_tick 47454492026000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 287392 # Simulator instruction rate (inst/s) -host_op_rate 338020 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15163142641 # Simulator tick rate (ticks/s) -host_mem_usage 759192 # Number of bytes of host memory used -host_seconds 3132.34 # Real time elapsed on the host -sim_insts 900209792 # Number of instructions simulated -sim_ops 1058792792 # Number of ops (including micro ops) simulated +host_inst_rate 169815 # Simulator instruction rate (inst/s) +host_op_rate 199687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8468561033 # Simulator tick rate (ticks/s) +host_mem_usage 764912 # Number of bytes of host memory used +host_seconds 5603.61 # Real time elapsed on the host +sim_insts 951575519 # Number of instructions simulated +sim_ops 1118968402 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 123968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 99904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7981184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13323912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 15275072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 135168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 122048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3081152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10821968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12736320 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 446656 # Number of bytes read from this memory -system.physmem.bytes_read::total 64147352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7981184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3081152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11062336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 76613760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 233088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 210624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7916672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 17537736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 18153728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 166400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 132160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3894272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12497872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 21171968 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 432064 # Number of bytes read from this memory +system.physmem.bytes_read::total 82346584 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7916672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3894272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11810944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 92922304 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 76634344 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1937 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1561 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 124706 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 208199 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 238673 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 48143 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 169106 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 199005 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6979 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1002328 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1197090 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 92942888 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3642 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 123698 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 274040 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 283652 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 60848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 195292 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 330812 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6751 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1286691 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1451911 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1199664 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 168039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 280526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 321607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 227849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 268155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9404 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1350580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 168039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64872 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 232910 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1613052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1454485 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4912 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 166827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 369570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 382550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 82063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 263365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 446153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1735275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 166827 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 82063 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248890 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1958135 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1613486 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1613052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 168039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 280960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 321607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 227850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 268155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2964066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1002328 # Number of read requests accepted -system.physmem.writeReqs 1199664 # Number of write requests accepted -system.physmem.readBursts 1002328 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1199664 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 64118976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 30016 # Total number of bytes read from write queue -system.physmem.bytesWritten 76632896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 64147352 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 76634344 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 469 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1958569 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1958135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4912 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 166827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 370003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 382550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 82063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 263365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 446153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3693844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1286691 # Number of read requests accepted +system.physmem.writeReqs 1454485 # Number of write requests accepted +system.physmem.readBursts 1286691 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1454485 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 82317440 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 30784 # Total number of bytes read from write queue +system.physmem.bytesWritten 92941888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 82346584 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 92942888 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 481 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 52312 # Per bank write bursts -system.physmem.perBankRdBursts::1 66235 # Per bank write bursts -system.physmem.perBankRdBursts::2 59334 # Per bank write bursts -system.physmem.perBankRdBursts::3 65978 # Per bank write bursts -system.physmem.perBankRdBursts::4 61446 # Per bank write bursts -system.physmem.perBankRdBursts::5 69476 # Per bank write bursts -system.physmem.perBankRdBursts::6 59128 # Per bank write bursts -system.physmem.perBankRdBursts::7 60480 # Per bank write bursts -system.physmem.perBankRdBursts::8 57677 # Per bank write bursts -system.physmem.perBankRdBursts::9 110303 # Per bank write bursts -system.physmem.perBankRdBursts::10 51521 # Per bank write bursts -system.physmem.perBankRdBursts::11 60498 # Per bank write bursts -system.physmem.perBankRdBursts::12 54125 # Per bank write bursts -system.physmem.perBankRdBursts::13 57278 # Per bank write bursts -system.physmem.perBankRdBursts::14 58648 # Per bank write bursts -system.physmem.perBankRdBursts::15 57420 # Per bank write bursts -system.physmem.perBankWrBursts::0 71344 # Per bank write bursts -system.physmem.perBankWrBursts::1 78863 # Per bank write bursts -system.physmem.perBankWrBursts::2 73221 # Per bank write bursts -system.physmem.perBankWrBursts::3 79189 # Per bank write bursts -system.physmem.perBankWrBursts::4 75543 # Per bank write bursts -system.physmem.perBankWrBursts::5 82829 # Per bank write bursts -system.physmem.perBankWrBursts::6 74512 # Per bank write bursts -system.physmem.perBankWrBursts::7 77237 # Per bank write bursts -system.physmem.perBankWrBursts::8 71961 # Per bank write bursts -system.physmem.perBankWrBursts::9 73593 # Per bank write bursts -system.physmem.perBankWrBursts::10 69363 # Per bank write bursts -system.physmem.perBankWrBursts::11 76682 # Per bank write bursts -system.physmem.perBankWrBursts::12 71227 # Per bank write bursts -system.physmem.perBankWrBursts::13 74509 # Per bank write bursts -system.physmem.perBankWrBursts::14 73049 # Per bank write bursts -system.physmem.perBankWrBursts::15 74267 # Per bank write bursts +system.physmem.perBankRdBursts::0 68545 # Per bank write bursts +system.physmem.perBankRdBursts::1 77862 # Per bank write bursts +system.physmem.perBankRdBursts::2 76461 # Per bank write bursts +system.physmem.perBankRdBursts::3 81936 # Per bank write bursts +system.physmem.perBankRdBursts::4 74664 # Per bank write bursts +system.physmem.perBankRdBursts::5 81822 # Per bank write bursts +system.physmem.perBankRdBursts::6 81067 # Per bank write bursts +system.physmem.perBankRdBursts::7 83827 # Per bank write bursts +system.physmem.perBankRdBursts::8 73756 # Per bank write bursts +system.physmem.perBankRdBursts::9 133954 # Per bank write bursts +system.physmem.perBankRdBursts::10 75964 # Per bank write bursts +system.physmem.perBankRdBursts::11 77586 # Per bank write bursts +system.physmem.perBankRdBursts::12 69247 # Per bank write bursts +system.physmem.perBankRdBursts::13 78127 # Per bank write bursts +system.physmem.perBankRdBursts::14 73347 # Per bank write bursts +system.physmem.perBankRdBursts::15 78045 # Per bank write bursts +system.physmem.perBankWrBursts::0 83788 # Per bank write bursts +system.physmem.perBankWrBursts::1 90226 # Per bank write bursts +system.physmem.perBankWrBursts::2 90168 # Per bank write bursts +system.physmem.perBankWrBursts::3 95983 # Per bank write bursts +system.physmem.perBankWrBursts::4 89513 # Per bank write bursts +system.physmem.perBankWrBursts::5 93413 # Per bank write bursts +system.physmem.perBankWrBursts::6 92742 # Per bank write bursts +system.physmem.perBankWrBursts::7 93553 # Per bank write bursts +system.physmem.perBankWrBursts::8 87937 # Per bank write bursts +system.physmem.perBankWrBursts::9 94416 # Per bank write bursts +system.physmem.perBankWrBursts::10 91588 # Per bank write bursts +system.physmem.perBankWrBursts::11 94818 # Per bank write bursts +system.physmem.perBankWrBursts::12 85405 # Per bank write bursts +system.physmem.perBankWrBursts::13 92349 # Per bank write bursts +system.physmem.perBankWrBursts::14 86484 # Per bank write bursts +system.physmem.perBankWrBursts::15 89834 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 57 # Number of times write queue was full causing retry -system.physmem.totGap 47496135919500 # Total gap between requests +system.physmem.numWrRetry 36 # Number of times write queue was full causing retry +system.physmem.totGap 47454489913500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1002298 # Read request sizes (log2) +system.physmem.readPktSize::6 1286661 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1197090 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 675393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 29137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 27086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 24475 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 22026 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1451911 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 827173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 164897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 63225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 47515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 40751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 37481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 5741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2483 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1354 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 527 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,168 +188,167 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 38080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 51935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 55190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 65836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 70016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 72724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 73495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 74816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 77871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 75261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 76182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 84001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 74766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 69103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 66691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 34612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 41901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 58265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 63048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 69768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 73771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 78937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 85048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 89045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 90562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 92833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 96249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 94408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 95986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 105469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 93952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 86808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 83066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 153 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 167 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 993836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.624332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 96.550200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 190.035765 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 676204 68.04% 68.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 192250 19.34% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44807 4.51% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21137 2.13% 94.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15251 1.53% 95.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9933 1.00% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5714 0.57% 97.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4523 0.46% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24017 2.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 993836 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 62276 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.086984 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 158.174793 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 62273 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::58 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 99 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1224605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 143.114986 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 97.246112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 190.672457 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 830563 67.82% 67.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 233051 19.03% 86.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 57759 4.72% 91.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27718 2.26% 93.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20623 1.68% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13112 1.07% 96.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7173 0.59% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5754 0.47% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 28852 2.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1224605 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 77530 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.589449 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 141.842916 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 77527 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 62276 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 62276 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.227134 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.463029 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.016188 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49891 80.11% 80.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 5512 8.85% 88.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 3034 4.87% 93.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1650 2.65% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 463 0.74% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 302 0.48% 97.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 265 0.43% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 82 0.13% 98.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 283 0.45% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 77 0.12% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 32 0.05% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 49 0.08% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 248 0.40% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 39 0.06% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 31 0.05% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 106 0.17% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 143 0.23% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 12 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 11 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 77530 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 77530 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.731033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.088703 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.268543 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 64617 83.34% 83.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 6035 7.78% 91.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 3056 3.94% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1620 2.09% 97.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 474 0.61% 97.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 277 0.36% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 269 0.35% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 83 0.11% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 290 0.37% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 69 0.09% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 30 0.04% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 52 0.07% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 249 0.32% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 33 0.04% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 40 0.05% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 110 0.14% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 167 0.22% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 62276 # Writes before turning the bus around for reads -system.physmem.totQLat 32552700191 # Total ticks spent queuing -system.physmem.totMemAccLat 51337556441 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5009295000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32492.30 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 77530 # Writes before turning the bus around for reads +system.physmem.totQLat 47048753044 # Total ticks spent queuing +system.physmem.totMemAccLat 71165190544 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6431050000 # Total ticks spent in databus transfers +system.physmem.avgQLat 36579.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51242.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.35 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.61 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.35 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.61 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 55329.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.74 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.96 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.36 # Average write queue length when enqueuing -system.physmem.readRowHits 748874 # Number of row buffer hits during reads -system.physmem.writeRowHits 456536 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.75 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.13 # Row buffer hit rate for writes -system.physmem.avgGap 21569622.38 # Average gap between requests -system.physmem.pageHitRate 54.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3877765920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2115844500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3856171800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3970542240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3102216508560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1199773763640 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27445246701750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31761057298410 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.708277 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45657180846254 # Time in different power states -system.physmem_0.memoryStateTime::REF 1586000260000 # Time in different power states +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.33 # Average write queue length when enqueuing +system.physmem.readRowHits 962295 # Number of row buffer hits during reads +system.physmem.writeRowHits 551527 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 37.98 # Row buffer hit rate for writes +system.physmem.avgGap 17311726.76 # Average gap between requests +system.physmem.pageHitRate 55.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4656869280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2540950500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4884235200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4726421280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1219171959180 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27403246221750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31738723386870 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.824424 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45587152483743 # Time in different power states +system.physmem_0.memoryStateTime::REF 1584609520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 252951953746 # Time in different power states +system.physmem_0.memoryStateTime::ACT 282729931257 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3635634240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1983729000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3958266000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3788538480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3102216508560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1194664304160 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27449728675500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31759975655940 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.685504 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45664625089280 # Time in different power states -system.physmem_1.memoryStateTime::REF 1586000260000 # Time in different power states +system.physmem_1.actEnergy 4601144520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2510545125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5148202800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4683944880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1221460881390 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27401238395250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31739139843645 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.833200 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45583769039323 # Time in different power states +system.physmem_1.memoryStateTime::REF 1584609520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 245507696970 # Time in different power states +system.physmem_1.memoryStateTime::ACT 286113375677 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -383,15 +382,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 138061860 # Number of BP lookups -system.cpu0.branchPred.condPredicted 98120507 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6229967 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 103103324 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75422199 # Number of BTB hits +system.cpu0.branchPred.lookups 147959066 # Number of BP lookups +system.cpu0.branchPred.condPredicted 105493690 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6448516 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 111296242 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 81329533 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.152054 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16055942 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1103312 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.074824 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17161750 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1109253 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -422,62 +421,64 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 287097 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 287097 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9253 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79328 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 287097 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 287097 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 287097 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 88581 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23354.082704 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21377.049680 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 19303.806083 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 87487 98.76% 98.76% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 212 0.24% 99.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 756 0.85% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 31 0.03% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 29 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 88581 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 300034 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 300034 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11904 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91094 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 300034 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 300034 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 300034 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 102998 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 24703.863182 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21663.255890 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 26203.116698 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 100872 97.94% 97.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 180 0.17% 98.11% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1639 1.59% 99.70% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 73 0.07% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 76 0.07% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 46 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 69 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 28 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 102998 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 79328 89.55% 89.55% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9253 10.45% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 88581 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 287097 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 91094 88.44% 88.44% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11904 11.56% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 102998 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 300034 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 287097 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 88581 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 300034 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 102998 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 88581 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 375678 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 102998 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 403032 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 87655759 # DTB read hits -system.cpu0.dtb.read_misses 237615 # DTB read misses -system.cpu0.dtb.write_hits 78096829 # DTB write hits -system.cpu0.dtb.write_misses 49482 # DTB write misses -system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 94891169 # DTB read hits +system.cpu0.dtb.read_misses 247198 # DTB read misses +system.cpu0.dtb.write_hits 84318368 # DTB write hits +system.cpu0.dtb.write_misses 52836 # DTB write misses +system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36184 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2196 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9698 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 40307 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1747 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9392 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11726 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 87893374 # DTB read accesses -system.cpu0.dtb.write_accesses 78146311 # DTB write accesses +system.cpu0.dtb.perms_faults 12141 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 95138367 # DTB read accesses +system.cpu0.dtb.write_accesses 84371204 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 165752588 # DTB hits -system.cpu0.dtb.misses 287097 # DTB misses -system.cpu0.dtb.accesses 166039685 # DTB accesses +system.cpu0.dtb.hits 179209537 # DTB hits +system.cpu0.dtb.misses 300034 # DTB misses +system.cpu0.dtb.accesses 179509571 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,187 +508,187 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 66101 # Table walker walks requested -system.cpu0.itb.walker.walksLong 66101 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 650 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56681 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 66101 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 66101 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 66101 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 57331 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26460.544906 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23886.492389 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 21943.926110 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 56305 98.21% 98.21% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 11 0.02% 98.23% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 903 1.58% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 44 0.08% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 42 0.07% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 57331 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 71231 # Table walker walks requested +system.cpu0.itb.walker.walksLong 71231 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 667 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60897 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 71231 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 71231 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 71231 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 61564 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 29116.975830 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24576.932577 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 30900.488305 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 59287 96.30% 96.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 14 0.02% 96.32% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 2011 3.27% 99.59% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 94 0.15% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 85 0.14% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 46 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 61564 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 56681 98.87% 98.87% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 650 1.13% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 57331 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 60897 98.92% 98.92% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 667 1.08% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 61564 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66101 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66101 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 71231 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 71231 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57331 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57331 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 123432 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 246672238 # ITB inst hits -system.cpu0.itb.inst_misses 66101 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61564 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61564 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 132795 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 264582301 # ITB inst hits +system.cpu0.itb.inst_misses 71231 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25870 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 28772 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 211969 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 223649 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 246738339 # ITB inst accesses -system.cpu0.itb.hits 246672238 # DTB hits -system.cpu0.itb.misses 66101 # DTB misses -system.cpu0.itb.accesses 246738339 # DTB accesses -system.cpu0.numCycles 1042581150 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 264653532 # ITB inst accesses +system.cpu0.itb.hits 264582301 # DTB hits +system.cpu0.itb.misses 71231 # DTB misses +system.cpu0.itb.accesses 264653532 # DTB accesses +system.cpu0.numCycles 1106984671 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 455270721 # Number of instructions committed -system.cpu0.committedOps 534899361 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 47095692 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4288 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93950410811 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.290025 # CPI: cycles per instruction -system.cpu0.ipc 0.436677 # IPC: instructions per cycle +system.cpu0.committedInsts 488099503 # Number of instructions committed +system.cpu0.committedOps 574418730 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 50785821 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 5453 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93802885102 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.267949 # CPI: cycles per instruction +system.cpu0.ipc 0.440927 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13221 # number of quiesce instructions executed -system.cpu0.tickCycles 736979138 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 305602012 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5679788 # number of replacements -system.cpu0.dcache.tags.tagsinuse 503.382728 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 157129733 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5680300 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.662224 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 5643 # number of quiesce instructions executed +system.cpu0.tickCycles 789747765 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 317236906 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 6140209 # number of replacements +system.cpu0.dcache.tags.tagsinuse 501.783411 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 169967706 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6140721 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.678787 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.382728 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983169 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.983169 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.783411 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980046 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.980046 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 439 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 334387337 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 334387337 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 80268736 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80268736 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72233903 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72233903 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 277349 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 277349 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 251788 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 251788 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1785654 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1785654 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1744754 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1744754 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 152502639 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 152502639 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 152779988 # number of overall hits -system.cpu0.dcache.overall_hits::total 152779988 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3412741 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3412741 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2489296 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2489296 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 686937 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 686937 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 801634 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 801634 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 154902 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 154902 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194385 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 194385 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5902037 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5902037 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6588974 # number of overall misses -system.cpu0.dcache.overall_misses::total 6588974 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 58848858500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 58848858500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 63605542500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 63605542500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 48599001500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 48599001500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2502004000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2502004000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5451875000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5451875000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 6380500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 6380500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 122454401000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 122454401000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 122454401000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 122454401000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83681477 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83681477 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74723199 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74723199 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 964286 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 964286 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1053422 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1053422 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1940556 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1940556 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1939139 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1939139 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 158404676 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 158404676 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 159368962 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 159368962 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040783 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.040783 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033314 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033314 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.712379 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.712379 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760981 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760981 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079824 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079824 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100243 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100243 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037259 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.037259 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041344 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.041344 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17243.868931 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17243.868931 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25551.618811 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25551.618811 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60624.925465 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60624.925465 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16152.173632 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16152.173632 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28046.788590 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28046.788590 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 361643482 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 361643482 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 86800691 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86800691 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 78258675 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 78258675 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268918 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 268918 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 127943 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 127943 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1971519 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1971519 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1943002 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1943002 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 165059366 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 165059366 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 165328284 # number of overall hits +system.cpu0.dcache.overall_hits::total 165328284 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3776237 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3776237 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2642039 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2642039 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 748095 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 748095 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 774634 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 774634 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 182353 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 182353 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 209431 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 209431 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 6418276 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6418276 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 7166371 # number of overall misses +system.cpu0.dcache.overall_misses::total 7166371 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 71342778500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 71342778500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67996340500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 67996340500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46419090000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 46419090000 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3111811500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3111811500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5902963500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5902963500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7077000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7077000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 139339119000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 139339119000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 139339119000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 139339119000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 90576928 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 90576928 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 80900714 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 80900714 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1017013 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1017013 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 902577 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 902577 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2153872 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2153872 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2152433 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2152433 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 171477642 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 171477642 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 172494655 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 172494655 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041691 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.041691 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032658 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.032658 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.735581 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.735581 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.858247 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.858247 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084663 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084663 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097300 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097300 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037429 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.037429 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041545 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.041545 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18892.558518 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 18892.558518 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25736.312182 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25736.312182 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59923.899545 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59923.899545 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17064.767237 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17064.767237 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28185.719879 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28185.719879 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20747.819948 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20747.819948 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18584.744909 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18584.744909 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21709.742460 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 21709.742460 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19443.469924 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19443.469924 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,161 +697,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 5679821 # number of writebacks -system.cpu0.dcache.writebacks::total 5679821 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 423726 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 423726 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1038452 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1038452 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 85 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 85 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41327 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41327 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 43 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1462178 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1462178 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1462178 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1462178 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2989015 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2989015 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1450844 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1450844 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 685285 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 685285 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801549 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 801549 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113575 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113575 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194342 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 194342 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4439859 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4439859 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5125144 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5125144 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32143 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32143 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31553 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31553 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 63696 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 63696 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46000579500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 46000579500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36719986000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36719986000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17989395000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17989395000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 47789065000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 47789065000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1631247500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1631247500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5254690500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5254690500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 6005000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 6005000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 82720565500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 82720565500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 100709960500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 100709960500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6124425500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6124425500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5931269500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5931269500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12055695000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12055695000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035719 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035719 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019416 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019416 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.710666 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.710666 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760900 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760900 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058527 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058527 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100221 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100221 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028029 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028029 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032159 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032159 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15389.879107 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15389.879107 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25309.396462 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25309.396462 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26250.968575 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26250.968575 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59620.890301 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59620.890301 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14362.733876 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14362.733876 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27038.367929 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.367929 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 6140232 # number of writebacks +system.cpu0.dcache.writebacks::total 6140232 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 470815 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 470815 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1099674 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1099674 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 78 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 78 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45572 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45572 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 53 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1570489 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1570489 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1570489 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1570489 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3305422 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3305422 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1542365 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1542365 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 746538 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 746538 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 774556 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 774556 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 136781 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136781 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 209378 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 209378 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4847787 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4847787 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5594325 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5594325 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15086 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15086 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15976 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15976 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31062 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31062 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56024435500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56024435500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39191815000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 39191815000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 20208395000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 20208395000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45637665000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45637665000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2043982500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2043982500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5689319500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5689319500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 6788500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 6788500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95216250500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 95216250500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115424645500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 115424645500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2640339000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2640339000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2747173500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2747173500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5387512500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5387512500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036493 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036493 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019065 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019065 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.734050 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.734050 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.858161 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.858161 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063505 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063505 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097275 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097275 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028271 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028271 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032432 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032432 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16949.253530 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16949.253530 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25410.207701 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25410.207701 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27069.479384 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27069.479384 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58921.065746 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58921.065746 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14943.468026 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14943.468026 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27172.479917 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27172.479917 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18631.349667 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18631.349667 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19650.171878 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19650.171878 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190536.835392 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190536.835392 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187977.989415 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187977.989415 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189269.263376 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189269.263376 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19641.178645 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19641.178645 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20632.452619 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20632.452619 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175019.156834 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 175019.156834 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171956.278167 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171956.278167 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 173443.838130 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173443.838130 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 9549530 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.897064 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 236903550 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9550042 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.806545 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 9845680 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.897003 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 254505668 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9846192 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 25.848132 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 33055106000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897064 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897003 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999799 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 502457255 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 502457255 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 236903550 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 236903550 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 236903550 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 236903550 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 236903550 # number of overall hits -system.cpu0.icache.overall_hits::total 236903550 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9550052 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9550052 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9550052 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9550052 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9550052 # number of overall misses -system.cpu0.icache.overall_misses::total 9550052 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 101421985500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 101421985500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 101421985500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 101421985500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 101421985500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 101421985500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 246453602 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 246453602 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 246453602 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 246453602 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 246453602 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 246453602 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038750 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.038750 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038750 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.038750 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038750 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.038750 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10620.045367 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10620.045367 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10620.045367 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10620.045367 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10620.045367 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10620.045367 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 538549912 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 538549912 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 254505668 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 254505668 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 254505668 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 254505668 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 254505668 # number of overall hits +system.cpu0.icache.overall_hits::total 254505668 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9846192 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9846192 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9846192 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9846192 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9846192 # number of overall misses +system.cpu0.icache.overall_misses::total 9846192 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 104168962000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 104168962000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 104168962000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 104168962000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 104168962000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 104168962000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 264351860 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 264351860 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 264351860 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 264351860 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 264351860 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 264351860 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037247 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.037247 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037247 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.037247 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037247 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.037247 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10579.619207 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10579.619207 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10579.619207 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10579.619207 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10579.619207 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10579.619207 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -859,260 +860,258 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 9549530 # number of writebacks -system.cpu0.icache.writebacks::total 9549530 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9550052 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9550052 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9550052 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9550052 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9550052 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9550052 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 9845680 # number of writebacks +system.cpu0.icache.writebacks::total 9845680 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9846192 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9846192 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9846192 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9846192 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9846192 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9846192 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 96646960000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 96646960000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 96646960000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 96646960000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 96646960000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 96646960000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 99245866000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 99245866000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 99245866000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 99245866000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 99245866000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 99245866000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038750 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038750 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038750 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.038750 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038750 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.038750 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10120.045420 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10120.045420 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10120.045420 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10120.045420 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10120.045420 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10120.045420 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037247 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.037247 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.037247 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10079.619207 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10079.619207 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10079.619207 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7772165 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7773534 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 1208 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8550248 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8550537 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 256 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 991570 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2865211 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16182.470551 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 23591597 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2881428 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 8.187467 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1111887 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 3055162 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16188.315469 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 24712613 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 3070855 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 8.047470 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 8707838500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15283.265421 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 60.779936 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 54.474522 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 783.950672 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.932816 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003710 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003325 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.047849 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.987700 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1265 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14897 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 535 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 649 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 58 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 45 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1135 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5291 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7937 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 458 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.077209 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.909241 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 513878817 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 513878817 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 534301 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 171000 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 705301 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3781367 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3781367 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 11445215 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 11445215 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 428 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 428 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 897370 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 897370 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8796749 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 8796749 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2760570 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2760570 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 203097 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 203097 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 534301 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 171000 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 8796749 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3657940 # 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number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1026998 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 596103 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 596103 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12394 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8896 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 753302 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1325987 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2100579 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12394 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8896 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 753302 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1325987 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2100579 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 543058500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 406297500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 949356000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3394715000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 3394715000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1886445500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1886445500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 5898999 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 5898999 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 19173654497 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 19173654497 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 29218782500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 29218782500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 41703375488 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 41703375488 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 451954500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 451954500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 543058500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 406297500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 29218782500 # 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number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3781369 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 3781369 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 11445216 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 11445216 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 263478 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 263478 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194335 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 194335 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 849 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 47 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 34 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 880 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5451 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7600 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.067139 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # 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miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses +system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.996808 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.996808 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999986 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999986 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.249916 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.249916 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.078879 # 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number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 25048433000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 25048433000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 44909041489 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 44909041489 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 39596476000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 39596476000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 722944500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 599881000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 25048433000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 62260992489 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 88632250989 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 722944500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 599881000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 25048433000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 62260992489 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 54995868600 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 143628119589 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5867073000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 12863228000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5694540000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5694540000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2519460500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9515615500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2627296000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2627296000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11561613000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 18557768000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022671 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049440 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029298 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses -system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses -system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses -system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5146756500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12142911500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.031104 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998376 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998376 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996808 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996808 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999986 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999986 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.241743 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.241743 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.078878 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078878 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270773 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270773 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.745871 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.745871 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022671 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049440 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078878 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263805 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.136913 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022671 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049440 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078878 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263805 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236376 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236376 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078301 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270406 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270406 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.746562 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.746562 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.138559 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.189379 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38593.949643 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59689.287295 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59689.287295 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29753.284535 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29753.284535 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19514.559909 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19514.559909 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 782714.142857 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 782714.142857 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55350.794047 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55350.794047 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32787.400786 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 34527.480263 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34527.480263 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69680.907566 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69680.907566 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39107.955826 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36823.924881 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39107.955826 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59689.287295 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43158.674848 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.053996 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61741.289726 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29925.451776 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29925.451776 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19653.868363 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19653.868363 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 557499.727273 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 557499.727273 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57548.640546 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57548.640546 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32489.756980 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39651.911728 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39651.911728 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68676.397845 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 68676.397845 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39758.098096 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46034.137306 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182530.348754 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152314.071899 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 180475.390613 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 180475.390613 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167006.529232 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141191.713035 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164452.679019 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164452.679019 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181512.386963 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159973.863196 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165693.017191 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145649.104605 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 31336515 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16003499 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2764 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2238925 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2238443 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 482 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 888197 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14329408 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31554 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31553 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5463883 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 11447979 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 3030252 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1046563 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 472775 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352055 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 529438 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1230630 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1206068 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9550052 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4850843 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 854414 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 799200 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28754250 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18474160 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 377323 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1153011 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 48758744 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1225720896 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 689935275 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1439168 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4373560 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1921468899 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7541383 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 23989921 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.106643 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.308724 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 32897508 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16815136 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2403341 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2402836 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 505 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 933618 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 15066373 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 15977 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 15976 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5804347 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 11960956 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 3276888 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1153420 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 478642 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 376774 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 550943 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1307095 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1283776 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9846192 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5335526 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 825564 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 772295 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29642681 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19817496 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 405752 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1239273 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 51105202 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1263627520 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 749575419 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1544024 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4686408 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 2019433371 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 8071773 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 25329179 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.108588 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.311185 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 21432051 89.34% 89.34% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2557388 10.66% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 482 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 22579246 89.14% 89.14% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2749428 10.85% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 505 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 23989921 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 31215182485 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 25329179 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 32745453976 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 206081920 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 192728655 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14406948660 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14851397186 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8156637515 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8851946898 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 197502349 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 212824349 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 606443243 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 653582276 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 134798362 # Number of BP lookups -system.cpu1.branchPred.condPredicted 95816419 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6051956 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 100961028 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 73848042 # Number of BTB hits +system.cpu1.branchPred.lookups 143060728 # Number of BP lookups +system.cpu1.branchPred.condPredicted 103431257 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6108949 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 108043566 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 80039888 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.145097 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 15861028 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1023147 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 74.081124 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15973583 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1078136 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1391,63 +1385,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 282723 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 282723 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10766 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86594 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 282723 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 282723 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 282723 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 97360 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23363.804437 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21328.911362 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 20585.456118 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 96095 98.70% 98.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 182 0.19% 98.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 912 0.94% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 29 0.03% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 49 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 15 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 316205 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 316205 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13111 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 102055 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 316205 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 316205 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 316205 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 115166 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23006.933470 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21361.362420 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 17841.956140 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 114056 99.04% 99.04% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 145 0.13% 99.16% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 815 0.71% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 40 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 32 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 97360 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 115166 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1788277352 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1788277352 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1788277352 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 86594 88.94% 88.94% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10766 11.06% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 97360 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 282723 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 102056 88.62% 88.62% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 13111 11.38% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 115167 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 316205 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 282723 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97360 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 316205 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 115167 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97360 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 380083 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 115167 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 431372 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 88221750 # DTB read hits -system.cpu1.dtb.read_misses 234611 # DTB read misses -system.cpu1.dtb.write_hits 76459163 # DTB write hits -system.cpu1.dtb.write_misses 48112 # DTB write misses -system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 90416501 # DTB read hits +system.cpu1.dtb.read_misses 263668 # DTB read misses +system.cpu1.dtb.write_hits 78865175 # DTB write hits +system.cpu1.dtb.write_misses 52537 # DTB write misses +system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 39871 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1240 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8073 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 39779 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1900 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9673 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11018 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 88456361 # DTB read accesses -system.cpu1.dtb.write_accesses 76507275 # DTB write accesses +system.cpu1.dtb.perms_faults 11862 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 90680169 # DTB read accesses +system.cpu1.dtb.write_accesses 78917712 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 164680913 # DTB hits -system.cpu1.dtb.misses 282723 # DTB misses -system.cpu1.dtb.accesses 164963636 # DTB accesses +system.cpu1.dtb.hits 169281676 # DTB hits +system.cpu1.dtb.misses 316205 # DTB misses +system.cpu1.dtb.accesses 169597881 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1477,188 +1471,187 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 64693 # Table walker walks requested -system.cpu1.itb.walker.walksLong 64693 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 526 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55247 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 64693 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 64693 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 64693 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 55773 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26679.495455 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23706.173761 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 24561.580376 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 54531 97.77% 97.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 9 0.02% 97.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1101 1.97% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 35 0.06% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 52 0.09% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 31 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 61623 # Table walker walks requested +system.cpu1.itb.walker.walksLong 61623 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 682 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 51951 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 61623 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 61623 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 61623 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 52633 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26809.463644 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23734.871548 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 24762.364644 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 51446 97.74% 97.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 9 0.02% 97.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1035 1.97% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 54 0.10% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 44 0.08% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 33 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 55773 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 52633 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1787261852 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1787261852 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1787261852 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 55247 99.06% 99.06% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 526 0.94% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55773 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 51951 98.70% 98.70% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 682 1.30% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 52633 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64693 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64693 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61623 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61623 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55773 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55773 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 120466 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 241355329 # ITB inst hits -system.cpu1.itb.inst_misses 64693 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 52633 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 52633 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 114256 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 255703249 # ITB inst hits +system.cpu1.itb.inst_misses 61623 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 28782 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 28254 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 214506 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 225386 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 241420022 # ITB inst accesses -system.cpu1.itb.hits 241355329 # DTB hits -system.cpu1.itb.misses 64693 # DTB misses -system.cpu1.itb.accesses 241420022 # DTB accesses -system.cpu1.numCycles 943222184 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 255764872 # ITB inst accesses +system.cpu1.itb.hits 255703249 # DTB hits +system.cpu1.itb.misses 61623 # DTB misses +system.cpu1.itb.accesses 255764872 # DTB accesses +system.cpu1.numCycles 1013399126 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 444939071 # Number of instructions committed -system.cpu1.committedOps 523893431 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 46484386 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5697 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 94049904755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.119891 # CPI: cycles per instruction -system.cpu1.ipc 0.471722 # IPC: instructions per cycle +system.cpu1.committedInsts 463476016 # Number of instructions committed +system.cpu1.committedOps 544549672 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 51973590 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4681 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93896343891 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.186519 # CPI: cycles per instruction +system.cpu1.ipc 0.457348 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5760 # number of quiesce instructions executed -system.cpu1.tickCycles 722277565 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 220944619 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5315264 # number of replacements -system.cpu1.dcache.tags.tagsinuse 430.485039 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 156623393 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5315774 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.463892 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8391021559000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.485039 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.840791 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.840791 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 332053228 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 332053228 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 80890555 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 80890555 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 71395384 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 71395384 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 230003 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 230003 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 70856 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 70856 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1784180 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1784180 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1762697 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1762697 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 152285939 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 152285939 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 152515942 # number of overall hits -system.cpu1.dcache.overall_hits::total 152515942 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3470383 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3470383 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2256465 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2256465 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 629037 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 629037 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 454847 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 454847 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 178965 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 178965 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 198846 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 198846 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5726848 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5726848 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6355885 # number of overall misses -system.cpu1.dcache.overall_misses::total 6355885 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 57691506500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 57691506500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 50161466000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 50161466000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17158564500 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 17158564500 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2980004000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2980004000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5546868500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5546868500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5779500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5779500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 107852972500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 107852972500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 107852972500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 107852972500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 84360938 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 84360938 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 73651849 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 73651849 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 859040 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 859040 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 525703 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 525703 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1963145 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1963145 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1961543 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1961543 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 158012787 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 158012787 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 158871827 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 158871827 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041137 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.041137 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030637 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030637 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.732256 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.732256 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.865217 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.865217 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091162 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091162 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101372 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101372 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036243 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.036243 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040006 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040006 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16623.959517 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16623.959517 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22230.110372 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22230.110372 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37723.815921 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37723.815921 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16651.322884 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16651.322884 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27895.298372 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27895.298372 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 13591 # number of quiesce instructions executed +system.cpu1.tickCycles 759435347 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 253963779 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5640902 # number of replacements +system.cpu1.dcache.tags.tagsinuse 433.747661 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 160682361 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5641413 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.482645 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8381463375500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 433.747661 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.847163 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.847163 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 341448433 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 341448433 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 82699161 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 82699161 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 73240702 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 73240702 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 257576 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 257576 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 197387 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 197387 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1901357 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1901357 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1855769 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1855769 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 155939863 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 155939863 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 156197439 # number of overall hits +system.cpu1.dcache.overall_hits::total 156197439 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3585243 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3585243 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2523734 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2523734 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 738365 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 738365 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 486988 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 486988 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162310 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 162310 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 206438 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 206438 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 6108977 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 6108977 # 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number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5741911000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 7112000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 7112000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 119194321000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 119194321000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 119194321000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 119194321000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 86284404 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 86284404 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 75764436 # 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number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 162048840 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 163044781 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 163044781 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041551 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.041551 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033310 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.033310 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.741374 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.741374 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.711581 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.711581 # 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average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 23244.765692 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45191.877418 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45191.877418 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16871.702298 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16871.702298 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27814.215406 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27814.215406 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18832.868010 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18832.868010 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16968.993696 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16968.993696 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19511.338969 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19511.338969 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17407.385377 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17407.385377 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1667,161 +1660,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1855767000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036489 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036489 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018139 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018139 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.731903 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.731903 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.865103 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.865103 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068448 # 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average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5640935 # number of writebacks +system.cpu1.dcache.writebacks::total 5640935 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 429416 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 429416 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1043359 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1043359 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42170 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42170 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 72 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 72 # 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number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 486914 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120140 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120140 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 206366 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 206366 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4636202 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4636202 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5374284 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5374284 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23242 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23242 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22236 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22236 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 45478 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 45478 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 47412877500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 47412877500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 34746994000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 34746994000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 19660408500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 19660408500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 21514132500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 21514132500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1774236500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1774236500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5529988500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5529988500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6729000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6729000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82159871500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 82159871500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101820280000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 101820280000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4292810500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4292810500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4172773000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4172773000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8465583500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8465583500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036575 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036575 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019539 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019539 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.741090 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.741090 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.711473 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.711473 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058217 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058217 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100070 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100070 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028610 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028610 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032962 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032962 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.915284 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15023.915284 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23471.751414 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23471.751414 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 26637.160234 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 26637.160234 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44184.666081 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44184.666081 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14768.074746 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14768.074746 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26796.994175 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26796.994175 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17245.647975 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17245.647975 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18053.396003 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18053.396003 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 124694.324766 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 124694.324766 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 141134.337684 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 141134.337684 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 133192.205555 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 133192.205555 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17721.374414 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17721.374414 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18945.831668 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18945.831668 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184700.563635 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184700.563635 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187658.436769 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187658.436769 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186146.785259 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186146.785259 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 9419212 # number of replacements -system.cpu1.icache.tags.tagsinuse 506.776997 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 231714815 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9419724 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 24.598896 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8379179578000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.776997 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989799 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.989799 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 9253909 # number of replacements +system.cpu1.icache.tags.tagsinuse 506.772073 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 246217857 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9254421 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 26.605431 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8381293063000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.772073 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989789 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.989789 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 491688802 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 491688802 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 231714815 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 231714815 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 231714815 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 231714815 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10569.994463 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1830,498 +1823,498 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 9419212 # number of writebacks -system.cpu1.icache.writebacks::total 9419212 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9419724 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9419724 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9419724 # 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number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91472670500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 91472670500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91472670500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 91472670500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91472670500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 91472670500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 93192079500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 93192079500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 93192079500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 93192079500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 93192079500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 93192079500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13081000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13081000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13081000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 13081000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039064 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039064 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039064 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.039064 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039064 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.039064 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9710.759094 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9710.759094 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9710.759094 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9710.759094 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9710.759094 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9710.759094 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.036225 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.036225 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.036225 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10069.994517 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10069.994517 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10069.994517 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140655.913978 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140655.913978 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7256046 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7256259 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 183 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7972481 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7973767 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 1132 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 925773 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2304751 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13454.881705 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 23669466 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2320587 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 10.199775 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9853632359500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12618.151234 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.761915 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 57.964405 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 717.004151 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.770151 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003770 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003538 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.043762 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.821221 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1043 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 71 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14722 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 319 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 650 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 71 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5507 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8143 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 659 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.063660 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.898560 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 496871809 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 496871809 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 551874 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 166024 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 717898 # 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number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11967 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8433 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 20400 # number of ReadReq misses -system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses -system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 222957 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 222957 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 198797 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 198797 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 249481 # 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number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1915512500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5381000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5381000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13948272999 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 13948272999 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24574911500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24574911500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 38337752989 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 38337752989 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 401272000 # 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number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 77846048988 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 563841 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 174457 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 738298 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3295377 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3295377 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 11437109 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 11437109 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 223524 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 223524 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 198797 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 198797 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1114614 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1114614 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9419724 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 9419724 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3841058 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3841058 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 29 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1053 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5404 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7290 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 973 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076965 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903809 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 504035480 # 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number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 9254432 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5253677 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 15305764 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020577 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050749 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.026836 # miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses +system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996768 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996768 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # 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average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 51787.797937 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 48289.779412 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15020.438919 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15020.438919 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9635.520154 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9635.520154 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1076200 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1076200 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 55909.159411 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 55909.159411 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 50509233988 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 74956946988 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 566505000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 415038000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 23466170000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 50509233988 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 64551953809 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 139508900797 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12337000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 785396000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 797733000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 962364500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 962364500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 4106803500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 4119140500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 4005950500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 4005950500 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12337000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1747760500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1760097500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021224 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048333 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027630 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses -system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 8112754000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 8125091000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026835 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997463 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997463 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996768 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996768 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.217724 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.217724 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.072919 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.072919 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.251698 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251698 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.578401 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.578401 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021224 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048333 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.072919 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.244056 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.126821 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021224 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048333 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.072919 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.244056 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207689 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207689 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081006 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.269659 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.269659 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.654937 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.654937 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255033 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.137917 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255033 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174889 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42291.337811 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53304.865332 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53304.865332 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31396.571949 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31396.571949 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19362.414921 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19362.414921 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 998200 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 998200 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47276.636115 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47276.636115 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29777.775756 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29777.775756 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33589.328536 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33589.328536 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 49894.194371 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 49894.194371 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29777.775756 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36335.678304 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34048.993127 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29777.775756 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36335.678304 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53304.865332 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 39341.423766 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.195584 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 45855.781359 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 73136.413477 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 73136.413477 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30690.875696 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30690.875696 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19278.434926 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19278.434926 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 681611 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 681611 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 52889.128769 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 52889.128769 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31302.166565 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34082.743167 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34082.743167 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55618.562661 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55618.562661 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 37697.368599 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35508.934910 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 37697.368599 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 73136.413477 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 46603.070327 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116683.405140 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 116901.084408 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133624.618162 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 133624.618162 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176697.508820 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176521.984144 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 180156.075733 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 180156.075733 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 125440.357425 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 125488.200485 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178388.539514 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178295.209673 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 30305906 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15477606 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2013 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 2090955 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2090626 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 329 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 826390 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 14176907 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 7202 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7202 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4434109 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 11439122 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2886028 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 940232 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 438079 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353355 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 486110 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1143505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1120857 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9419724 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4894979 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 500608 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 453070 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28258846 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17165188 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 367696 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1190168 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 46981898 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1205697856 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 663528133 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1395656 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4510728 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1875132373 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6705692 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 22548909 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.107052 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.309227 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 30687781 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15695228 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2622 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 2305562 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2305078 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 484 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 905031 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 14265709 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 22236 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 22236 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4974934 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 11314728 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 3212624 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1143576 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 456570 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 371810 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 515155 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 96 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1270102 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1247161 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9254432 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5086529 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 540215 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 484636 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27762958 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18273152 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 349398 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1329953 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 47715461 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1184539712 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 703787179 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1323840 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 5057400 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1894708131 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 7537959 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 23658040 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.112405 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.315929 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 20135326 89.30% 89.30% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2413254 10.70% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 329 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 20999234 88.76% 88.76% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2658322 11.24% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 484 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 22548909 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 30147553476 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 23658040 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 30538190977 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 176219861 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 182787124 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 14133264904 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13885672200 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7885730738 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8385983653 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 193298381 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 183975884 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 626482687 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 697921212 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40387 # Transaction distribution -system.iobus.trans_dist::ReadResp 40387 # Transaction distribution +system.iobus.trans_dist::ReadReq 40434 # Transaction distribution +system.iobus.trans_dist::ReadResp 40434 # Transaction distribution system.iobus.trans_dist::WriteReq 136979 # Transaction distribution system.iobus.trans_dist::WriteResp 136979 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47874 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2334,13 +2327,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231694 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231694 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122964 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231782 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231782 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354732 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354826 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47894 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2353,101 +2346,101 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155996 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355128 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156002 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355480 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513210 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47188500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47273505 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26264003 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26273501 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36399000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36398000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568799211 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568842992 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92966000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92972000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148134000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148222000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115828 # number of replacements -system.iocache.tags.tagsinuse 11.305227 # Cycle average of tags in use +system.iocache.tags.replacements 115872 # number of replacements +system.iocache.tags.tagsinuse 11.252872 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115844 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115888 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9138950806000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.834041 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.471186 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239628 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466949 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706577 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9138217056000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.833219 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.419652 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239576 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.463728 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.703304 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042980 # Number of tag accesses -system.iocache.tags.data_accesses 1042980 # Number of data accesses +system.iocache.tags.tag_accesses 1043376 # Number of tag accesses +system.iocache.tags.data_accesses 1043376 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8863 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8900 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8907 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8944 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8863 # number of demand (read+write) misses -system.iocache.demand_misses::total 8903 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8907 # number of demand (read+write) misses +system.iocache.demand_misses::total 8947 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8863 # number of overall misses -system.iocache.overall_misses::total 8903 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5197000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1710789963 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1715986963 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8907 # number of overall misses +system.iocache.overall_misses::total 8947 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5277000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1705079977 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1710356977 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13562248248 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13562248248 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5566000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1710789963 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1716355963 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5566000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1710789963 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1716355963 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13558851015 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13558851015 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5646000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1705079977 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1710725977 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5646000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1705079977 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1710725977 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8863 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8900 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8944 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8863 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8903 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8907 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8947 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8863 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8903 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8907 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8947 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2461,55 +2454,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 193026.059235 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 192807.523933 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142621.621622 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 191431.455821 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 191229.536784 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126768.939729 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126768.939729 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139150 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 193026.059235 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 192784.001236 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139150 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 193026.059235 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 192784.001236 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 35587 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126737.185140 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126737.185140 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 141150 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 191431.455821 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 191206.658880 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 141150 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 191431.455821 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 191206.658880 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 35119 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3530 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3508 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.081303 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.011117 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106950 # number of writebacks system.iocache.writebacks::total 106950 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8863 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8900 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8907 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8944 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8863 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8903 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8907 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8947 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8863 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8903 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3347000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1267639963 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1270986963 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8907 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8947 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3427000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1259729977 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1263156977 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8206832286 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8206832286 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3566000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1267639963 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1271205963 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3566000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1267639963 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1271205963 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8203408528 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8203408528 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3646000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1259729977 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1263375977 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3646000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1259729977 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1263375977 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2523,645 +2516,654 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143026.059235 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 142807.523933 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92621.621622 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141431.455821 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 141229.536784 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76710.837938 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76710.837938 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89150 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 143026.059235 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 142784.001236 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89150 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 143026.059235 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 142784.001236 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76678.835415 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76678.835415 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 91150 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 141431.455821 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 141206.658880 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 91150 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 141431.455821 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 141206.658880 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1399797 # number of replacements -system.l2c.tags.tagsinuse 63464.709741 # Cycle average of tags in use -system.l2c.tags.total_refs 6644913 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1460922 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.548438 # Average number of references to valid blocks. +system.l2c.tags.replacements 1736304 # number of replacements +system.l2c.tags.tagsinuse 63595.107970 # Cycle average of tags in use +system.l2c.tags.total_refs 7296515 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1796625 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.061234 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 21707.053985 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 102.735345 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 115.995716 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4966.190479 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4993.948919 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 6019.423287 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 241.036337 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 317.216521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3872.812023 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8822.287754 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12306.009376 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.331223 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001568 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001770 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075778 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.076202 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.091849 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003678 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004840 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.059094 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.134617 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.187775 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.968395 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10216 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 187 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50722 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 140 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 3377 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 6697 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 176 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2228 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13666 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 34520 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.155884 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.002853 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.773956 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 81151228 # Number of tag accesses -system.l2c.tags.data_accesses 81151228 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2809703 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2809703 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 181902 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 125777 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 307679 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 42034 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 42908 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 84942 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 62506 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 50661 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113167 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7522 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5409 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 680705 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 645150 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 332678 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6067 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4079 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 638595 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 567372 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 305148 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3192725 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 139615 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 131240 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 270855 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 7522 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5409 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 680705 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 707656 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 332678 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6067 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4079 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 638595 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 618033 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 305148 # number of demand (read+write) hits -system.l2c.demand_hits::total 3305892 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 7522 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5409 # number of overall hits -system.l2c.overall_hits::cpu0.inst 680705 # number of overall hits -system.l2c.overall_hits::cpu0.data 707656 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 332678 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6067 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4079 # number of overall hits -system.l2c.overall_hits::cpu1.inst 638595 # number of overall hits -system.l2c.overall_hits::cpu1.data 618033 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 305148 # number of overall hits -system.l2c.overall_hits::total 3305892 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 64206 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 62132 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 126338 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 12168 # 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.132204 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.970384 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 8701 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 194 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 51426 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 62 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 67 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 253 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1394 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 6925 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 186 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 389 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2651 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 12885 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 35470 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.132767 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.002960 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.784698 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 90467673 # Number of tag accesses +system.l2c.tags.data_accesses 90467673 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 3161640 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 3161640 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 190042 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 150318 # 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average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146076.538245 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69978.879648 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69612.317690 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69901.332925 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124649.624738 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129665.397702 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124535.368286 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 128141.349774 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 143389.033978 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124649.624738 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129665.397702 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124535.368286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128141.349774 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 143389.033978 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.260477 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.292781 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.275100 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.226122 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.236223 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230886 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573251 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.549054 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.562606 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.322586 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.397560 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.092611 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.213527 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.452612 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.275687 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.341605 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.081075 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.162635 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.522701 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.239318 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.745352 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.563953 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.681658 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.322586 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.397560 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.092611 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.267207 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.452612 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.275687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.341605 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.081075 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.213268 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.522701 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.258011 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.322586 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.397560 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.092611 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.267207 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.452612 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.275687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.341605 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.081075 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.213268 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.522701 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.258011 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70758.339917 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70359.930821 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70566.394621 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73641.009191 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73548.748351 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73596.483261 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 127912.406083 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 128004.597362 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 127951.987161 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131423.037819 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134145.307792 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 150265.373892 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70087.808865 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69270.608839 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69850.417852 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 130299.138826 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 132073.816824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 147452.086842 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 130299.138826 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 132073.816824 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 147452.086842 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164525.170581 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 148992.246785 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 98704.194085 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129944.590793 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163469.575571 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 116608.102749 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154761.116604 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158707.724699 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130545.300866 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147439.379444 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163149.942166 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156581.535643 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164002.261932 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148193.566448 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 107960.094609 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 137341.128933 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160879.796728 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 138261.266457 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 91274 # Transaction distribution -system.membus.trans_dist::ReadResp 916539 # Transaction distribution -system.membus.trans_dist::WriteReq 38755 # Transaction distribution -system.membus.trans_dist::WriteResp 38755 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1197090 # Transaction distribution -system.membus.trans_dist::CleanEvict 262945 # Transaction distribution -system.membus.trans_dist::UpgradeReq 440993 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 308067 # Transaction distribution +system.membus.trans_dist::ReadReq 90728 # Transaction distribution +system.membus.trans_dist::ReadResp 1177835 # Transaction distribution +system.membus.trans_dist::WriteReq 38212 # Transaction distribution +system.membus.trans_dist::WriteResp 38212 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1451911 # Transaction distribution +system.membus.trans_dist::CleanEvict 312799 # Transaction distribution +system.membus.trans_dist::UpgradeReq 438732 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 328709 # Transaction distribution system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 144406 # Transaction distribution -system.membus.trans_dist::ReadExResp 127298 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 825265 # Transaction distribution -system.membus.trans_dist::InvalidateReq 666679 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122958 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 166722 # Transaction distribution +system.membus.trans_dist::ReadExResp 150087 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1087107 # Transaction distribution +system.membus.trans_dist::InvalidateReq 695373 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122964 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4666640 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4816726 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238694 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238694 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5055420 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155996 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5587054 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5734962 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238554 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238554 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5973516 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156002 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 133490240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 133701712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7291456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7291456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 140993168 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 609728 # Total snoops (count) -system.membus.snoop_fanout::samples 3975535 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168012608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 168219718 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7276864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 175496582 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 622390 # Total snoops (count) +system.membus.snoop_fanout::samples 4610336 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3975535 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4610336 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3975535 # Request fanout histogram -system.membus.reqLayer0.occupancy 110272997 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4610336 # Request fanout histogram +system.membus.reqLayer0.occupancy 110366494 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22907496 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20951999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8443265855 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 10147074149 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5364054651 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6858565377 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45386996 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45617493 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3215,54 +3217,53 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 12590063 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6816351 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2112405 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 136080 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 123352 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 12728 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 91276 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4889046 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38755 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38755 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4006843 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 3033326 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 740212 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 393009 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1133221 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 135 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 301958 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301958 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4804997 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 940884 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 833900 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10292862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8190937 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18483799 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255537947 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200300853 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 455838800 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3066288 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8826957 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.357421 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.482240 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 13817515 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 7477037 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2215935 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 187202 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 169247 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 17955 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 90730 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5393978 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38212 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38212 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4613586 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 3368394 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 769711 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 415575 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1185286 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 166 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 331620 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 331620 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 5310492 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 975909 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 868925 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10817825 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9492092 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 20309917 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 274107435 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 237950875 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 512058310 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3424368 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9784683 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.340448 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.477717 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5684742 64.40% 64.40% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3129487 35.45% 99.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 12728 0.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6471464 66.14% 66.14% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3295264 33.68% 99.82% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 17955 0.18% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8826957 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9586281743 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9784683 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 10614903907 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2585661 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2624417 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4723415116 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5004390482 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4064152578 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4630478453 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal index d57761389..049b0949c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal @@ -31,136 +31,136 @@ [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
-[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[ 0.000028] Console: colour dummy device 80x25
[ 0.000031] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000033] pid_max: default: 32768 minimum: 301
-[ 0.000046] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000047] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000219] hw perfevents: no hardware support available
-[ 0.060056] CPU1: Booted secondary processor
+[ 0.000032] pid_max: default: 32768 minimum: 301
+[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000046] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000199] hw perfevents: no hardware support available
+[ 0.060051] CPU1: Booted secondary processor
[ 1.080085] CPU2: failed to come online
-[ 2.100162] CPU3: failed to come online
-[ 2.100165] Brought up 2 CPUs
-[ 2.100166] SMP: Total of 2 processors activated.
-[ 2.100236] devtmpfs: initialized
-[ 2.100755] atomic64_test: passed
-[ 2.100809] regulator-dummy: no parameters
-[ 2.101182] NET: Registered protocol family 16
-[ 2.101326] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 2.101335] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 2.102656] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 2.102660] Serial: AMBA PL011 UART driver
-[ 2.102871] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 2.102913] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 2.103488] console [ttyAMA0] enabled
-[ 2.103636] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 2.103696] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 2.103756] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 2.103816] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 2.140419] 3V3: 3300 mV
-[ 2.140469] vgaarb: loaded
-[ 2.140516] SCSI subsystem initialized
-[ 2.140554] libata version 3.00 loaded.
-[ 2.140615] usbcore: registered new interface driver usbfs
-[ 2.140634] usbcore: registered new interface driver hub
-[ 2.140657] usbcore: registered new device driver usb
-[ 2.140684] pps_core: LinuxPPS API ver. 1 registered
-[ 2.140693] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 2.140713] PTP clock support registered
-[ 2.140852] Switched to clocksource arch_sys_counter
-[ 2.141883] NET: Registered protocol family 2
-[ 2.141966] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 2.141983] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 2.142000] TCP: Hash tables configured (established 2048 bind 2048)
-[ 2.142036] TCP: reno registered
-[ 2.142043] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.142056] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.142093] NET: Registered protocol family 1
-[ 2.142147] RPC: Registered named UNIX socket transport module.
-[ 2.142158] RPC: Registered udp transport module.
-[ 2.142166] RPC: Registered tcp transport module.
-[ 2.142175] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 2.142187] PCI: CLS 0 bytes, default 64
-[ 2.142348] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 2.142446] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 2.144602] fuse init (API version 7.23)
-[ 2.144721] msgmni has been set to 469
-[ 2.144831] io scheduler noop registered
-[ 2.144882] io scheduler cfq registered (default)
-[ 2.145442] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 2.145456] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 2.145468] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.145481] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 2.145491] pci_bus 0000:00: scanning bus
-[ 2.145502] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 2.145516] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 2.145531] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.145568] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 2.145580] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 2.145591] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 2.145601] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.145612] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 2.145623] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 2.145635] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.145670] pci_bus 0000:00: fixups for bus
-[ 2.145678] pci_bus 0000:00: bus scan returning with max=00
-[ 2.145690] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 2.145712] pci 0000:00:00.0: fixup irq: got 33
-[ 2.145720] pci 0000:00:00.0: assigning IRQ 33
-[ 2.145731] pci 0000:00:01.0: fixup irq: got 34
-[ 2.145740] pci 0000:00:01.0: assigning IRQ 34
-[ 2.145752] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 2.145765] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.145778] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 2.145791] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 2.145803] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.145814] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 2.145826] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 2.145838] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 2.146509] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.146789] ata_piix 0000:00:01.0: version 2.13
-[ 2.146800] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.146833] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.147105] scsi0 : ata_piix
-[ 2.147189] scsi1 : ata_piix
-[ 2.147233] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.147246] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.147373] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 2.147386] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 2.147401] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.147412] e1000 0000:00:00.0: enabling bus mastering
-[ 2.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.290910] ata1.00: 2096640 sectors, multi 0: LBA
-[ 2.290939] ata1.00: configured for UDMA/33
-[ 2.291006] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.291132] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 2.291158] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.291199] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.291208] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.291229] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.291366] sda: sda1
-[ 2.291489] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 2.411161] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 2.411175] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 2.411196] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 2.411207] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 2.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 2.411241] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 2.411314] usbcore: registered new interface driver usb-storage
-[ 2.411382] mousedev: PS/2 mouse device common for all mice
-[ 2.411554] usbcore: registered new interface driver usbhid
-[ 2.411564] usbhid: USB HID core driver
-[ 2.411599] TCP: cubic registered
-[ 2.411606] NET: Registered protocol family 17
- -[ 2.412104] devtmpfs: mounted
-[ 2.412177] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 2.100161] CPU3: failed to come online
+[ 2.100164] Brought up 2 CPUs
+[ 2.100165] SMP: Total of 2 processors activated.
+[ 2.100234] devtmpfs: initialized
+[ 2.100742] atomic64_test: passed
+[ 2.100794] regulator-dummy: no parameters
+[ 2.101157] NET: Registered protocol family 16
+[ 2.101296] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.101304] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.102113] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.102117] Serial: AMBA PL011 UART driver
+[ 2.102318] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.102358] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.102933] console [ttyAMA0] enabled
+[ 2.103072] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.103132] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.103192] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.103250] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.140336] 3V3: 3300 mV
+[ 2.140383] vgaarb: loaded
+[ 2.140429] SCSI subsystem initialized
+[ 2.140466] libata version 3.00 loaded.
+[ 2.140524] usbcore: registered new interface driver usbfs
+[ 2.140543] usbcore: registered new interface driver hub
+[ 2.140567] usbcore: registered new device driver usb
+[ 2.140593] pps_core: LinuxPPS API ver. 1 registered
+[ 2.140602] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.140621] PTP clock support registered
+[ 2.140762] Switched to clocksource arch_sys_counter
+[ 2.141783] NET: Registered protocol family 2
+[ 2.141863] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.141880] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.141897] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.141925] TCP: reno registered
+[ 2.141932] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.141945] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.141981] NET: Registered protocol family 1
+[ 2.142034] RPC: Registered named UNIX socket transport module.
+[ 2.142044] RPC: Registered udp transport module.
+[ 2.142052] RPC: Registered tcp transport module.
+[ 2.142061] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.142073] PCI: CLS 0 bytes, default 64
+[ 2.142235] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.142334] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.144468] fuse init (API version 7.23)
+[ 2.144588] msgmni has been set to 469
+[ 2.144697] io scheduler noop registered
+[ 2.144749] io scheduler cfq registered (default)
+[ 2.145214] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.145228] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.145239] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.145252] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.145262] pci_bus 0000:00: scanning bus
+[ 2.145274] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.145288] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.145302] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.145340] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.145352] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.145363] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.145373] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.145384] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.145395] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.145406] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.145441] pci_bus 0000:00: fixups for bus
+[ 2.145450] pci_bus 0000:00: bus scan returning with max=00
+[ 2.145462] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.145483] pci 0000:00:00.0: fixup irq: got 33
+[ 2.145492] pci 0000:00:00.0: assigning IRQ 33
+[ 2.145502] pci 0000:00:01.0: fixup irq: got 34
+[ 2.145511] pci 0000:00:01.0: assigning IRQ 34
+[ 2.145524] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.145538] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.145551] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.145564] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.145576] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.145587] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.145599] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.145610] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.146274] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.146553] ata_piix 0000:00:01.0: version 2.13
+[ 2.146565] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.146593] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.146864] scsi0 : ata_piix
+[ 2.146948] scsi1 : ata_piix
+[ 2.146979] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.146991] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.147095] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.147108] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.147123] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.147134] e1000 0000:00:00.0: enabling bus mastering
+[ 2.290805] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.290816] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.290846] ata1.00: configured for UDMA/33
+[ 2.290909] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.291028] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.291029] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.291056] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.291067] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.291092] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.291248] sda: sda1
+[ 2.291370] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.411068] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.411082] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.411104] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.411115] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.411135] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.411147] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.411217] usbcore: registered new interface driver usb-storage
+[ 2.411286] mousedev: PS/2 mouse device common for all mice
+[ 2.411453] usbcore: registered new interface driver usbhid
+[ 2.411463] usbhid: USB HID core driver
+[ 2.411495] TCP: cubic registered
+[ 2.411502] NET: Registered protocol family 17
+ +[ 2.411975] devtmpfs: mounted
+[ 2.412025] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.450669] udevd[609]: starting version 182
+[ 2.460540] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.523747] random: dd urandom read with 17 bits of entropy available
+[ 2.553667] random: dd urandom read with 18 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.651088] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.680995] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
|