diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt | 2129 |
1 files changed, 1066 insertions, 1063 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index f3459bbfc..72f54d4c6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.728175 # Number of seconds simulated -sim_ticks 51728174627500 # Number of ticks simulated -final_tick 51728174627500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.690388 # Number of seconds simulated +sim_ticks 51690388482000 # Number of ticks simulated +final_tick 51690388482000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121986 # Simulator instruction rate (inst/s) -host_op_rate 143338 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6618487836 # Simulator tick rate (ticks/s) -host_mem_usage 708088 # Number of bytes of host memory used -host_seconds 7815.71 # Real time elapsed on the host -sim_insts 953410832 # Number of instructions simulated -sim_ops 1120287994 # Number of ops (including micro ops) simulated +host_inst_rate 185969 # Simulator instruction rate (inst/s) +host_op_rate 218525 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10104822635 # Simulator tick rate (ticks/s) +host_mem_usage 719212 # Number of bytes of host memory used +host_seconds 5115.42 # Real time elapsed on the host +sim_insts 951311494 # Number of instructions simulated +sim_ops 1117847862 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 394816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 334912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10241472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 67386632 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 424256 # Number of bytes read from this memory -system.physmem.bytes_read::total 78782088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10241472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10241472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 95103808 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 413184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 346752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10436032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 67415176 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 415104 # Number of bytes read from this memory +system.physmem.bytes_read::total 79026248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10436032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10436032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 95778368 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 95124388 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5233 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 160023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1052929 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6629 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1230983 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1485997 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 95798948 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 163063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1053375 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6486 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1234798 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1496537 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1488570 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 197986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1302707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1523002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197986 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197986 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1838530 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1499110 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 201895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1304211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1528838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852924 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1838928 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1838530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7633 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1303104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3361929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1230983 # Number of read requests accepted -system.physmem.writeReqs 2135785 # Number of write requests accepted -system.physmem.readBursts 1230983 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2135785 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 78738176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 44736 # Total number of bytes read from write queue -system.physmem.bytesWritten 136238784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 78782088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 136546148 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 699 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7032 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 39789 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 72855 # Per bank write bursts -system.physmem.perBankRdBursts::1 77589 # Per bank write bursts -system.physmem.perBankRdBursts::2 71702 # Per bank write bursts -system.physmem.perBankRdBursts::3 69206 # Per bank write bursts -system.physmem.perBankRdBursts::4 71012 # Per bank write bursts -system.physmem.perBankRdBursts::5 79882 # Per bank write bursts -system.physmem.perBankRdBursts::6 74555 # Per bank write bursts -system.physmem.perBankRdBursts::7 73696 # Per bank write bursts -system.physmem.perBankRdBursts::8 66951 # Per bank write bursts -system.physmem.perBankRdBursts::9 130748 # Per bank write bursts -system.physmem.perBankRdBursts::10 72702 # Per bank write bursts -system.physmem.perBankRdBursts::11 77684 # Per bank write bursts -system.physmem.perBankRdBursts::12 73029 # Per bank write bursts -system.physmem.perBankRdBursts::13 75645 # Per bank write bursts -system.physmem.perBankRdBursts::14 69035 # Per bank write bursts -system.physmem.perBankRdBursts::15 73993 # Per bank write bursts -system.physmem.perBankWrBursts::0 130105 # Per bank write bursts -system.physmem.perBankWrBursts::1 136647 # Per bank write bursts -system.physmem.perBankWrBursts::2 132594 # Per bank write bursts -system.physmem.perBankWrBursts::3 132058 # Per bank write bursts -system.physmem.perBankWrBursts::4 132790 # Per bank write bursts -system.physmem.perBankWrBursts::5 135723 # Per bank write bursts -system.physmem.perBankWrBursts::6 131916 # Per bank write bursts -system.physmem.perBankWrBursts::7 135307 # Per bank write bursts -system.physmem.perBankWrBursts::8 129762 # Per bank write bursts -system.physmem.perBankWrBursts::9 138269 # Per bank write bursts -system.physmem.perBankWrBursts::10 133041 # Per bank write bursts -system.physmem.perBankWrBursts::11 135411 # Per bank write bursts -system.physmem.perBankWrBursts::12 131809 # Per bank write bursts -system.physmem.perBankWrBursts::13 134107 # Per bank write bursts -system.physmem.perBankWrBursts::14 128778 # Per bank write bursts -system.physmem.perBankWrBursts::15 130414 # Per bank write bursts +system.physmem.bw_write::total 1853322 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 201895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1304609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3382161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1234798 # Number of read requests accepted +system.physmem.writeReqs 2155868 # Number of write requests accepted +system.physmem.readBursts 1234798 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2155868 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 78985984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 41088 # Total number of bytes read from write queue +system.physmem.bytesWritten 134775168 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 79026248 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 137831460 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 642 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49988 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 39660 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 74085 # Per bank write bursts +system.physmem.perBankRdBursts::1 76722 # Per bank write bursts +system.physmem.perBankRdBursts::2 75273 # Per bank write bursts +system.physmem.perBankRdBursts::3 67779 # Per bank write bursts +system.physmem.perBankRdBursts::4 73670 # Per bank write bursts +system.physmem.perBankRdBursts::5 87218 # Per bank write bursts +system.physmem.perBankRdBursts::6 75623 # Per bank write bursts +system.physmem.perBankRdBursts::7 75034 # Per bank write bursts +system.physmem.perBankRdBursts::8 70647 # Per bank write bursts +system.physmem.perBankRdBursts::9 127770 # Per bank write bursts +system.physmem.perBankRdBursts::10 77193 # Per bank write bursts +system.physmem.perBankRdBursts::11 73706 # Per bank write bursts +system.physmem.perBankRdBursts::12 69495 # Per bank write bursts +system.physmem.perBankRdBursts::13 70758 # Per bank write bursts +system.physmem.perBankRdBursts::14 68705 # Per bank write bursts +system.physmem.perBankRdBursts::15 70478 # Per bank write bursts +system.physmem.perBankWrBursts::0 131375 # Per bank write bursts +system.physmem.perBankWrBursts::1 133100 # Per bank write bursts +system.physmem.perBankWrBursts::2 134570 # Per bank write bursts +system.physmem.perBankWrBursts::3 130352 # Per bank write bursts +system.physmem.perBankWrBursts::4 132576 # Per bank write bursts +system.physmem.perBankWrBursts::5 140660 # Per bank write bursts +system.physmem.perBankWrBursts::6 130709 # Per bank write bursts +system.physmem.perBankWrBursts::7 134220 # Per bank write bursts +system.physmem.perBankWrBursts::8 130946 # Per bank write bursts +system.physmem.perBankWrBursts::9 136651 # Per bank write bursts +system.physmem.perBankWrBursts::10 131424 # Per bank write bursts +system.physmem.perBankWrBursts::11 131217 # Per bank write bursts +system.physmem.perBankWrBursts::12 125851 # Per bank write bursts +system.physmem.perBankWrBursts::13 128099 # Per bank write bursts +system.physmem.perBankWrBursts::14 126227 # Per bank write bursts +system.physmem.perBankWrBursts::15 127885 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 51728172924500 # Total gap between requests +system.physmem.numWrRetry 155 # Number of times write queue was full causing retry +system.physmem.totGap 51690386784000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1230968 # Read request sizes (log2) +system.physmem.readPktSize::6 1234783 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2133212 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1193516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 30294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 774 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2153295 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1198377 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 29223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -159,161 +159,158 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 48810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 75161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 120471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 133680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 129638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 132279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 134371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 139270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 139351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 138718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 134041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 121456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 116921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 112653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 104822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 724941 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.543548 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 170.840359 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.964737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 292739 40.38% 40.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 175978 24.27% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 64522 8.90% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 36242 5.00% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25200 3.48% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 17306 2.39% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13334 1.84% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 11857 1.64% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 87763 12.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 724941 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98383 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.504427 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 125.607658 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 98380 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 52281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 61850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 106555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 108316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 116449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 154618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 128128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 118111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 116108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 109682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 109242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 142032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 116099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 110906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 124147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 111898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 106882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 105751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 8381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 7481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 6361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 272 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 737863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 289.702517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.794717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.456499 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 301335 40.84% 40.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 180643 24.48% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 66243 8.98% 74.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 37149 5.03% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 25772 3.49% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 17225 2.33% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13400 1.82% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 11666 1.58% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 84430 11.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 737863 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 101448 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.165149 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 123.730461 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 101445 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98383 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.637183 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.054808 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.113777 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 71754 72.93% 72.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 19885 20.21% 93.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 3061 3.11% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 745 0.76% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 867 0.88% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 408 0.41% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 354 0.36% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 234 0.24% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 298 0.30% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 183 0.19% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 211 0.21% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 51 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 56 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 41 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 125 0.13% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 21 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 37 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 9 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 12 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 7 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98383 # Writes before turning the bus around for reads -system.physmem.totQLat 15890716010 # Total ticks spent queuing -system.physmem.totMemAccLat 38958541010 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6151420000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12916.30 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 101448 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 101448 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.758044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.253158 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.739377 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 97720 96.33% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 2404 2.37% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 434 0.43% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 505 0.50% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 168 0.17% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 63 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 44 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 12 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 10 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 11 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 20 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 26 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 6 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-735 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::832-863 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-927 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::928-959 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1152-1183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 101448 # Writes before turning the bus around for reads +system.physmem.totQLat 16140892467 # Total ticks spent queuing +system.physmem.totMemAccLat 39281317467 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6170780000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13078.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31666.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31828.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.61 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing -system.physmem.readRowHits 953619 # Number of row buffer hits during reads -system.physmem.writeRowHits 1680454 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes -system.physmem.avgGap 15364341.39 # Average gap between requests -system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2748558960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1499709750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4605829800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6915067200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3378632599680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1310572243215 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29887277315250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34592251323855 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.731394 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49719326487750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1727317280000 # Time in different power states +system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing +system.physmem.readRowHits 952465 # Number of row buffer hits during reads +system.physmem.writeRowHits 1649689 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.34 # Row buffer hit rate for writes +system.physmem.avgGap 15244906.69 # Average gap between requests +system.physmem.pageHitRate 77.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2866207680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1563903000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4722104400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6917801760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3376164558000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1320834277260 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29855603520000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34568672372100 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.764092 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49666580122402 # Time in different power states +system.physmem_0.memoryStateTime::REF 1726055500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 281530424750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 297752382598 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2731995000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1490671875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4990338600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6879109680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3378632599680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1309819963770 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29887937201250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34592481879855 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.735851 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49720391571002 # Time in different power states -system.physmem_1.memoryStateTime::REF 1727317280000 # Time in different power states +system.physmem_1.actEnergy 2712036600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1479781875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4904265600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6728184000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3376164558000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1311236111385 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29864022963750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34567247901210 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.736534 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49680605946994 # Time in different power states +system.physmem_1.memoryStateTime::REF 1726055500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 280461298998 # Time in different power states +system.physmem_1.memoryStateTime::ACT 283722031756 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -337,15 +334,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 261740307 # Number of BP lookups -system.cpu.branchPred.condPredicted 183617747 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12193617 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 193974198 # Number of BTB lookups -system.cpu.branchPred.BTBHits 136954935 # Number of BTB hits +system.cpu.branchPred.lookups 261231631 # Number of BP lookups +system.cpu.branchPred.condPredicted 183305796 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12196019 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 193363774 # Number of BTB lookups +system.cpu.branchPred.BTBHits 136711559 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.604718 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31757981 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2120874 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.701743 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31664930 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2143732 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -376,61 +373,68 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 587644 # Table walker walks requested -system.cpu.dtb.walker.walksLong 587644 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20971 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 193860 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 587644 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 587644 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 587644 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 214831 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23073.231987 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 18856.280230 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 14797.492454 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 212337 98.84% 98.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2138 1.00% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 152 0.07% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 133 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 38 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 214831 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -243009796 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -243009796 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -243009796 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 193861 90.24% 90.24% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 20971 9.76% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 214832 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 587644 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 585994 # Table walker walks requested +system.cpu.dtb.walker.walksLong 585994 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21793 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191747 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 585994 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 585994 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 585994 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 213540 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24710.005137 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20824.581984 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15872.776829 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 123160 57.68% 57.68% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 87731 41.08% 98.76% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 1449 0.68% 99.44% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 786 0.37% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 33 0.02% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 127 0.06% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-229375 51 0.02% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::229376-262143 62 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 77 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 22 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 20 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::360448-393215 10 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-491519 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 213540 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -15748296 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -15748296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -15748296 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 191748 89.79% 89.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 21793 10.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 213541 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 585994 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 587644 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 214832 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 585994 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213541 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 214832 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 802476 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213541 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 799535 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 184101010 # DTB read hits -system.cpu.dtb.read_misses 486113 # DTB read misses -system.cpu.dtb.write_hits 163332837 # DTB write hits -system.cpu.dtb.write_misses 101531 # DTB write misses +system.cpu.dtb.read_hits 183604569 # DTB read hits +system.cpu.dtb.read_misses 484391 # DTB read misses +system.cpu.dtb.write_hits 162970808 # DTB write hits +system.cpu.dtb.write_misses 101603 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47436 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 47405 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 79171 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 889 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14871 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 80226 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 794 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23598 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 184587123 # DTB read accesses -system.cpu.dtb.write_accesses 163434368 # DTB write accesses +system.cpu.dtb.perms_faults 23565 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 184088960 # DTB read accesses +system.cpu.dtb.write_accesses 163072411 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 347433847 # DTB hits -system.cpu.dtb.misses 587644 # DTB misses -system.cpu.dtb.accesses 348021491 # DTB accesses +system.cpu.dtb.hits 346575377 # DTB hits +system.cpu.dtb.misses 585994 # DTB misses +system.cpu.dtb.accesses 347161371 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -460,175 +464,175 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 136955 # Table walker walks requested -system.cpu.itb.walker.walksLong 136955 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1083 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 119238 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 136955 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 136955 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 136955 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 120321 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 25178.697160 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 21090.590253 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 16725.174106 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 117467 97.63% 97.63% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2593 2.16% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 161 0.13% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 40 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 38 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 136676 # Table walker walks requested +system.cpu.itb.walker.walksLong 136676 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1079 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 118957 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 136676 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 136676 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 136676 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 120036 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27117.842072 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23228.726671 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17468.785563 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 117053 97.51% 97.51% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2702 2.25% 99.77% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 172 0.14% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 64 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 25 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 17 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 120321 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -243525796 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -243525796 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -243525796 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 119238 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1083 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 120321 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 120036 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -16365796 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -16365796 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -16365796 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 118957 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1079 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 120036 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136955 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 136955 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136676 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 136676 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120321 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 120321 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 257276 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 455989522 # ITB inst hits -system.cpu.itb.inst_misses 136955 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120036 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 120036 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 256712 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 454948976 # ITB inst hits +system.cpu.itb.inst_misses 136676 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47436 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 47405 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 56761 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 57709 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 364272 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 370702 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 456126477 # ITB inst accesses -system.cpu.itb.hits 455989522 # DTB hits -system.cpu.itb.misses 136955 # DTB misses -system.cpu.itb.accesses 456126477 # DTB accesses -system.cpu.numCycles 2523007146 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 455085652 # ITB inst accesses +system.cpu.itb.hits 454948976 # DTB hits +system.cpu.itb.misses 136676 # DTB misses +system.cpu.itb.accesses 455085652 # DTB accesses +system.cpu.numCycles 2543244455 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 953410832 # Number of instructions committed -system.cpu.committedOps 1120287994 # Number of ops (including micro ops) committed -system.cpu.discardedOps 97416264 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7771 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100934517430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.646296 # CPI: cycles per instruction -system.cpu.ipc 0.377887 # IPC: instructions per cycle +system.cpu.committedInsts 951311494 # Number of instructions committed +system.cpu.committedOps 1117847862 # Number of ops (including micro ops) committed +system.cpu.discardedOps 97312681 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7756 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100838701590 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.673409 # CPI: cycles per instruction +system.cpu.ipc 0.374054 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16631 # number of quiesce instructions executed -system.cpu.tickCycles 1807938889 # Number of cycles that the object actually ticked -system.cpu.idleCycles 715068257 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 11209162 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.959689 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 331084794 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11209674 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.535631 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4089991250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.959689 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999921 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16616 # number of quiesce instructions executed +system.cpu.tickCycles 1803568308 # Number of cycles that the object actually ticked +system.cpu.idleCycles 739676147 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 11160252 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.957398 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 330283218 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11160764 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.593245 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4320792250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.957398 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1391009936 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1391009936 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 169770938 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 169770938 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 152453541 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 152453541 # number of WriteReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337498 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 337498 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4114364 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4114364 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4358642 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4358642 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 322224479 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322224479 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 322224479 # number of overall hits -system.cpu.dcache.overall_hits::total 322224479 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 8085158 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 8085158 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4338895 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4338895 # number of WriteReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245002 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1245002 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 246013 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 246013 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 12424053 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12424053 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12424053 # number of overall misses -system.cpu.dcache.overall_misses::total 12424053 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 128824080247 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128824080247 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 144514675403 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 144514675403 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 29607413192 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 29607413192 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3571422003 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 3571422003 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 273338755650 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 273338755650 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 273338755650 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 273338755650 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 177856096 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177856096 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 156792436 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 156792436 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1582500 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1582500 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4360377 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4360377 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4358644 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4358644 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 334648532 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 334648532 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 334648532 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 334648532 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.045459 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.045459 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027673 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027673 # miss rate for WriteReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786731 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786731 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056420 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056420 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1387540349 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1387540349 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 169325544 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 169325544 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 152117254 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 152117254 # number of WriteReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336638 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 336638 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4103260 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4103260 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4350721 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4350721 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 321442798 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 321442798 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 321442798 # number of overall hits +system.cpu.dcache.overall_hits::total 321442798 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 8046914 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 8046914 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4320227 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4320227 # number of WriteReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245138 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1245138 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 249194 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 249194 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 12367141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12367141 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12367141 # number of overall misses +system.cpu.dcache.overall_misses::total 12367141 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 131461867675 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 131461867675 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 154903534956 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 154903534956 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35707428702 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35707428702 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3656528250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 3656528250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 286365402631 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 286365402631 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 286365402631 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 286365402631 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 177372458 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177372458 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 156437481 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 156437481 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1581776 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1581776 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4352454 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4352454 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4350722 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4350722 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 333809939 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 333809939 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 333809939 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 333809939 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.045367 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.045367 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027616 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027616 # miss rate for WriteReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787177 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787177 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057254 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057254 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037126 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037126 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037126 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037126 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15933.402940 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15933.402940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33306.792490 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33306.792490 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 23781.016570 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 23781.016570 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14517.208452 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14517.208452 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75250 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22000.771862 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22000.771862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22000.771862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22000.771862 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.037048 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037048 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037048 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037048 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16336.929620 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16336.929620 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.415689 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.415689 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28677.486915 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28677.486915 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14673.420106 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14673.420106 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23155.343877 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23155.343877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23155.343877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23155.343877 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,82 +641,82 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8593512 # number of writebacks -system.cpu.dcache.writebacks::total 8593512 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 755938 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 755938 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1899458 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1899458 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 141 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 141 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2655396 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2655396 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2655396 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2655396 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7329220 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7329220 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2439437 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2439437 # number of WriteReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244861 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244861 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 246009 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 246009 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9768657 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9768657 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9768657 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9768657 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 102525908749 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 102525908749 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73694416463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73694416463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 27114416558 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 27114416558 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3077572997 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3077572997 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176220325212 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 176220325212 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176220325212 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 176220325212 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5727815999 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5727815999 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5585117500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5585117500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11312933499 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11312933499 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041209 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041209 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015558 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015558 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786642 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786642 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056419 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056419 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 8571803 # number of writebacks +system.cpu.dcache.writebacks::total 8571803 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 759012 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 759012 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1891728 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1891728 # number of WriteReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 152 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 152 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2650740 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2650740 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2650740 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2650740 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7287902 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7287902 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2428499 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2428499 # number of WriteReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244986 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244986 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 249191 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 249191 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9716401 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9716401 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9716401 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9716401 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108232242328 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 108232242328 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80044946410 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 80044946410 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33835516298 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33835516298 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3281036750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3281036750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 80500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 80500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 188277188738 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 188277188738 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 188277188738 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 188277188738 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5752052750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5752052750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5611431750 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5611431750 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363484500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363484500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015524 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015524 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787081 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787081 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057253 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057253 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029191 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029191 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029191 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029191 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13988.652101 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13988.652101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30209.600192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30209.600192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21781.079621 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 21781.079621 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12510.001654 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12510.001654 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18039.360499 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18039.360499 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029108 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029108 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029108 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029108 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14850.946449 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14850.946449 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32960.666819 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32960.666819 # average WriteReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27177.427134 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27177.427134 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.754618 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.754618 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19377.255914 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19377.255914 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19377.255914 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19377.255914 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -720,58 +724,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24725990 # number of replacements -system.cpu.icache.tags.tagsinuse 511.931995 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 430886861 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24726502 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.426115 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 21192166000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.931995 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999867 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999867 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 24658319 # number of replacements +system.cpu.icache.tags.tagsinuse 511.926866 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 429907589 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24658831 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.434224 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 23112715250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.926866 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999857 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 480339884 # Number of tag accesses -system.cpu.icache.tags.data_accesses 480339884 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 430886861 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 430886861 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 430886861 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 430886861 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 430886861 # number of overall hits -system.cpu.icache.overall_hits::total 430886861 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24726512 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24726512 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24726512 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24726512 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24726512 # number of overall misses -system.cpu.icache.overall_misses::total 24726512 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 328589993689 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 328589993689 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 328589993689 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 328589993689 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 328589993689 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 328589993689 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 455613373 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 455613373 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 455613373 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 455613373 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 455613373 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 455613373 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054271 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.054271 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.054271 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.054271 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.054271 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.054271 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13288.974753 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13288.974753 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13288.974753 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13288.974753 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13288.974753 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13288.974753 # average overall miss latency +system.cpu.icache.tags.tag_accesses 479225270 # Number of tag accesses +system.cpu.icache.tags.data_accesses 479225270 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 429907589 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 429907589 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 429907589 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 429907589 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 429907589 # number of overall hits +system.cpu.icache.overall_hits::total 429907589 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24658841 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24658841 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24658841 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24658841 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24658841 # number of overall misses +system.cpu.icache.overall_misses::total 24658841 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 328732138519 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 328732138519 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 328732138519 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 328732138519 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 328732138519 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 328732138519 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 454566430 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 454566430 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 454566430 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 454566430 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 454566430 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 454566430 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054247 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.054247 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.054247 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.054247 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.054247 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.054247 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13331.208004 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13331.208004 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13331.208004 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13331.208004 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13331.208004 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13331.208004 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -780,208 +784,209 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24726512 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24726512 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24726512 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 24726512 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 24726512 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 24726512 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 279088621775 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 279088621775 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 279088621775 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 279088621775 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 279088621775 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 279088621775 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3812277750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3812277750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3812277750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 3812277750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054271 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.054271 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.054271 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11287.019446 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11287.019446 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11287.019446 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11287.019446 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11287.019446 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11287.019446 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24658841 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 24658841 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 24658841 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 24658841 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 24658841 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 24658841 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 291693903909 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 291693903909 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 291693903909 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 291693903909 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 291693903909 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 291693903909 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4024065500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4024065500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4024065500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 4024065500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054247 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.054247 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.054247 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11829.181425 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11829.181425 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11829.181425 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11829.181425 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11829.181425 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11829.181425 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1618545 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65358.053127 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 40402502 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1681764 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.023883 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5745484000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36067.634498 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 340.939586 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 425.072148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8071.479946 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20452.926949 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.550348 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005202 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006486 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123161 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.312087 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997285 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 346 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62873 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 346 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 1634699 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65328.398065 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 40258941 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1697658 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.714400 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6394381000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36150.495855 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 348.587735 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 419.061629 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8126.200133 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20284.052712 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.551613 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005319 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006394 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123996 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.309510 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996832 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 298 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62661 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 297 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2402 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5577 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54331 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005280 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959366 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 371551924 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 371551924 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 967297 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 281175 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 24618722 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 7240126 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 33107320 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 8593512 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 8593512 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 704117 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 704117 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 10834 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 10834 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1670528 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1670528 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 967297 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 281175 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 24618722 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 8910654 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 34777848 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 967297 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 281175 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 24618722 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 8910654 # number of overall hits -system.cpu.l2cache.overall_hits::total 34777848 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6169 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5233 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 107787 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 334891 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 454080 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 540744 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 540744 # number of WriteInvalidateReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 38969 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 38969 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 719318 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 719318 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 6169 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5233 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 107787 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1054209 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1173398 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 6169 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5233 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 107787 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1054209 # number of overall misses -system.cpu.l2cache.overall_misses::total 1173398 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 490563500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 420808500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 7986963739 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25374551222 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 34272886961 # number of ReadReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 4498807 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 4498807 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 431949947 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 431949947 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53534470118 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 53534470118 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 490563500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 420808500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 7986963739 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 78909021340 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 87807357079 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 490563500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 420808500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 7986963739 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 78909021340 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 87807357079 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 973466 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 286408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 24726509 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7575017 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 33561400 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 8593512 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 8593512 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1244861 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1244861 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49803 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 49803 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2389846 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2389846 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 973466 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 286408 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 24726509 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9964863 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 35951246 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 973466 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 286408 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 24726509 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9964863 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 35951246 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006337 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018271 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004359 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.044210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013530 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.434381 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.434381 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782463 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782463 # miss rate for UpgradeReq accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 526 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2409 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5622 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54054 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004547 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956131 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 370467994 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 370467994 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 967855 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 283816 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 24548042 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 7200740 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 33000453 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 8571803 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 8571803 # number of Writeback hits +system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 694691 # number of WriteInvalidateReq hits +system.cpu.l2cache.WriteInvalidateReq_hits::total 694691 # number of WriteInvalidateReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 10952 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 10952 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1660414 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1660414 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 967855 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 283816 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 24548042 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 8861154 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 34660867 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 967855 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 283816 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 24548042 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 8861154 # number of overall hits +system.cpu.l2cache.overall_hits::total 34660867 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6456 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5418 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 110797 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 336133 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 458804 # number of ReadReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 550295 # number of WriteInvalidateReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::total 550295 # number of WriteInvalidateReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 38841 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 38841 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 718512 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 718512 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 6456 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5418 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 110797 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1054645 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1177316 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 6456 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5418 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 110797 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1054645 # number of overall misses +system.cpu.l2cache.overall_misses::total 1177316 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 558145500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 469017250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9061497564 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28118014803 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 38206675117 # number of ReadReq miss cycles +system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 6284799 # number of WriteInvalidateReq miss cycles +system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 6284799 # number of WriteInvalidateReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 581575900 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 581575900 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58834664128 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 58834664128 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 558145500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 469017250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9061497564 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 86952678931 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 97041339245 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 558145500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 469017250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9061497564 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 86952678931 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 97041339245 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 974311 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 289234 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 24658839 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7536873 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 33459257 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 8571803 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 8571803 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1244986 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::total 1244986 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49793 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 49793 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2378926 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2378926 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 974311 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 289234 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 24658839 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9915799 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 35838183 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 974311 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 289234 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 24658839 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9915799 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 35838183 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006626 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018732 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004493 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.044598 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.013712 # miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.442009 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.442009 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780049 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780049 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.300989 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.300989 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006337 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018271 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004359 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.105793 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.032639 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006337 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018271 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004359 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.105793 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.032639 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79520.748906 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80414.389452 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74099.508651 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75769.582407 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75477.640418 # average ReadReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 8.319661 # average WriteInvalidateReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 8.319661 # average WriteInvalidateReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11084.450384 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11084.450384 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72250 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74423.926717 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74423.926717 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79520.748906 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80414.389452 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74099.508651 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74851.401705 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74831.691446 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79520.748906 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80414.389452 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74099.508651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74851.401705 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74831.691446 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.302032 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.302032 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006626 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018732 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004493 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.106360 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.032851 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006626 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018732 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004493 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.106360 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.032851 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86453.763941 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 86566.491325 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81784.683376 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83651.455831 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 83274.503093 # average ReadReq miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 11.420782 # average WriteInvalidateReq miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 11.420782 # average WriteInvalidateReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14973.247342 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14973.247342 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81884.038301 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81884.038301 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86453.763941 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 86566.491325 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81784.683376 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82447.343828 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82425.907101 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86453.763941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 86566.491325 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81784.683376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82447.343828 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82425.907101 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -990,117 +995,117 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1379367 # number of writebacks -system.cpu.l2cache.writebacks::total 1379367 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1389906 # number of writebacks +system.cpu.l2cache.writebacks::total 1389906 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 20 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 20 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 20 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6169 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5233 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 107785 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 334871 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 454058 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 540744 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 540744 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38969 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 38969 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 719318 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 719318 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6169 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5233 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 107785 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1054189 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1173376 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6169 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5233 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 107785 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1054189 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1173376 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 413632000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 355518000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6634859761 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21149756024 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28553765785 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 12667521943 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 12667521943 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 390061961 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 390061961 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44297743880 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44297743880 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 413632000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 355518000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6634859761 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65447499904 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 72851509665 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 413632000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 355518000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6634859761 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65447499904 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 72851509665 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2718370250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5287998001 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8006368251 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5177591000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5177591000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2718370250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465589001 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13183959251 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004359 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.044207 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013529 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.434381 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.434381 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782463 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782463 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 23 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6456 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5418 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 110795 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 336112 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 458781 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 550295 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 550295 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38841 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 38841 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 718512 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 718512 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5418 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 110795 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1054624 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1177293 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6456 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5418 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 110795 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1054624 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1177293 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 477004500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 400897250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7672809436 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23903949947 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32454661133 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 18536320703 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 18536320703 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 689128833 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 689128833 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 67500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 67500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49848772872 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49848772872 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 477004500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 400897250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7672809436 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73752722819 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 82303434005 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 477004500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 400897250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7672809436 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73752722819 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 82303434005 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3108920000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5279556250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8388476250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5172564500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5172564500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3108920000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10452120750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13561040750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006626 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018732 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004493 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.044596 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013712 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.442009 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.442009 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.780049 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.780049 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.300989 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.300989 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004359 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.105791 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.032638 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004359 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.105791 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.032638 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61556.429568 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.920584 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62885.723377 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 23426.098011 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 23426.098011 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10009.545049 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.545049 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61582.977042 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61582.977042 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61556.429568 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62083.269607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61556.429568 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62083.269607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.302032 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.302032 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006626 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018732 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004493 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.106358 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.032850 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006626 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018732 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004493 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.106358 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.032850 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73885.455390 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73993.586194 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69252.307740 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71119.001842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70741.075007 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 33684.334226 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33684.334226 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17742.304086 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17742.304086 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69377.787528 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69377.787528 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73885.455390 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73993.586194 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69252.307740 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69932.718029 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69909.048984 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73885.455390 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73993.586194 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69252.307740 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69932.718029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69909.048984 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1110,62 +1115,60 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 34111380 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 34103268 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8593512 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 49806 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 49808 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2389846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2389846 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49557548 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31248640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 695589 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2279215 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 83780992 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1585841408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1267646988 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2291264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7787728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2863567388 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 571370 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 46410026 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.002490 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.049834 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 33999690 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33991608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8571803 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 49796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 49797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2378926 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2378926 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49422267 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31128556 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 697608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2275060 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 83523491 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581512448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1263125858 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2313872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7794488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2854746666 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 562001 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 46265986 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.002499 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.049932 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 46294483 99.75% 99.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115543 0.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 46150346 99.75% 99.75% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115640 0.25% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 46410026 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 33063458385 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 46265986 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32968786985 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1149000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1168500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 37204558207 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 37104005805 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15864083234 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15790852218 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 409855669 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 409077948 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1306481232 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1301562725 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40405 # Transaction distribution -system.iobus.trans_dist::ReadResp 40405 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::ReadReq 40307 # Transaction distribution +system.iobus.trans_dist::ReadResp 40307 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1180,13 +1183,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230972 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230972 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354276 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1201,13 +1204,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334320 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492862 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1235,71 +1238,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042384689 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 606946752 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179052263 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148389141 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115484 # number of replacements -system.iocache.tags.tagsinuse 10.452585 # Cycle average of tags in use +system.iocache.tags.replacements 115468 # number of replacements +system.iocache.tags.tagsinuse 10.447877 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115484 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13141230176000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.516704 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.935881 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219794 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433493 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653287 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13143236480000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.519281 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.928596 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219955 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433037 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652992 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039884 # Number of tag accesses -system.iocache.tags.data_accesses 1039884 # Number of data accesses +system.iocache.tags.tag_accesses 1039731 # Number of tag accesses +system.iocache.tags.data_accesses 1039731 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8822 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8859 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses -system.iocache.demand_misses::total 8879 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8822 # number of demand (read+write) misses +system.iocache.demand_misses::total 8862 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8839 # number of overall misses -system.iocache.overall_misses::total 8879 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1924538358 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1930023358 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28851084068 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28851084068 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1924538358 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1930362358 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1924538358 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1930362358 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8822 # number of overall misses +system.iocache.overall_misses::total 8862 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1598742761 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1603814761 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19786721850 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19786721850 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1598742761 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1604167261 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1598742761 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1604167261 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8822 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8859 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8822 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8862 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8822 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8862 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1313,55 +1316,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 217732.589433 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217442.920009 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270485.675279 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270485.675279 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 217732.589433 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217407.631265 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 217732.589433 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217407.631265 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 225366 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 181222.258105 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 181037.900553 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185505.154973 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185505.154973 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 181222.258105 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 181016.391447 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 181222.258105 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 181016.391447 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 108614 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27560 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16000 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.177286 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.788375 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8822 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8859 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8822 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8862 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1464798862 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1468359862 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23304534090 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23304534090 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1464798862 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1468542862 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1464798862 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1468542862 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8822 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8862 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1138893007 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1142035007 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14240157886 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14240157886 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1138893007 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1142228507 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1138893007 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1142228507 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1375,71 +1378,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165719.975337 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 165430.358495 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218485.469230 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218485.469230 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 165719.975337 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165395.073995 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 165719.975337 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165395.073995 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129096.917592 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 128912.406254 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133504.817802 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133504.817802 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 129096.917592 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 128890.601106 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 129096.917592 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 128890.601106 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 548979 # Transaction distribution -system.membus.trans_dist::ReadResp 548979 # Transaction distribution -system.membus.trans_dist::WriteReq 33870 # Transaction distribution -system.membus.trans_dist::WriteResp 33870 # Transaction distribution -system.membus.trans_dist::Writeback 1485997 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 647215 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 647215 # Transaction distribution -system.membus.trans_dist::UpgradeReq 39795 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 39797 # Transaction distribution -system.membus.trans_dist::ReadExReq 718688 # Transaction distribution -system.membus.trans_dist::ReadExResp 718688 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 553634 # Transaction distribution +system.membus.trans_dist::ReadResp 553634 # Transaction distribution +system.membus.trans_dist::WriteReq 33707 # Transaction distribution +system.membus.trans_dist::WriteResp 33707 # Transaction distribution +system.membus.trans_dist::Writeback 1496537 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 656758 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 656758 # Transaction distribution +system.membus.trans_dist::UpgradeReq 39666 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 39667 # Transaction distribution +system.membus.trans_dist::ReadExReq 717891 # Transaction distribution +system.membus.trans_dist::ReadExResp 717891 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6926 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4994566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5124714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5460180 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5031846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5161506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335307 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335307 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5496813 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13852 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 201253164 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 201424076 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14075072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14075072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 215499148 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2915 # Total snoops (count) -system.membus.snoop_fanout::samples 3354632 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 202791724 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 202962146 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14065984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14065984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 217028130 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3038 # Total snoops (count) +system.membus.snoop_fanout::samples 3378648 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3354632 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3378648 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3354632 # Request fanout histogram -system.membus.reqLayer0.occupancy 113785000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3378648 # Request fanout histogram +system.membus.reqLayer0.occupancy 100002500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5606499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5714500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 21358745741 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 12721299869 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 12484485177 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7256295209 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186617737 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151537359 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1450,11 +1453,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post |