diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt | 2211 |
1 files changed, 1126 insertions, 1085 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 6b3e79c96..d628e39f4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.660643 # Number of seconds simulated -sim_ticks 51660642512000 # Number of ticks simulated -final_tick 51660642512000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.660653 # Number of seconds simulated +sim_ticks 51660652947000 # Number of ticks simulated +final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 304990 # Simulator instruction rate (inst/s) -host_op_rate 358371 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16937149026 # Simulator tick rate (ticks/s) -host_mem_usage 683404 # Number of bytes of host memory used -host_seconds 3050.14 # Real time elapsed on the host -sim_insts 930261902 # Number of instructions simulated -sim_ops 1093080704 # Number of ops (including micro ops) simulated +host_inst_rate 204210 # Simulator instruction rate (inst/s) +host_op_rate 239956 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11350998190 # Simulator tick rate (ticks/s) +host_mem_usage 682908 # Number of bytes of host memory used +host_seconds 4551.20 # Real time elapsed on the host +sim_insts 929398934 # Number of instructions simulated +sim_ops 1092086880 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 377280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 320000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10274880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 61682056 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 384384 # Number of bytes read from this memory -system.physmem.bytes_read::total 73038600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10274880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10274880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 89590976 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 61721352 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 394752 # Number of bytes read from this memory +system.physmem.bytes_read::total 73038088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10229888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10229888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 89631104 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 89611556 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 5895 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5000 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 160545 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 963795 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6006 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1141241 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1399859 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 89651684 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 5915 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4899 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 159842 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 964409 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6168 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1141233 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1400486 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1402432 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 198892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1193985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1413815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 198892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 198892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1734221 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1403059 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 198021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1194746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1413805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 198021 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 198021 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1734998 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1734619 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1734221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 198892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1194384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3148435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1141241 # Number of read requests accepted -system.physmem.writeReqs 1402432 # Number of write requests accepted -system.physmem.readBursts 1141241 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1402432 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 72981760 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 57664 # Total number of bytes read from write queue -system.physmem.bytesWritten 89610624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 73038600 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 89611556 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 901 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1735396 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1734998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 198021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1195144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3149201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1141233 # Number of read requests accepted +system.physmem.writeReqs 1403059 # Number of write requests accepted +system.physmem.readBursts 1141233 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1403059 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 72990656 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 48256 # Total number of bytes read from write queue +system.physmem.bytesWritten 89651072 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 73038088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 89651684 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 754 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 67748 # Per bank write bursts -system.physmem.perBankRdBursts::1 75024 # Per bank write bursts -system.physmem.perBankRdBursts::2 69908 # Per bank write bursts -system.physmem.perBankRdBursts::3 64252 # Per bank write bursts -system.physmem.perBankRdBursts::4 67104 # Per bank write bursts -system.physmem.perBankRdBursts::5 72834 # Per bank write bursts -system.physmem.perBankRdBursts::6 66007 # Per bank write bursts -system.physmem.perBankRdBursts::7 65201 # Per bank write bursts -system.physmem.perBankRdBursts::8 62658 # Per bank write bursts -system.physmem.perBankRdBursts::9 122060 # Per bank write bursts -system.physmem.perBankRdBursts::10 69885 # Per bank write bursts -system.physmem.perBankRdBursts::11 74467 # Per bank write bursts -system.physmem.perBankRdBursts::12 66975 # Per bank write bursts -system.physmem.perBankRdBursts::13 66087 # Per bank write bursts -system.physmem.perBankRdBursts::14 62026 # Per bank write bursts -system.physmem.perBankRdBursts::15 68104 # Per bank write bursts -system.physmem.perBankWrBursts::0 85430 # Per bank write bursts -system.physmem.perBankWrBursts::1 89554 # Per bank write bursts -system.physmem.perBankWrBursts::2 89147 # Per bank write bursts -system.physmem.perBankWrBursts::3 85797 # Per bank write bursts -system.physmem.perBankWrBursts::4 87375 # Per bank write bursts -system.physmem.perBankWrBursts::5 90488 # Per bank write bursts -system.physmem.perBankWrBursts::6 83025 # Per bank write bursts -system.physmem.perBankWrBursts::7 85134 # Per bank write bursts -system.physmem.perBankWrBursts::8 84926 # Per bank write bursts -system.physmem.perBankWrBursts::9 90963 # Per bank write bursts -system.physmem.perBankWrBursts::10 87836 # Per bank write bursts -system.physmem.perBankWrBursts::11 92829 # Per bank write bursts -system.physmem.perBankWrBursts::12 87557 # Per bank write bursts -system.physmem.perBankWrBursts::13 87424 # Per bank write bursts -system.physmem.perBankWrBursts::14 84847 # Per bank write bursts -system.physmem.perBankWrBursts::15 87834 # Per bank write bursts +system.physmem.perBankRdBursts::0 69460 # Per bank write bursts +system.physmem.perBankRdBursts::1 75077 # Per bank write bursts +system.physmem.perBankRdBursts::2 69733 # Per bank write bursts +system.physmem.perBankRdBursts::3 63631 # Per bank write bursts +system.physmem.perBankRdBursts::4 66485 # Per bank write bursts +system.physmem.perBankRdBursts::5 73840 # Per bank write bursts +system.physmem.perBankRdBursts::6 65699 # Per bank write bursts +system.physmem.perBankRdBursts::7 65290 # Per bank write bursts +system.physmem.perBankRdBursts::8 63012 # Per bank write bursts +system.physmem.perBankRdBursts::9 121917 # Per bank write bursts +system.physmem.perBankRdBursts::10 71008 # Per bank write bursts +system.physmem.perBankRdBursts::11 72120 # Per bank write bursts +system.physmem.perBankRdBursts::12 67529 # Per bank write bursts +system.physmem.perBankRdBursts::13 67730 # Per bank write bursts +system.physmem.perBankRdBursts::14 61491 # Per bank write bursts +system.physmem.perBankRdBursts::15 66457 # Per bank write bursts +system.physmem.perBankWrBursts::0 88448 # Per bank write bursts +system.physmem.perBankWrBursts::1 89667 # Per bank write bursts +system.physmem.perBankWrBursts::2 88153 # Per bank write bursts +system.physmem.perBankWrBursts::3 85223 # Per bank write bursts +system.physmem.perBankWrBursts::4 87614 # Per bank write bursts +system.physmem.perBankWrBursts::5 91670 # Per bank write bursts +system.physmem.perBankWrBursts::6 83331 # Per bank write bursts +system.physmem.perBankWrBursts::7 85393 # Per bank write bursts +system.physmem.perBankWrBursts::8 84672 # Per bank write bursts +system.physmem.perBankWrBursts::9 89835 # Per bank write bursts +system.physmem.perBankWrBursts::10 89185 # Per bank write bursts +system.physmem.perBankWrBursts::11 91387 # Per bank write bursts +system.physmem.perBankWrBursts::12 86991 # Per bank write bursts +system.physmem.perBankWrBursts::13 87934 # Per bank write bursts +system.physmem.perBankWrBursts::14 84251 # Per bank write bursts +system.physmem.perBankWrBursts::15 87044 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 50 # Number of times write queue was full causing retry -system.physmem.totGap 51660640624000 # Total gap between requests +system.physmem.numWrRetry 34 # Number of times write queue was full causing retry +system.physmem.totGap 51660651059000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1141226 # Read request sizes (log2) +system.physmem.readPktSize::6 1141218 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1399859 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1072907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 449 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1400486 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1073017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 679 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -159,164 +159,166 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 34167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 78543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 80306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 82649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 80800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 81768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 85658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 85076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 81194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 82459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 85799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 82823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 82988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 84778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 80804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 79640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 79007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 132 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 648089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 250.879123 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.008733 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 285.888919 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 280289 43.25% 43.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 166837 25.74% 68.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 60882 9.39% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 33521 5.17% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 23050 3.56% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16307 2.52% 89.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 11522 1.78% 91.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9570 1.48% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 46111 7.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 648089 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 76765 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.854530 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 142.199486 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 76763 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 34323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 78472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 80418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 82705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 81025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 81933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 85813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 85053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 81235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 82570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 85921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 82664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 82805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 85182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 80817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 79743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 79137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 648791 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 250.683724 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 151.960276 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 285.693480 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 280366 43.21% 43.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 167406 25.80% 69.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 61019 9.41% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 33573 5.17% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23084 3.56% 87.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16255 2.51% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11383 1.75% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9506 1.47% 92.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 46199 7.12% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 648791 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 76825 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.845063 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 142.168306 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 76822 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 76765 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 76765 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.239640 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.683114 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.179019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 64873 84.51% 84.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 9480 12.35% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 455 0.59% 97.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 326 0.42% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 60 0.08% 97.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 114 0.15% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 230 0.30% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 35 0.05% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 294 0.38% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 75 0.10% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 27 0.04% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 50 0.07% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 318 0.41% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 35 0.05% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 31 0.04% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 111 0.14% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 179 0.23% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 5 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 6 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 76825 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 76825 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.233622 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.685886 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.065993 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 64901 84.48% 84.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9488 12.35% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 481 0.63% 97.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 307 0.40% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 57 0.07% 97.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 121 0.16% 98.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 251 0.33% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 28 0.04% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 303 0.39% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 81 0.11% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 29 0.04% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 51 0.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 317 0.41% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 31 0.04% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 27 0.04% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 113 0.15% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 181 0.24% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 5 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 14 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 7 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 8 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 76765 # Writes before turning the bus around for reads -system.physmem.totQLat 16541565713 # Total ticks spent queuing -system.physmem.totMemAccLat 37922940713 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5701700000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14505.82 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 76825 # Writes before turning the bus around for reads +system.physmem.totQLat 16555348236 # Total ticks spent queuing +system.physmem.totMemAccLat 37939329486 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5702395000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14516.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33255.82 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33266.14 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.74 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.41 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.73 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing -system.physmem.readRowHits 872320 # Number of row buffer hits during reads -system.physmem.writeRowHits 1020096 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.85 # Row buffer hit rate for writes -system.physmem.avgGap 20309466.12 # Average gap between requests -system.physmem.pageHitRate 74.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2456674920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1340447625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4274961600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4509756000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3374221858800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1317434781870 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29840739448500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34544977929315 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.690476 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49641970693393 # Time in different power states -system.physmem_0.memoryStateTime::REF 1725062300000 # Time in different power states +system.physmem.avgWrQLen 24.25 # Average write queue length when enqueuing +system.physmem.readRowHits 872195 # Number of row buffer hits during reads +system.physmem.writeRowHits 1020290 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.84 # Row buffer hit rate for writes +system.physmem.avgGap 20304529.14 # Average gap between requests +system.physmem.pageHitRate 74.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2468362680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1346824875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4283830200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4532753520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1318333461255 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29839955813250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34545143413140 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.693578 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49640663734133 # Time in different power states +system.physmem_0.memoryStateTime::REF 1725062560000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 293608746107 # Time in different power states +system.physmem_0.memoryStateTime::ACT 294925880867 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2442877920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1332919500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4619643600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4563319680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3374221858800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1319027164650 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29839342629750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34545550413900 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.701557 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49639611346782 # Time in different power states -system.physmem_1.memoryStateTime::REF 1725062300000 # Time in different power states +system.physmem_1.actEnergy 2436497280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1329438000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4611859200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4544417520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1316960739945 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29841159946500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34545265265805 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.695937 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49642646529009 # Time in different power states +system.physmem_1.memoryStateTime::REF 1725062560000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 295966370718 # Time in different power states +system.physmem_1.memoryStateTime::ACT 292938700991 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -340,15 +342,19 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 254908438 # Number of BP lookups -system.cpu.branchPred.condPredicted 178242351 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12005241 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 187385958 # Number of BTB lookups -system.cpu.branchPred.BTBHits 132827814 # Number of BTB hits +system.cpu.branchPred.lookups 256209592 # Number of BP lookups +system.cpu.branchPred.condPredicted 178352168 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12215343 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 188533609 # Number of BTB lookups +system.cpu.branchPred.BTBHits 127068742 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.884615 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31213174 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2144347 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 67.398456 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31319231 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2132154 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7072039 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 5016643 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2055396 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 841768 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -379,64 +385,63 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 567320 # Table walker walks requested -system.cpu.dtb.walker.walksLong 567320 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20723 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 182198 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 567320 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 567320 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 567320 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 202921 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 27429.733739 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 23186.871186 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 21494.309968 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 200464 98.79% 98.79% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 14 0.01% 98.80% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2073 1.02% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 61 0.03% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 133 0.07% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 52 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 92 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 15 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 561578 # Table walker walks requested +system.cpu.dtb.walker.walksLong 561578 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20867 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 181761 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 561578 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 561578 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 561578 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 202628 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 27245.592909 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 23033.802603 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 21444.921579 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 200160 98.78% 98.78% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.78% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2084 1.03% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 75 0.04% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 137 0.07% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 55 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 85 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 10 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 202921 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 202628 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 182199 89.79% 89.79% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 20723 10.21% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 202922 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 567320 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 181762 89.70% 89.70% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 20867 10.30% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 202629 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 561578 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 567320 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 202922 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 561578 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 202629 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 202922 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 770242 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 202629 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 764207 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 179769202 # DTB read hits -system.cpu.dtb.read_misses 468572 # DTB read misses -system.cpu.dtb.write_hits 159383411 # DTB write hits -system.cpu.dtb.write_misses 98748 # DTB write misses +system.cpu.dtb.read_hits 179568747 # DTB read hits +system.cpu.dtb.read_misses 462708 # DTB read misses +system.cpu.dtb.write_hits 159223685 # DTB write hits +system.cpu.dtb.write_misses 98870 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 45817 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 78846 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15815 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 78994 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14910 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23199 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 180237774 # DTB read accesses -system.cpu.dtb.write_accesses 159482159 # DTB write accesses +system.cpu.dtb.perms_faults 23300 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 180031455 # DTB read accesses +system.cpu.dtb.write_accesses 159322555 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 339152613 # DTB hits -system.cpu.dtb.misses 567320 # DTB misses -system.cpu.dtb.accesses 339719933 # DTB accesses +system.cpu.dtb.hits 338792432 # DTB hits +system.cpu.dtb.misses 561578 # DTB misses +system.cpu.dtb.accesses 339354010 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -466,184 +471,219 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 135719 # Table walker walks requested -system.cpu.itb.walker.walksLong 135719 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1067 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 118398 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 135719 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 135719 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 135719 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 119465 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 30823.412715 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 26220.565528 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24055.511247 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 116639 97.63% 97.63% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 7 0.01% 97.64% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 2565 2.15% 99.79% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 80 0.07% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 132 0.11% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 26 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 13 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 133823 # Table walker walks requested +system.cpu.itb.walker.walksLong 133823 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1057 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 116932 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 133823 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 133823 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 133823 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 117989 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 30581.308427 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 25983.502451 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24251.357512 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 115208 97.64% 97.64% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 3 0.00% 97.65% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 2538 2.15% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 65 0.06% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 122 0.10% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 30 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 18 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 119465 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 117989 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 118398 99.11% 99.11% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1067 0.89% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 119465 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 116932 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1057 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 117989 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135719 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 135719 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 133823 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 133823 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119465 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 119465 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 255184 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 443155891 # ITB inst hits -system.cpu.itb.inst_misses 135719 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 117989 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 117989 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 251812 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 442793055 # ITB inst hits +system.cpu.itb.inst_misses 133823 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 45817 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 56716 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 56590 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 363456 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 313131 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 443291610 # ITB inst accesses -system.cpu.itb.hits 443155891 # DTB hits -system.cpu.itb.misses 135719 # DTB misses -system.cpu.itb.accesses 443291610 # DTB accesses -system.cpu.numCycles 2560430377 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 442926878 # ITB inst accesses +system.cpu.itb.hits 442793055 # DTB hits +system.cpu.itb.misses 133823 # DTB misses +system.cpu.itb.accesses 442926878 # DTB accesses +system.cpu.numCycles 2561963341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 930261902 # Number of instructions committed -system.cpu.committedOps 1093080704 # Number of ops (including micro ops) committed -system.cpu.discardedOps 94082781 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7654 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100762000477 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.752376 # CPI: cycles per instruction -system.cpu.ipc 0.363322 # IPC: instructions per cycle +system.cpu.committedInsts 929398934 # Number of instructions committed +system.cpu.committedOps 1092086880 # Number of ops (including micro ops) committed +system.cpu.discardedOps 94664249 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7656 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100760459460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.756581 # CPI: cycles per instruction +system.cpu.ipc 0.362768 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 756821893 69.30% 69.30% # Class of committed instruction +system.cpu.op_class_0::IntMult 2277263 0.21% 69.51% # Class of committed instruction +system.cpu.op_class_0::IntDiv 98455 0.01% 69.52% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 109444 0.01% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::MemRead 174118935 15.94% 85.47% # Class of committed instruction +system.cpu.op_class_0::MemWrite 158660847 14.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 1092086880 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16514 # number of quiesce instructions executed -system.cpu.tickCycles 1756892100 # Number of cycles that the object actually ticked -system.cpu.idleCycles 803538277 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 10835760 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.930073 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 323161698 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10836272 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.822221 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 16516 # number of quiesce instructions executed +system.cpu.tickCycles 1757425284 # Number of cycles that the object actually ticked +system.cpu.idleCycles 804538057 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 10826762 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.930071 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322795140 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10827274 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.813150 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.930073 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.930071 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1357625936 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1357625936 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 165326360 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 165326360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148822242 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148822242 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 515783 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 515783 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336254 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336254 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3901835 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3901835 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4210707 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4210707 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 314148602 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 314148602 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 314664385 # number of overall hits -system.cpu.dcache.overall_hits::total 314664385 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6435963 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6435963 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4178110 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4178110 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1419320 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1419320 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1240241 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1240241 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 310588 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 310588 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 10614073 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10614073 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12033393 # number of overall misses -system.cpu.dcache.overall_misses::total 12033393 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 119289543000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 119289543000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 206542043000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 206542043000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53400604000 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 53400604000 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5170357500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5170357500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 245500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 245500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 325831586000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 325831586000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 325831586000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 325831586000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 171762323 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 171762323 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 153000352 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 153000352 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1935103 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1935103 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1576495 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1576495 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4212423 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4212423 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4210710 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4210710 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 324762675 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 324762675 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 326697778 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 326697778 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037470 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037470 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027308 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027308 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733460 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.733460 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786708 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786708 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073731 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073731 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032683 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032683 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036833 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036833 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18534.839775 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18534.839775 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49434.323893 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49434.323893 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43056.634960 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43056.634960 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16646.996986 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16646.996986 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 81833.333333 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 81833.333333 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30698.072832 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30698.072832 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27077.282858 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27077.282858 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 1356106386 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1356106386 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 165131668 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 165131668 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148654336 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148654336 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 515490 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 515490 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 336587 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 336587 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3899601 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3899601 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4208890 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4208890 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 313786004 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 313786004 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 314301494 # number of overall hits +system.cpu.dcache.overall_hits::total 314301494 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6423881 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6423881 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4177328 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4177328 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1420881 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1420881 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1240100 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1240100 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 311002 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 311002 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 10601209 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10601209 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12022090 # number of overall misses +system.cpu.dcache.overall_misses::total 12022090 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 119203222500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 119203222500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 206322817500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 206322817500 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53471775500 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 53471775500 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5200645500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5200645500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 325526040000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 325526040000 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4210603 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4208892 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4208892 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 324387213 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 324387213 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 326323584 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 326323584 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037445 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037445 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027333 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027333 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733786 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.733786 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786523 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786523 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073862 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073862 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032681 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032681 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036841 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036841 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18556.262562 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18556.262562 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49391.098209 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49391.098209 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43118.922264 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43118.922264 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16722.225259 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16722.225259 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30706.501494 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30706.501494 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27077.325157 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27077.325157 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -652,155 +692,155 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8326510 # number of writebacks -system.cpu.dcache.writebacks::total 8326510 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 781266 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 781266 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1841490 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1841490 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 148 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 148 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69021 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 69021 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2622756 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2622756 # 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number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1841560 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 166 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 166 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69564 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 69564 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2620111 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2620111 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2620111 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2620111 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5645330 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5645330 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2335768 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2335768 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1413353 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1413353 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1239934 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1239934 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241438 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 241438 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7981098 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7981098 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9394451 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9394451 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97635804500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 97635804500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109449194500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 109449194500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26743318000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26743318000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52153246000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52153246000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3514198000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3514198000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 242500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 242500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207084999000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 207084999000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 233828317000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 233828317000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197367000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197367000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207571500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207571500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12404938500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 12404938500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032922 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032922 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015272 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015272 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729568 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729568 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786614 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786614 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057346 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057346 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024607 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024607 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028782 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17266.319398 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17266.319398 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46840.819004 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46840.819004 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18942.857608 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18942.857608 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42055.915161 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42055.915161 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14547.508559 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14547.508559 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80833.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80833.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25913.751013 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25913.751013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24867.136136 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24867.136136 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183914.502775 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183914.502775 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184168.145137 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184168.145137 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184041.340890 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184041.340890 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97557432500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 97557432500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109336281500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 109336281500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26901290500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26901290500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52221764000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52221764000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3529658500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3529658500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206893714000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 206893714000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 233795004500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 233795004500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197628500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197628500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6191865500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6191865500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12389494000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12389494000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032907 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032907 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015283 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015283 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729898 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729898 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786417 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786417 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057340 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057340 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024604 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024604 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17281.085871 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17281.085871 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46809.563921 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46809.563921 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19033.667102 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19033.667102 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42116.567495 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42116.567495 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14619.316346 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14619.316346 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25922.963733 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25922.963733 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24886.499967 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24886.499967 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 183702.174687 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183702.174687 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 183812.204205 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 183812.204205 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24282731 # number of replacements -system.cpu.icache.tags.tagsinuse 511.885324 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 418496927 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24283243 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.233980 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 32778398500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.885324 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 24339101 # number of replacements +system.cpu.icache.tags.tagsinuse 511.885333 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 418129059 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24339613 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.178953 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 32773385500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.885333 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 467063432 # Number of tag accesses -system.cpu.icache.tags.data_accesses 467063432 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 418496927 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 418496927 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 418496927 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 418496927 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 418496927 # number of overall hits -system.cpu.icache.overall_hits::total 418496927 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24283253 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24283253 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24283253 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24283253 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24283253 # number of overall misses -system.cpu.icache.overall_misses::total 24283253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 329126236000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 329126236000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 329126236000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 329126236000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 329126236000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 329126236000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 442780180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 442780180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 442780180 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 442780180 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 442780180 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 442780180 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054843 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.054843 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.054843 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.054843 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.054843 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.054843 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5471 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54751 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003494 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963974 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 576746891 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 576746891 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 934890 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 285217 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1220107 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8326510 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8326510 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 24279004 # 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average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69662.957429 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69662.957429 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122519.268728 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123503.885757 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123442.045334 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122519.268728 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123503.885757 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123442.045334 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.281473 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.281473 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004419 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044081 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044081 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.433198 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.433198 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.100722 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030853 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.100722 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030853 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127272.008692 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68013.417428 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68013.417428 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122748.217880 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122748.217880 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122464.475999 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122464.475999 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125035.706823 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125035.706823 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69662.462277 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69662.462277 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122464.475999 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123510.470995 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123444.210366 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122464.475999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123510.470995 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123444.210366 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171412.648010 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136178.475920 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172650.477660 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172650.477660 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171419.592249 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136181.196661 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172180.427817 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172180.427817 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172031.645476 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146447.498998 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 171800.060828 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146317.106890 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 70987580 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 35868028 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4400 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2259 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 71082854 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 35915919 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1747427 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33339280 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1731601 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33371848 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 9726418 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24282731 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2753122 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 48457 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 48460 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2288395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2288395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24283253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7316706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1346757 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1240093 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72953851 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32740884 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 695726 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2196697 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 108587158 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3111570496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1147294802 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2321736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7526280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4268713314 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2190531 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 38708484 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018284 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.133976 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 9712830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24339101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2759131 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 48504 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 48506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2287534 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2287534 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24339623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7308730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1346598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1239934 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73122960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32713992 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 682590 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2171018 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 108690560 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3118785792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1145820498 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2260056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7404048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4274270394 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2199102 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 38741497 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018274 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.133941 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 38000745 98.17% 98.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 707739 1.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 38033532 98.17% 98.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 707965 1.83% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 38708484 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 68659919994 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 38741497 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 68741576495 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1469394 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1462889 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36510728693 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36594790182 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15090009225 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15076717704 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 405546924 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 400149367 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1255965393 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1245546930 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40330 # Transaction distribution -system.iobus.trans_dist::ReadResp 40330 # Transaction distribution +system.iobus.trans_dist::ReadReq 40324 # Transaction distribution +system.iobus.trans_dist::ReadResp 40324 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1256,11 +1297,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231018 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231018 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353802 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1275,100 +1316,100 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334504 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334504 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492424 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42214500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37107000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 333500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25698500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25573000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34147500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34140500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 566993946 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567103107 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147778000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115490 # number of replacements +system.iocache.tags.replacements 115484 # number of replacements system.iocache.tags.tagsinuse 10.441254 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115506 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153331095000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.521304 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.919950 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220081 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13153318095000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.521307 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.919947 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220082 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.432497 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.652578 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039938 # Number of tag accesses -system.iocache.tags.data_accesses 1039938 # Number of data accesses +system.iocache.tags.tag_accesses 1039884 # Number of tag accesses +system.iocache.tags.data_accesses 1039884 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8845 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8882 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8845 # number of demand (read+write) misses -system.iocache.demand_misses::total 8885 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses +system.iocache.demand_misses::total 8879 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8845 # number of overall misses -system.iocache.overall_misses::total 8885 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1624796190 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1629882190 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8839 # number of overall misses +system.iocache.overall_misses::total 8879 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1644126101 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1649196101 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13412464756 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13412464756 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1624796190 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1630233190 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1624796190 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1630233190 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13411893006 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13411893006 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1644126101 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1649547101 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1644126101 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1649547101 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8845 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8882 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8845 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8885 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8845 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8885 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1382,55 +1423,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183696.573205 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183503.961946 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186008.157144 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 185803.977129 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125745.000713 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125745.000713 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 183696.573205 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183481.507034 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 183696.573205 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183481.507034 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31904 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.640422 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125739.640422 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 186008.157144 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 185780.729925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 186008.157144 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 185780.729925 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32855 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3290 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3383 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.697264 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.711794 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8845 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8882 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8845 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8885 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8845 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8885 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1182546190 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1185782190 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1202176101 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1205396101 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8074127324 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8074127324 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1182546190 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1185983190 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1182546190 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1185983190 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073547861 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8073547861 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1202176101 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1205597101 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1202176101 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1205597101 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1444,72 +1485,72 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133696.573205 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133503.961946 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136008.157144 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 135803.977129 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75696.836083 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75696.836083 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 133696.573205 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 133481.507034 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 133696.573205 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 133481.507034 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.403482 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.403482 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136008.157144 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 135780.729925 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136008.157144 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 135780.729925 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 86006 # Transaction distribution -system.membus.trans_dist::ReadResp 534352 # Transaction distribution +system.membus.trans_dist::ReadResp 535040 # Transaction distribution system.membus.trans_dist::WriteReq 33706 # Transaction distribution system.membus.trans_dist::WriteResp 33706 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1399859 # Transaction distribution -system.membus.trans_dist::CleanEvict 242769 # Transaction distribution -system.membus.trans_dist::UpgradeReq 38707 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1400486 # Transaction distribution +system.membus.trans_dist::CleanEvict 243574 # Transaction distribution +system.membus.trans_dist::UpgradeReq 38729 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 644117 # Transaction distribution -system.membus.trans_dist::ReadExResp 644117 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448346 # Transaction distribution -system.membus.trans_dist::InvalidateReq 642566 # Transaction distribution +system.membus.trans_dist::ReadExReq 643252 # Transaction distribution +system.membus.trans_dist::ReadExResp 643252 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 449034 # Transaction distribution +system.membus.trans_dist::InvalidateReq 643674 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4378022 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4507674 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237045 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237045 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4744719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4380248 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4509900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237195 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237195 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4747095 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155441452 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 155611858 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7208704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7208704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 162820562 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3543 # Total snoops (count) -system.membus.snoop_fanout::samples 3536130 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155470700 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 155641106 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7219072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7219072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 162860178 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3374 # Total snoops (count) +system.membus.snoop_fanout::samples 3538498 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3536130 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3538498 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3536130 # Request fanout histogram -system.membus.reqLayer0.occupancy 102490000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3538498 # Request fanout histogram +system.membus.reqLayer0.occupancy 97241000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5501500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5639000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9311720798 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9317752261 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6129482304 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6128850630 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44955070 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44857615 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks |