diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt | 2398 |
1 files changed, 1200 insertions, 1198 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index c77078f22..1319d3c2e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.687765 # Number of seconds simulated -sim_ticks 51687764518000 # Number of ticks simulated -final_tick 51687764518000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.688775 # Number of seconds simulated +sim_ticks 51688774990000 # Number of ticks simulated +final_tick 51688774990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151884 # Simulator instruction rate (inst/s) -host_op_rate 178474 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8204277049 # Simulator tick rate (ticks/s) -host_mem_usage 687220 # Number of bytes of host memory used -host_seconds 6300.10 # Real time elapsed on the host -sim_insts 956884636 # Number of instructions simulated -sim_ops 1124405089 # Number of ops (including micro ops) simulated +host_inst_rate 210815 # Simulator instruction rate (inst/s) +host_op_rate 247704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11507504763 # Simulator tick rate (ticks/s) +host_mem_usage 684036 # Number of bytes of host memory used +host_seconds 4491.74 # Real time elapsed on the host +sim_insts 946928269 # Number of instructions simulated +sim_ops 1112623169 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 423488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 359680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10197440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 68348040 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 416768 # Number of bytes read from this memory -system.physmem.bytes_read::total 79745416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10197440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10197440 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 96812416 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 401472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 331520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10196544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 65400968 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 425152 # Number of bytes read from this memory +system.physmem.bytes_read::total 76755656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10196544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10196544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 93615936 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 96832996 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6617 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5620 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 159335 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1067951 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6512 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1246035 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1512694 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 93636516 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5180 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 159321 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1021903 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6643 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1199320 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1462749 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1515267 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 8193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6959 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 197289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1322325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1542830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1873024 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1465322 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 197268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1265284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1484958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197268 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197268 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1811146 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1873422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1873024 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 8193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1322723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3416252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1246035 # Number of read requests accepted -system.physmem.writeReqs 1515267 # Number of write requests accepted -system.physmem.readBursts 1246035 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1515267 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 79703040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 43200 # Total number of bytes read from write queue -system.physmem.bytesWritten 96830656 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 79745416 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 96832996 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 675 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2258 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1811544 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1811146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1265682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3296502 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1199320 # Number of read requests accepted +system.physmem.writeReqs 1465322 # Number of write requests accepted +system.physmem.readBursts 1199320 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1465322 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 76712512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 43968 # Total number of bytes read from write queue +system.physmem.bytesWritten 93634496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 76755656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 93636516 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 687 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 74796 # Per bank write bursts -system.physmem.perBankRdBursts::1 76131 # Per bank write bursts -system.physmem.perBankRdBursts::2 70862 # Per bank write bursts -system.physmem.perBankRdBursts::3 68837 # Per bank write bursts -system.physmem.perBankRdBursts::4 72123 # Per bank write bursts -system.physmem.perBankRdBursts::5 84628 # Per bank write bursts -system.physmem.perBankRdBursts::6 78694 # Per bank write bursts -system.physmem.perBankRdBursts::7 74893 # Per bank write bursts -system.physmem.perBankRdBursts::8 72007 # Per bank write bursts -system.physmem.perBankRdBursts::9 129561 # Per bank write bursts -system.physmem.perBankRdBursts::10 74825 # Per bank write bursts -system.physmem.perBankRdBursts::11 74032 # Per bank write bursts -system.physmem.perBankRdBursts::12 72055 # Per bank write bursts -system.physmem.perBankRdBursts::13 77727 # Per bank write bursts -system.physmem.perBankRdBursts::14 71057 # Per bank write bursts -system.physmem.perBankRdBursts::15 73132 # Per bank write bursts -system.physmem.perBankWrBursts::0 93267 # Per bank write bursts -system.physmem.perBankWrBursts::1 94026 # Per bank write bursts -system.physmem.perBankWrBursts::2 93600 # Per bank write bursts -system.physmem.perBankWrBursts::3 92665 # Per bank write bursts -system.physmem.perBankWrBursts::4 94539 # Per bank write bursts -system.physmem.perBankWrBursts::5 102396 # Per bank write bursts -system.physmem.perBankWrBursts::6 95600 # Per bank write bursts -system.physmem.perBankWrBursts::7 94740 # Per bank write bursts -system.physmem.perBankWrBursts::8 92115 # Per bank write bursts -system.physmem.perBankWrBursts::9 99710 # Per bank write bursts -system.physmem.perBankWrBursts::10 92671 # Per bank write bursts -system.physmem.perBankWrBursts::11 94633 # Per bank write bursts -system.physmem.perBankWrBursts::12 92127 # Per bank write bursts -system.physmem.perBankWrBursts::13 95527 # Per bank write bursts -system.physmem.perBankWrBursts::14 92160 # Per bank write bursts -system.physmem.perBankWrBursts::15 93203 # Per bank write bursts +system.physmem.perBankRdBursts::0 70144 # Per bank write bursts +system.physmem.perBankRdBursts::1 74650 # Per bank write bursts +system.physmem.perBankRdBursts::2 68418 # Per bank write bursts +system.physmem.perBankRdBursts::3 68145 # Per bank write bursts +system.physmem.perBankRdBursts::4 72367 # Per bank write bursts +system.physmem.perBankRdBursts::5 76479 # Per bank write bursts +system.physmem.perBankRdBursts::6 68140 # Per bank write bursts +system.physmem.perBankRdBursts::7 71247 # Per bank write bursts +system.physmem.perBankRdBursts::8 66581 # Per bank write bursts +system.physmem.perBankRdBursts::9 125666 # Per bank write bursts +system.physmem.perBankRdBursts::10 74635 # Per bank write bursts +system.physmem.perBankRdBursts::11 76739 # Per bank write bursts +system.physmem.perBankRdBursts::12 72169 # Per bank write bursts +system.physmem.perBankRdBursts::13 75530 # Per bank write bursts +system.physmem.perBankRdBursts::14 66172 # Per bank write bursts +system.physmem.perBankRdBursts::15 71551 # Per bank write bursts +system.physmem.perBankWrBursts::0 89120 # Per bank write bursts +system.physmem.perBankWrBursts::1 91694 # Per bank write bursts +system.physmem.perBankWrBursts::2 88427 # Per bank write bursts +system.physmem.perBankWrBursts::3 87889 # Per bank write bursts +system.physmem.perBankWrBursts::4 92386 # Per bank write bursts +system.physmem.perBankWrBursts::5 94711 # Per bank write bursts +system.physmem.perBankWrBursts::6 88472 # Per bank write bursts +system.physmem.perBankWrBursts::7 91239 # Per bank write bursts +system.physmem.perBankWrBursts::8 88274 # Per bank write bursts +system.physmem.perBankWrBursts::9 94990 # Per bank write bursts +system.physmem.perBankWrBursts::10 92874 # Per bank write bursts +system.physmem.perBankWrBursts::11 94799 # Per bank write bursts +system.physmem.perBankWrBursts::12 93039 # Per bank write bursts +system.physmem.perBankWrBursts::13 95949 # Per bank write bursts +system.physmem.perBankWrBursts::14 87664 # Per bank write bursts +system.physmem.perBankWrBursts::15 91512 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 51687762664000 # Total gap between requests +system.physmem.numWrRetry 468 # Number of times write queue was full causing retry +system.physmem.totGap 51688773130000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1246020 # Read request sizes (log2) +system.physmem.readPktSize::6 1199305 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1512694 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1180646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 58552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1462749 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1127245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 509 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -160,173 +160,184 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 83104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 89526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 91633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 87574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 93055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 92225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 93220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 90182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 92806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 94606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 92258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 89036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 87252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 83915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 83414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 82380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 106 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 686907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 256.997398 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.492038 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 292.459663 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 294027 42.80% 42.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 175466 25.54% 68.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 64376 9.37% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35669 5.19% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24767 3.61% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16380 2.38% 88.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 12324 1.79% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 10264 1.49% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 53634 7.81% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 686907 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 80666 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.437595 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 138.740748 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 80664 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 29655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 37473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 78822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 84952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 87044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 83743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 88388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 87662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 88784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 85626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 88571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 89853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 87229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 84323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 82904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 81964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 79861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 79771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1066 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 662940 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 256.956322 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 154.084684 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 293.850288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 284383 42.90% 42.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 170705 25.75% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 61081 9.21% 77.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 33561 5.06% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23575 3.56% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15515 2.34% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11286 1.70% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9362 1.41% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 53472 8.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 662940 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 77129 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.540445 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 141.912078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 77126 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 80666 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 80666 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.756093 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.057108 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.363487 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 67894 84.17% 84.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 3915 4.85% 89.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 3350 4.15% 93.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 2485 3.08% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1103 1.37% 97.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 521 0.65% 98.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 244 0.30% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 153 0.19% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 79 0.10% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 83 0.10% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 83 0.10% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 89 0.11% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 450 0.56% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 43 0.05% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 41 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 30 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 23 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 5 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 9 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 18 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 80666 # Writes before turning the bus around for reads -system.physmem.totQLat 17151209707 # Total ticks spent queuing -system.physmem.totMemAccLat 40501709707 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6226800000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13772.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 77129 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 77129 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.968728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.139558 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.416384 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 64621 83.78% 83.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 3761 4.88% 88.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 3195 4.14% 92.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 2420 3.14% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1145 1.48% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 346 0.45% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 199 0.26% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 173 0.22% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 112 0.15% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 62 0.08% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 79 0.10% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 69 0.09% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 561 0.73% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 77 0.10% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 111 0.14% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 54 0.07% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 32 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.00% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 13 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 7 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 12 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 12 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 77129 # Writes before turning the bus around for reads +system.physmem.totQLat 38956691672 # Total ticks spent queuing +system.physmem.totMemAccLat 61431060422 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5993165000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32500.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32522.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.54 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.54 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51250.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.30 # Average write queue length when enqueuing -system.physmem.readRowHits 964137 # Number of row buffer hits during reads -system.physmem.writeRowHits 1107294 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.18 # Row buffer hit rate for writes -system.physmem.avgGap 18718619.94 # Average gap between requests -system.physmem.pageHitRate 75.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2629783800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1434901875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4687519200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4930197840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3375993173280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1305935149860 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29867098550250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34562709276105 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.682675 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49685845654409 # Time in different power states -system.physmem_0.memoryStateTime::REF 1725967880000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 275945978091 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2563233120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1398589500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5026242000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4873906080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3375993173280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1305717731910 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29867289276000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34562862151890 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.685632 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49686132095770 # Time in different power states -system.physmem_1.memoryStateTime::REF 1725967880000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 275664064230 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing +system.physmem.readRowHits 929087 # Number of row buffer hits during reads +system.physmem.writeRowHits 1069644 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.11 # Row buffer hit rate for writes +system.physmem.avgGap 19398017.87 # Average gap between requests +system.physmem.pageHitRate 75.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2341677240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1244627175 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4066872600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3778956360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50725624560.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 43528474080 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3238135680 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 96319832910 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 74142648000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12293580495315 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12572988857670 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.244086 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51584838283234 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 6009063000 # Time in different power states +system.physmem_0.memoryStateTime::REF 21570724000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51180529926500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 193079953190 # Time in different power states +system.physmem_0.memoryStateTime::ACT 76356875016 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 211228448294 # Time in different power states +system.physmem_1.actEnergy 2391721500 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1271230125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4491367020 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3858107220 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 51763751520.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 44789626440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3183541920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 99591324540 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 75005755680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12290774240265 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12577142748300 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.324450 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51582206485554 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5783812250 # Time in different power states +system.physmem_1.memoryStateTime::REF 22010710000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51168482999000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 195327455894 # Time in different power states +system.physmem_1.memoryStateTime::ACT 78768252696 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 218401760160 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory @@ -343,30 +354,30 @@ system.realview.nvmem.bw_inst_read::total 14 # I system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 264432116 # Number of BP lookups -system.cpu.branchPred.condPredicted 184777930 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12360480 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 195121872 # Number of BTB lookups -system.cpu.branchPred.BTBHits 131792442 # Number of BTB hits +system.cpu.branchPred.lookups 261505306 # Number of BP lookups +system.cpu.branchPred.condPredicted 182498706 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12291836 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 192874347 # Number of BTB lookups +system.cpu.branchPred.BTBHits 130159045 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 67.543654 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 32005520 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2166164 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7202634 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 5156312 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2046322 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 848562 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 67.483855 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31722667 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2144910 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7175659 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 5109497 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2066162 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 844099 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -396,70 +407,65 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 584775 # Table walker walks requested -system.cpu.dtb.walker.walksLong 584775 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 23234 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 194431 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 584775 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 584775 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 584775 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 217665 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 25428.727632 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21638.505013 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 16299.176879 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 136227 62.59% 62.59% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 78767 36.19% 98.77% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 1401 0.64% 99.42% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 854 0.39% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 27 0.01% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 133 0.06% 99.88% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-229375 57 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::229376-262143 75 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 47 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 26 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 20 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::360448-393215 15 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-425983 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 217665 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -10206296 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -10206296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -10206296 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 194432 89.33% 89.33% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 23234 10.67% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 217666 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 584775 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 574319 # Table walker walks requested +system.cpu.dtb.walker.walksLong 574319 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21733 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 190269 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 574319 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 574319 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 574319 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 212002 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 25745.962302 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21834.815515 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 18121.324193 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 209468 98.80% 98.80% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 2131 1.01% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 103 0.05% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 132 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 91 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 12 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 29 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 212002 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 316311704 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 316311704 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 316311704 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 190270 89.75% 89.75% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 21733 10.25% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 212003 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 574319 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 584775 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 217666 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 574319 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 212003 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 217666 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 802441 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 212003 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 786322 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 184602893 # DTB read hits -system.cpu.dtb.read_misses 481054 # DTB read misses -system.cpu.dtb.write_hits 163948315 # DTB write hits -system.cpu.dtb.write_misses 103721 # DTB write misses +system.cpu.dtb.read_hits 182769858 # DTB read hits +system.cpu.dtb.read_misses 473161 # DTB read misses +system.cpu.dtb.write_hits 162201881 # DTB write hits +system.cpu.dtb.write_misses 101158 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47766 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1117 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 80755 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1436 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15519 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 47051 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 79796 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1477 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 15505 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23435 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 185083947 # DTB read accesses -system.cpu.dtb.write_accesses 164052036 # DTB write accesses +system.cpu.dtb.perms_faults 23270 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 183243019 # DTB read accesses +system.cpu.dtb.write_accesses 162303039 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 348551208 # DTB hits -system.cpu.dtb.misses 584775 # DTB misses -system.cpu.dtb.accesses 349135983 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 344971739 # DTB hits +system.cpu.dtb.misses 574319 # DTB misses +system.cpu.dtb.accesses 345546058 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -489,72 +495,70 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 136740 # Table walker walks requested -system.cpu.itb.walker.walksLong 136740 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1077 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 118526 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 136740 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 136740 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 136740 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 119603 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 27883.393393 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23898.853743 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 18564.311346 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-32767 67731 56.63% 56.63% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-65535 48774 40.78% 97.41% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-98303 1154 0.96% 98.37% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::98304-131071 1639 1.37% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-163839 37 0.03% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::163840-196607 137 0.11% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::229376-262143 18 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-294911 21 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::294912-327679 20 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-360447 18 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::360448-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 119603 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -10844796 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -10844796 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -10844796 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 118526 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1077 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 119603 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 135751 # Table walker walks requested +system.cpu.itb.walker.walksLong 135751 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1056 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 117755 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 135751 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 135751 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 135751 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 118811 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28810.606762 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24143.293111 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 28291.561253 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 115975 97.61% 97.61% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2399 2.02% 99.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 123 0.10% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 44 0.04% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 141 0.12% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 118811 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 315425204 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 315425204 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 315425204 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 117755 99.11% 99.11% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1056 0.89% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 118811 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136740 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 136740 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135751 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 135751 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119603 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 119603 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 256343 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 457894474 # ITB inst hits -system.cpu.itb.inst_misses 136740 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118811 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 118811 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 254562 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 452655900 # ITB inst hits +system.cpu.itb.inst_misses 135751 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47766 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1117 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57885 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 47051 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 57242 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 331252 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 322846 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 458031214 # ITB inst accesses -system.cpu.itb.hits 457894474 # DTB hits -system.cpu.itb.misses 136740 # DTB misses -system.cpu.itb.accesses 458031214 # DTB accesses -system.cpu.numPwrStateTransitions 33262 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16631 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3032078673.597498 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59558384510.943253 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7336 44.11% 44.11% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9260 55.68% 99.79% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 452791651 # ITB inst accesses +system.cpu.itb.hits 452655900 # DTB hits +system.cpu.itb.misses 135751 # DTB misses +system.cpu.itb.accesses 452791651 # DTB accesses +system.cpu.numPwrStateTransitions 33180 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16590 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3039388324.246233 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59640903157.908096 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7293 43.96% 43.96% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9262 55.83% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state @@ -567,23 +571,23 @@ system.cpu.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.89% system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988777698120 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16631 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1261264097400 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50426500420600 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2522582223 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 16590 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1265322690755 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50423452299245 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2530699433 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 956884636 # Number of instructions committed -system.cpu.committedOps 1124405089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 99545013 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7771 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100854059486 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.636245 # CPI: cycles per instruction -system.cpu.ipc 0.379327 # IPC: instructions per cycle +system.cpu.committedInsts 946928269 # Number of instructions committed +system.cpu.committedOps 1112623169 # Number of ops (including micro ops) committed +system.cpu.discardedOps 97851669 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7730 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100847957157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.672536 # CPI: cycles per instruction +system.cpu.ipc 0.374177 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 779381648 69.32% 69.32% # Class of committed instruction -system.cpu.op_class_0::IntMult 2317785 0.21% 69.52% # Class of committed instruction -system.cpu.op_class_0::IntDiv 99593 0.01% 69.53% # Class of committed instruction +system.cpu.op_class_0::IntAlu 771151081 69.31% 69.31% # Class of committed instruction +system.cpu.op_class_0::IntMult 2302642 0.21% 69.52% # Class of committed instruction +system.cpu.op_class_0::IntDiv 99189 0.01% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction @@ -606,522 +610,520 @@ system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Cl system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.53% # Class of committed instruction system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 108729 0.01% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::MemRead 179105650 15.93% 85.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 163391641 14.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 108989 0.01% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::MemRead 177312606 15.94% 85.47% # Class of committed instruction +system.cpu.op_class_0::MemWrite 161648619 14.53% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 1124405089 # Class of committed instruction +system.cpu.op_class_0::total 1112623169 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16631 # number of quiesce instructions executed -system.cpu.tickCycles 1810679239 # Number of cycles that the object actually ticked -system.cpu.idleCycles 711902984 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11237287 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.957340 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 332608189 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11237799 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.597272 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4326295500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.957340 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16590 # number of quiesce instructions executed +system.cpu.tickCycles 1791525295 # Number of cycles that the object actually ticked +system.cpu.idleCycles 739174138 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 11091024 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.954083 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 329234475 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11091536 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.683398 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4655908500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.954083 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1395920077 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1395920077 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 170244902 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 170244902 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 153016106 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 153016106 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 525044 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 525044 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336678 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336678 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4066137 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4066137 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4385244 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4385244 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 323597686 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 323597686 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 324122730 # number of overall hits -system.cpu.dcache.overall_hits::total 324122730 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6163054 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6163054 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4362358 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4362358 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1504058 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1504058 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1246141 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1246141 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 320841 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 320841 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1381544711 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1381544711 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 168600534 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 168600534 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 151416750 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 151416750 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 521238 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 521238 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 337307 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 337307 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4005998 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4005998 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4318996 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4318996 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 320354591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 320354591 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 320875829 # number of overall hits +system.cpu.dcache.overall_hits::total 320875829 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6093036 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6093036 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4287792 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4287792 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1473735 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1473735 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1243168 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1243168 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 314729 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 314729 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 11771553 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11771553 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 13275611 # number of overall misses -system.cpu.dcache.overall_misses::total 13275611 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 101076172500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 101076172500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157713428000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157713428000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27433825500 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 27433825500 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4889648000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4889648000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 11623996 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 11623996 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 13097731 # number of overall misses +system.cpu.dcache.overall_misses::total 13097731 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 107249746000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 107249746000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 169106972500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 169106972500 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27289591000 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 27289591000 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5063641000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5063641000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 286223426000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 286223426000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 286223426000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 286223426000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 176407956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 176407956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 157378464 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 157378464 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2029102 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2029102 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1582819 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1582819 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4386978 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4386978 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4385245 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4385245 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 335369239 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 335369239 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 337398341 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 337398341 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034936 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.034936 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027719 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027719 # 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number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3424677000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3424677000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 94763834000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 94763834000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88482137000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 88482137000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 25605238500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 25605238500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26041674000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26041674000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3459340500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3459340500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 197537687000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 197537687000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221752800000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 221752800000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6231251500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6231251500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6231251500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6231251500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033149 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033149 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.737534 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.737534 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787195 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787195 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056967 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056967 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 209287645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 209287645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 234892883500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 234892883500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6231136500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6231136500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6231136500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6231136500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033098 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033098 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015350 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015350 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.734983 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.734983 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786483 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786483 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056435 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056435 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028403 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028403 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032668 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032668 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15226.468489 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15226.468489 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33849.714876 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33849.714876 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16180.829532 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16180.829532 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21014.349668 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21014.349668 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13703.531643 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13703.531643 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028361 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028361 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032582 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032582 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16389.472905 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16389.472905 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37020.265679 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37020.265679 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17462.828154 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17462.828154 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 20950.393237 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 20950.393237 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14186.927904 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14186.927904 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20737.885034 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20737.885034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20119.141922 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20119.141922 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184914.579500 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184914.579500 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92444.944737 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92444.944737 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 24740790 # number of replacements -system.cpu.icache.tags.tagsinuse 511.930482 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 432810859 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24741302 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.493455 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20587192500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.930482 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999864 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22228.911293 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22228.911293 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21586.679439 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21586.679439 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184922.142094 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184922.142094 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92445.981633 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92445.981633 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 24547500 # number of replacements +system.cpu.icache.tags.tagsinuse 511.926335 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 427774095 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24548012 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.426018 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 21430762500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.926335 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999856 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999856 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 482293482 # Number of tag accesses -system.cpu.icache.tags.data_accesses 482293482 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 432810859 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 432810859 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 432810859 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 432810859 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 432810859 # number of overall hits -system.cpu.icache.overall_hits::total 432810859 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24741312 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24741312 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24741312 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24741312 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24741312 # number of overall misses -system.cpu.icache.overall_misses::total 24741312 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 329592002500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 329592002500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 329592002500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 329592002500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 329592002500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 329592002500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 457552171 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 457552171 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 457552171 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 457552171 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 457552171 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 457552171 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054073 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.054073 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.054073 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.054073 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.054073 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.054073 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13321.524845 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13321.524845 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13321.524845 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13321.524845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13321.524845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13321.524845 # average overall miss latency +system.cpu.icache.tags.tag_accesses 476870138 # Number of tag accesses +system.cpu.icache.tags.data_accesses 476870138 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 427774095 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 427774095 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 427774095 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 427774095 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 427774095 # number of overall hits +system.cpu.icache.overall_hits::total 427774095 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24548022 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24548022 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24548022 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24548022 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24548022 # number of overall misses +system.cpu.icache.overall_misses::total 24548022 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 329750158000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 329750158000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 329750158000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 329750158000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 329750158000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 329750158000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 452322117 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 452322117 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 452322117 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 452322117 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 452322117 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 452322117 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054271 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.054271 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.054271 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.054271 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.054271 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.054271 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13432.860619 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13432.860619 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13432.860619 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13432.860619 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13432.860619 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13432.860619 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 24740790 # number of writebacks -system.cpu.icache.writebacks::total 24740790 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24741312 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24741312 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24741312 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 24741312 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 24741312 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 24741312 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52293 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 52293 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52293 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 52293 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304850691500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 304850691500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304850691500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 304850691500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304850691500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 304850691500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4087122500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4087122500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4087122500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 4087122500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054073 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054073 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054073 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.054073 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054073 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.054073 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12321.524885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12321.524885 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12321.524885 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12321.524885 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12321.524885 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12321.524885 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 78158.118677 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 78158.118677 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 78158.118677 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 78158.118677 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1647378 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65415.989966 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 70152651 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1710758 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 41.006765 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5897369000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9082.397486 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 468.031396 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 465.228429 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8079.882193 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47320.450462 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.138586 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007142 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007099 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123289 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.722053 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998169 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63076 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 301 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 861 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5993 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55903 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004639 # 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number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25481161022 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25481161022 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 11306022501 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11306022501 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 516791000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 440365500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7782841501 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78867184023 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 87607182024 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 516791000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 440365500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7782841501 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78867184023 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 87607182024 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3276571500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5809931000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 9086502500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3276571500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5809931000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9086502500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010196 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60038241001 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60038241001 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10453433004 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10453433004 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33849413548 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33849413548 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 11199554001 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11199554001 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 877019000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 631565000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10453433004 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93887654549 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 105849671553 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 877019000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 631565000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10453433004 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93887654549 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 105849671553 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3611009000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5809783000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 9420792000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3611009000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5809783000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9420792000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009588 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.118132 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.118132 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.121055 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.121055 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.305219 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.305219 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004327 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044412 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044412 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.439635 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.439635 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.107001 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.033073 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.107001 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.033073 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78218.231593 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19083.602484 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19083.602484 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.295400 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.295400 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004361 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043639 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043639 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.436316 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.436316 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.103883 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.032075 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.103883 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.032075 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131719.549463 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19091.946968 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19091.946968 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72944.879406 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72944.879406 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72690.640537 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72690.640537 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75552.119164 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75552.119164 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20639.713938 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20639.713938 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72690.640537 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.351916 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73716.178974 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72690.640537 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.351916 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73716.178974 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62657.937009 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172411.745504 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 105668.064100 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62657.937009 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.362436 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 75911.899113 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 72719983 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 36740859 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1912 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1912 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86242.262534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86242.262534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97644.531871 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97644.531871 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 103535.606613 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 103535.606613 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20650.125014 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20650.125014 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97644.531871 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91768.445829 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92720.292670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97644.531871 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91768.445829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92720.292670 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172417.586657 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109560.654518 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.724270 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 78707.303624 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 72021080 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 36381496 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4425 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1940 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1940 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1798088 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 34134170 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1770978 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33811680 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 10025859 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24740790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2858806 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 34075 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 9868219 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24547500 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2814706 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 33649 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 34076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2397848 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2397848 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24741312 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7596551 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1271756 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1245987 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 74327998 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33916673 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 673778 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2238495 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 111156944 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3170201152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1191384986 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2119720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7481688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4371187546 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2188425 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 94133704 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 39520716 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018595 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.135091 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 33650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2356666 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2356666 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24548022 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7494335 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1271849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1243016 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73748124 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33477065 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 672528 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2206986 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 110104703 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3145459904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1175323090 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2133296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7422888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4330339178 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2114439 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 90765792 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 39101108 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018304 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134047 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 38785811 98.14% 98.14% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 734905 1.86% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 38385418 98.17% 98.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 715690 1.83% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 39520716 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 70288980496 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 39101108 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 69634684493 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1482392 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1487890 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 37194713363 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36904751913 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15679329987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15462672587 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 408839447 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 405908415 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1303303960 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1279140469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40309 # Transaction distribution -system.iobus.trans_dist::ReadResp 40309 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40325 # Transaction distribution +system.iobus.trans_dist::ReadResp 40325 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1333,11 +1335,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353760 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1352,102 +1354,102 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37793000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37691500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 335000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25128500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25239000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36456000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36441500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569339894 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569511366 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147736000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115470 # number of replacements -system.iocache.tags.tagsinuse 10.448409 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115486 # number of replacements +system.iocache.tags.tagsinuse 10.448155 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13140724969000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.519445 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.928964 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219965 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433060 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653026 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13141696144000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.519387 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.928768 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219962 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433048 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653010 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039749 # Number of tag accesses -system.iocache.tags.data_accesses 1039749 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039893 # Number of tag accesses +system.iocache.tags.data_accesses 1039893 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115488 # number of demand (read+write) misses -system.iocache.demand_misses::total 115528 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115504 # number of demand (read+write) misses +system.iocache.demand_misses::total 115544 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115488 # number of overall misses -system.iocache.overall_misses::total 115528 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1631024611 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1636110611 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115504 # number of overall misses +system.iocache.overall_misses::total 115544 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 2067712004 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 2072797504 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12739251283 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12739251283 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14370275894 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14375712894 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14370275894 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14375712894 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13276938862 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13276938862 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15344650866 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15350087366 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15344650866 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15350087366 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115488 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115528 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115504 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115544 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115488 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115528 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115504 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115544 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1461,53 +1463,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184839.597801 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 184641.757251 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 233904.072851 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 233502.028163 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119433.466615 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119433.466615 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124430.900994 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124434.880670 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124430.900994 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124434.880670 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31942 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124474.413692 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 124474.413692 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 132849.519203 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 132850.579571 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 132849.519203 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 132850.579571 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 54006 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3389 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3503 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.425199 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 15.417071 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8824 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8861 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115488 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115528 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115504 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115544 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115488 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115528 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1189824611 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1193060611 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115504 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115544 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1625712004 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1628947504 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7399114026 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7399114026 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8588938637 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8592375637 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8588938637 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8592375637 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7936726922 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7936726922 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9562438926 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9565875426 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9562438926 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9565875426 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1521,95 +1523,95 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134839.597801 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 134641.757251 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 183904.072851 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 183502.028163 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69368.428204 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69368.428204 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74370.831922 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74374.832396 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74370.831922 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74374.832396 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 3617552 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1792214 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3206 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74408.675111 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74408.675111 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 82788.811868 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82789.893253 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 82788.811868 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82789.893253 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 3510315 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1740308 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3085 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 85991 # Transaction distribution -system.membus.trans_dist::ReadResp 551423 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 85987 # Transaction distribution +system.membus.trans_dist::ReadResp 540308 # Transaction distribution system.membus.trans_dist::WriteReq 33707 # Transaction distribution system.membus.trans_dist::WriteResp 33707 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1512694 # Transaction distribution -system.membus.trans_dist::CleanEvict 249055 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4641 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1462749 # Transaction distribution +system.membus.trans_dist::CleanEvict 243530 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4703 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 731311 # Transaction distribution -system.membus.trans_dist::ReadExResp 731311 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 465432 # Transaction distribution -system.membus.trans_dist::InvalidateReq 654388 # Transaction distribution +system.membus.trans_dist::ReadExReq 695596 # Transaction distribution +system.membus.trans_dist::ReadExResp 695596 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 454321 # Transaction distribution +system.membus.trans_dist::InvalidateReq 648947 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6920 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4683490 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4813146 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5050656 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4528935 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4658587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4896260 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 169337260 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 169507674 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7241152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7241152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 176748826 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3012 # Total snoops (count) -system.membus.snoopTraffic 192320 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1975472 # Request fanout histogram -system.membus.snoop_fanout::mean 0.014689 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.120303 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163142636 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 163313042 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7249536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7249536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 170562578 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2899 # Total snoops (count) +system.membus.snoopTraffic 185088 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1923263 # Request fanout histogram +system.membus.snoop_fanout::mean 0.016618 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.127834 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1946455 98.53% 98.53% # Request fanout histogram -system.membus.snoop_fanout::1 29017 1.47% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1891303 98.34% 98.34% # Request fanout histogram +system.membus.snoop_fanout::1 31960 1.66% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1975472 # Request fanout histogram -system.membus.reqLayer0.occupancy 99807500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1923263 # Request fanout histogram +system.membus.reqLayer0.occupancy 99811000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5588000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5612500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9976212567 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9664854495 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6680987810 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6432615655 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44817130 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44921497 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1652,28 +1654,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |