diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt | 2459 |
1 files changed, 1242 insertions, 1217 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index d21e89078..c77078f22 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.660717 # Number of seconds simulated -sim_ticks 51660717372000 # Number of ticks simulated -final_tick 51660717372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.687765 # Number of seconds simulated +sim_ticks 51687764518000 # Number of ticks simulated +final_tick 51687764518000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187164 # Simulator instruction rate (inst/s) -host_op_rate 219920 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10422609624 # Simulator tick rate (ticks/s) -host_mem_usage 677216 # Number of bytes of host memory used -host_seconds 4956.60 # Real time elapsed on the host -sim_insts 927696922 # Number of instructions simulated -sim_ops 1090057089 # Number of ops (including micro ops) simulated +host_inst_rate 151884 # Simulator instruction rate (inst/s) +host_op_rate 178474 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8204277049 # Simulator tick rate (ticks/s) +host_mem_usage 687220 # Number of bytes of host memory used +host_seconds 6300.10 # Real time elapsed on the host +sim_insts 956884636 # Number of instructions simulated +sim_ops 1124405089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 368128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 311744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10118784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 60722568 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 418176 # Number of bytes read from this memory -system.physmem.bytes_read::total 71939400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10118784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10118784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 88730048 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 423488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 359680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10197440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 68348040 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 416768 # Number of bytes read from this memory +system.physmem.bytes_read::total 79745416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10197440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10197440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 96812416 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 88750628 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 5752 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4871 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 158106 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 948803 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6534 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1124066 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1386407 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 96832996 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5620 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 159335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1067951 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6512 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1246035 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1512694 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1388980 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 195870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1175411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1392536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 195870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 195870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1717554 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1515267 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 8193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 197289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1322325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1542830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1873024 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1717952 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1717554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 195870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1175809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3110488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1124066 # Number of read requests accepted -system.physmem.writeReqs 1388980 # Number of write requests accepted -system.physmem.readBursts 1124066 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1388980 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 71890560 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 49664 # Total number of bytes read from write queue -system.physmem.bytesWritten 88748928 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 71939400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 88750628 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 776 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1873422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1873024 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 8193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1322723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3416252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1246035 # Number of read requests accepted +system.physmem.writeReqs 1515267 # Number of write requests accepted +system.physmem.readBursts 1246035 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1515267 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 79703040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 43200 # Total number of bytes read from write queue +system.physmem.bytesWritten 96830656 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 79745416 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 96832996 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 675 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2258 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 65344 # Per bank write bursts -system.physmem.perBankRdBursts::1 73127 # Per bank write bursts -system.physmem.perBankRdBursts::2 68334 # Per bank write bursts -system.physmem.perBankRdBursts::3 62589 # Per bank write bursts -system.physmem.perBankRdBursts::4 65747 # Per bank write bursts -system.physmem.perBankRdBursts::5 73971 # Per bank write bursts -system.physmem.perBankRdBursts::6 66723 # Per bank write bursts -system.physmem.perBankRdBursts::7 65172 # Per bank write bursts -system.physmem.perBankRdBursts::8 63356 # Per bank write bursts -system.physmem.perBankRdBursts::9 122297 # Per bank write bursts -system.physmem.perBankRdBursts::10 70526 # Per bank write bursts -system.physmem.perBankRdBursts::11 71466 # Per bank write bursts -system.physmem.perBankRdBursts::12 64199 # Per bank write bursts -system.physmem.perBankRdBursts::13 65172 # Per bank write bursts -system.physmem.perBankRdBursts::14 60121 # Per bank write bursts -system.physmem.perBankRdBursts::15 65146 # Per bank write bursts -system.physmem.perBankWrBursts::0 84316 # Per bank write bursts -system.physmem.perBankWrBursts::1 87030 # Per bank write bursts -system.physmem.perBankWrBursts::2 86821 # Per bank write bursts -system.physmem.perBankWrBursts::3 84154 # Per bank write bursts -system.physmem.perBankWrBursts::4 87756 # Per bank write bursts -system.physmem.perBankWrBursts::5 92254 # Per bank write bursts -system.physmem.perBankWrBursts::6 85357 # Per bank write bursts -system.physmem.perBankWrBursts::7 85828 # Per bank write bursts -system.physmem.perBankWrBursts::8 86266 # Per bank write bursts -system.physmem.perBankWrBursts::9 90537 # Per bank write bursts -system.physmem.perBankWrBursts::10 89139 # Per bank write bursts -system.physmem.perBankWrBursts::11 90914 # Per bank write bursts -system.physmem.perBankWrBursts::12 83868 # Per bank write bursts -system.physmem.perBankWrBursts::13 84845 # Per bank write bursts -system.physmem.perBankWrBursts::14 82305 # Per bank write bursts -system.physmem.perBankWrBursts::15 85312 # Per bank write bursts +system.physmem.perBankRdBursts::0 74796 # Per bank write bursts +system.physmem.perBankRdBursts::1 76131 # Per bank write bursts +system.physmem.perBankRdBursts::2 70862 # Per bank write bursts +system.physmem.perBankRdBursts::3 68837 # Per bank write bursts +system.physmem.perBankRdBursts::4 72123 # Per bank write bursts +system.physmem.perBankRdBursts::5 84628 # Per bank write bursts +system.physmem.perBankRdBursts::6 78694 # Per bank write bursts +system.physmem.perBankRdBursts::7 74893 # Per bank write bursts +system.physmem.perBankRdBursts::8 72007 # Per bank write bursts +system.physmem.perBankRdBursts::9 129561 # Per bank write bursts +system.physmem.perBankRdBursts::10 74825 # Per bank write bursts +system.physmem.perBankRdBursts::11 74032 # Per bank write bursts +system.physmem.perBankRdBursts::12 72055 # Per bank write bursts +system.physmem.perBankRdBursts::13 77727 # Per bank write bursts +system.physmem.perBankRdBursts::14 71057 # Per bank write bursts +system.physmem.perBankRdBursts::15 73132 # Per bank write bursts +system.physmem.perBankWrBursts::0 93267 # Per bank write bursts +system.physmem.perBankWrBursts::1 94026 # Per bank write bursts +system.physmem.perBankWrBursts::2 93600 # Per bank write bursts +system.physmem.perBankWrBursts::3 92665 # Per bank write bursts +system.physmem.perBankWrBursts::4 94539 # Per bank write bursts +system.physmem.perBankWrBursts::5 102396 # Per bank write bursts +system.physmem.perBankWrBursts::6 95600 # Per bank write bursts +system.physmem.perBankWrBursts::7 94740 # Per bank write bursts +system.physmem.perBankWrBursts::8 92115 # Per bank write bursts +system.physmem.perBankWrBursts::9 99710 # Per bank write bursts +system.physmem.perBankWrBursts::10 92671 # Per bank write bursts +system.physmem.perBankWrBursts::11 94633 # Per bank write bursts +system.physmem.perBankWrBursts::12 92127 # Per bank write bursts +system.physmem.perBankWrBursts::13 95527 # Per bank write bursts +system.physmem.perBankWrBursts::14 92160 # Per bank write bursts +system.physmem.perBankWrBursts::15 93203 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 29 # Number of times write queue was full causing retry -system.physmem.totGap 51660715485000 # Total gap between requests +system.physmem.numWrRetry 30 # Number of times write queue was full causing retry +system.physmem.totGap 51687762664000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1124051 # Read request sizes (log2) +system.physmem.readPktSize::6 1246020 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1386407 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1060868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 132 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1512694 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1180646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 58552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,164 +160,173 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 33876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 77727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 79574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 81890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 80157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 81104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 84995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 84344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 80623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 81914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 84683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 81947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 82184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 83786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 79897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 78990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 78233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 638647 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.530251 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.310832 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 286.508507 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 275744 43.18% 43.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 164283 25.72% 68.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 60231 9.43% 78.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 32872 5.15% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22951 3.59% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16028 2.51% 89.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 11191 1.75% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9395 1.47% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 45952 7.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 638647 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 75991 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.781369 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 142.935713 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 75988 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 31478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 83104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 89526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 91633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 87574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 93055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 92225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 93220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 90182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 92806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 94606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 92258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 89036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 87252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 83915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 83414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 82380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 106 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 686907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 256.997398 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 154.492038 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 292.459663 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 294027 42.80% 42.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 175466 25.54% 68.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 64376 9.37% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35669 5.19% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24767 3.61% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16380 2.38% 88.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 12324 1.79% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 10264 1.49% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 53634 7.81% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 686907 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 80666 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.437595 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 138.740748 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 80664 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 75991 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 75991 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.248240 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.695683 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.085121 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 64109 84.36% 84.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 9386 12.35% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 485 0.64% 97.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 369 0.49% 97.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 63 0.08% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 114 0.15% 98.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 258 0.34% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 31 0.04% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 303 0.40% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 66 0.09% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 30 0.04% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 60 0.08% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 313 0.41% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 41 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 27 0.04% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 117 0.15% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 162 0.21% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 21 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 75991 # Writes before turning the bus around for reads -system.physmem.totQLat 16312474093 # Total ticks spent queuing -system.physmem.totMemAccLat 37374161593 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5616450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14522.05 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 80666 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 80666 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.756093 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.057108 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.363487 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 67894 84.17% 84.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 3915 4.85% 89.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 3350 4.15% 93.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 2485 3.08% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1103 1.37% 97.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 521 0.65% 98.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 244 0.30% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 153 0.19% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 79 0.10% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 83 0.10% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 83 0.10% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 89 0.11% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 450 0.56% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 43 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 41 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 30 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 23 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 5 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 9 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 18 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 80666 # Writes before turning the bus around for reads +system.physmem.totQLat 17151209707 # Total ticks spent queuing +system.physmem.totMemAccLat 40501709707 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6226800000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13772.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33272.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32522.09 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.67 # Average write queue length when enqueuing -system.physmem.readRowHits 859362 # Number of row buffer hits during reads -system.physmem.writeRowHits 1011981 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.98 # Row buffer hit rate for writes -system.physmem.avgGap 20557011.49 # Average gap between requests -system.physmem.pageHitRate 74.55 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2420719560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1320829125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4219854600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4493983680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3374226435840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1315006290315 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29842911750000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34544599863120 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.682250 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49645601262378 # Time in different power states -system.physmem_0.memoryStateTime::REF 1725064640000 # Time in different power states +system.physmem.avgWrQLen 25.30 # Average write queue length when enqueuing +system.physmem.readRowHits 964137 # Number of row buffer hits during reads +system.physmem.writeRowHits 1107294 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.18 # Row buffer hit rate for writes +system.physmem.avgGap 18718619.94 # Average gap between requests +system.physmem.pageHitRate 75.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2629783800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1434901875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4687519200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4930197840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3375993173280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1305935149860 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29867098550250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34562709276105 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.682675 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49685845654409 # Time in different power states +system.physmem_0.memoryStateTime::REF 1725967880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 290044177622 # Time in different power states +system.physmem_0.memoryStateTime::ACT 275945978091 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2407451760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1313589750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4541752800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4491845280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3374226435840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1315022855940 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29842897218750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34544901150120 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.688082 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49645554021211 # Time in different power states -system.physmem_1.memoryStateTime::REF 1725064640000 # Time in different power states +system.physmem_1.actEnergy 2563233120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1398589500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5026242000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4873906080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3375993173280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1305717731910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29867289276000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34562862151890 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.685632 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49686132095770 # Time in different power states +system.physmem_1.memoryStateTime::REF 1725967880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 290092863289 # Time in different power states +system.physmem_1.memoryStateTime::ACT 275664064230 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory @@ -334,30 +343,30 @@ system.realview.nvmem.bw_inst_read::total 14 # I system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 256052360 # Number of BP lookups -system.cpu.branchPred.condPredicted 178125867 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12215850 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 188334497 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126943208 # Number of BTB hits +system.cpu.branchPred.lookups 264432116 # Number of BP lookups +system.cpu.branchPred.condPredicted 184777930 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12360480 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 195121872 # Number of BTB lookups +system.cpu.branchPred.BTBHits 131792442 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 67.403057 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31309548 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2129742 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7077002 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 5011250 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2065752 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 841782 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 67.543654 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 32005520 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2166164 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7202634 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 5156312 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2046322 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 848562 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,65 +396,70 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 558947 # Table walker walks requested -system.cpu.dtb.walker.walksLong 558947 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 19870 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 181727 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 558947 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 558947 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 558947 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 201597 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 27104.207900 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 22942.325413 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 21051.309840 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 199234 98.83% 98.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2010 1.00% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 57 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 120 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 59 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 92 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 201597 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -1569310592 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -1569310592 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -1569310592 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 181728 90.14% 90.14% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 19870 9.86% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 201598 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 558947 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 584775 # Table walker walks requested +system.cpu.dtb.walker.walksLong 584775 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 23234 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 194431 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 584775 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 584775 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 584775 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 217665 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 25428.727632 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21638.505013 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 16299.176879 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 136227 62.59% 62.59% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 78767 36.19% 98.77% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 1401 0.64% 99.42% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 854 0.39% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 27 0.01% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 133 0.06% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-229375 57 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::229376-262143 75 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 47 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 26 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 20 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::360448-393215 15 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-425983 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 217665 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -10206296 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -10206296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -10206296 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 194432 89.33% 89.33% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 23234 10.67% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 217666 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 584775 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 558947 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 201598 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 584775 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 217666 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 201598 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 760545 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 217666 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 802441 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 179275780 # DTB read hits -system.cpu.dtb.read_misses 461379 # DTB read misses -system.cpu.dtb.write_hits 158920483 # DTB write hits -system.cpu.dtb.write_misses 97568 # DTB write misses +system.cpu.dtb.read_hits 184602893 # DTB read hits +system.cpu.dtb.read_misses 481054 # DTB read misses +system.cpu.dtb.write_hits 163948315 # DTB write hits +system.cpu.dtb.write_misses 103721 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 45647 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1093 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 78530 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1411 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14509 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 47766 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1117 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 80755 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1436 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 15519 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 22879 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 179737159 # DTB read accesses -system.cpu.dtb.write_accesses 159018051 # DTB write accesses +system.cpu.dtb.perms_faults 23435 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 185083947 # DTB read accesses +system.cpu.dtb.write_accesses 164052036 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 338196263 # DTB hits -system.cpu.dtb.misses 558947 # DTB misses -system.cpu.dtb.accesses 338755210 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 348551208 # DTB hits +system.cpu.dtb.misses 584775 # DTB misses +system.cpu.dtb.accesses 349135983 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -475,634 +489,639 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 134834 # Table walker walks requested -system.cpu.itb.walker.walksLong 134834 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1067 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 117333 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 134834 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 134834 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 134834 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 118400 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 30431.579392 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 25904.631312 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24094.406061 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 115676 97.70% 97.70% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 5 0.00% 97.70% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 2464 2.08% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 78 0.07% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 124 0.10% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 31 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 17 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 118400 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -1570341092 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -1570341092 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -1570341092 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 117333 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1067 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 118400 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 136740 # Table walker walks requested +system.cpu.itb.walker.walksLong 136740 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1077 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 118526 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 136740 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 136740 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 136740 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 119603 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27883.393393 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23898.853743 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 18564.311346 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-32767 67731 56.63% 56.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-65535 48774 40.78% 97.41% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-98303 1154 0.96% 98.37% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-131071 1639 1.37% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-163839 37 0.03% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::163840-196607 137 0.11% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::229376-262143 18 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-294911 21 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::294912-327679 20 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-360447 18 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::360448-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 119603 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -10844796 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -10844796 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -10844796 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 118526 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1077 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 119603 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134834 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 134834 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136740 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 136740 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118400 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 118400 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 253234 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 442741882 # ITB inst hits -system.cpu.itb.inst_misses 134834 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119603 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 119603 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 256343 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 457894474 # ITB inst hits +system.cpu.itb.inst_misses 136740 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 45647 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1093 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 56540 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 47766 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1117 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 57885 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 318606 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 331252 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 442876716 # ITB inst accesses -system.cpu.itb.hits 442741882 # DTB hits -system.cpu.itb.misses 134834 # DTB misses -system.cpu.itb.accesses 442876716 # DTB accesses -system.cpu.numPwrStateTransitions 33004 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16502 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3052827188.483881 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59796953066.006256 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7205 43.66% 43.66% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9262 56.13% 99.79% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 458031214 # ITB inst accesses +system.cpu.itb.hits 457894474 # DTB hits +system.cpu.itb.misses 136740 # DTB misses +system.cpu.itb.accesses 458031214 # DTB accesses +system.cpu.numPwrStateTransitions 33262 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16631 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3032078673.597498 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59558384510.943253 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7336 44.11% 44.11% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9260 55.68% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988777699120 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16502 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1282963107639 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50377754264361 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2565980290 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988777698120 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16631 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1261264097400 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50426500420600 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2522582223 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 927696922 # Number of instructions committed -system.cpu.committedOps 1090057089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 94830796 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7642 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100756547271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.765968 # CPI: cycles per instruction -system.cpu.ipc 0.361537 # IPC: instructions per cycle +system.cpu.committedInsts 956884636 # Number of instructions committed +system.cpu.committedOps 1124405089 # Number of ops (including micro ops) committed +system.cpu.discardedOps 99545013 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7771 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100854059486 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.636245 # CPI: cycles per instruction +system.cpu.ipc 0.379327 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 755349201 69.29% 69.29% # Class of committed instruction -system.cpu.op_class_0::IntMult 2273269 0.21% 69.50% # Class of committed instruction -system.cpu.op_class_0::IntDiv 98990 0.01% 69.51% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 109509 0.01% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::MemRead 173855507 15.95% 85.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 158370570 14.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 779381648 69.32% 69.32% # Class of committed instruction +system.cpu.op_class_0::IntMult 2317785 0.21% 69.52% # Class of committed instruction +system.cpu.op_class_0::IntDiv 99593 0.01% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 108729 0.01% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::MemRead 179105650 15.93% 85.47% # Class of committed instruction +system.cpu.op_class_0::MemWrite 163391641 14.53% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 1090057089 # Class of committed instruction +system.cpu.op_class_0::total 1124405089 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16502 # number of quiesce instructions executed -system.cpu.tickCycles 1756726391 # Number of cycles that the object actually ticked -system.cpu.idleCycles 809253899 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 10800470 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.930063 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322845784 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10800982 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.890410 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7088310500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.930063 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16631 # number of quiesce instructions executed +system.cpu.tickCycles 1810679239 # Number of cycles that the object actually ticked +system.cpu.idleCycles 711902984 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 11237287 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.957340 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 332608189 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11237799 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.597272 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4326295500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.957340 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1354272764 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1354272764 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 165477998 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 165477998 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148389977 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148389977 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 514152 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 514152 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336855 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336855 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3884412 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3884412 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4194010 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4194010 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 314204830 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 314204830 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 314718982 # number of overall hits -system.cpu.dcache.overall_hits::total 314718982 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5939711 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5939711 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4167073 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4167073 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1413293 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1413293 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1239143 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1239143 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 311310 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 311310 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1395920077 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1395920077 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 170244902 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 170244902 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 153016106 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 153016106 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 525044 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 525044 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 336678 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 336678 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4066137 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4066137 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4385244 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4385244 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 323597686 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 323597686 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 324122730 # number of overall hits +system.cpu.dcache.overall_hits::total 324122730 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6163054 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6163054 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4362358 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4362358 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1504058 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1504058 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1246141 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1246141 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 320841 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 320841 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 11345927 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11345927 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12759220 # number of overall misses -system.cpu.dcache.overall_misses::total 12759220 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 110013337000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 110013337000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 204497661000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 204497661000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53262030500 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 53262030500 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5161319000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5161319000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 367773028500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 367773028500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 367773028500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 367773028500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 171417709 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 171417709 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 152557050 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 152557050 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1927445 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1927445 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1575998 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1575998 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4195722 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4195722 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4194011 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4194011 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 325550757 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 325550757 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 327478202 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 327478202 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034651 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.034651 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027315 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027315 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733247 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.733247 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786259 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786259 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074197 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074197 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 11771553 # 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number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2029102 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1582819 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1582819 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4386978 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4386978 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4385245 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4385245 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 335369239 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 335369239 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 337398341 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 337398341 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034936 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.034936 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027719 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027719 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.741243 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.741243 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787292 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.787292 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073135 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073135 # 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miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039347 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039347 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16400.338615 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16400.338615 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36153.251980 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36153.251980 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22015.025186 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 22015.025186 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15240.097120 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15240.097120 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # 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number of writebacks -system.cpu.dcache.writebacks::total 8297164 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 307308 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 307308 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1836532 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1836532 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 159 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 159 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69724 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 69724 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2143999 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2143999 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2143999 # 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number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 249912 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9201928 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9201928 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 10607740 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 10607740 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # 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number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3504907500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3504907500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 256810102500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 256810102500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 283514195500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 283514195500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197989500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197989500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6197989500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6197989500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032858 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032858 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729366 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729366 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786158 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786158 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057579 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057579 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9525450 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9525450 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 11021981 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 11021981 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33698 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33698 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67405 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67405 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 89040002500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 89040002500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82314078000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 82314078000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 24215113000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 24215113000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26183606500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26183606500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3424677000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3424677000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 197537687000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 197537687000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221752800000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 221752800000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6231251500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6231251500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6231251500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6231251500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033149 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033149 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.737534 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.737534 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787195 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787195 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056967 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056967 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028266 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028266 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032392 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032392 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17115.819039 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17115.819039 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46509.168472 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46509.168472 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18995.493708 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18995.493708 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41982.291942 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41982.291942 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14507.908157 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14507.908157 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27908.292969 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27908.292969 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26727.106386 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26727.106386 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183932.976229 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183932.976229 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91954.208270 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91954.208270 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 24348068 # number of replacements -system.cpu.icache.tags.tagsinuse 511.885312 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 418063563 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24348580 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.169936 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 32786837500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.885312 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028403 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028403 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032668 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032668 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15226.468489 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15226.468489 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33849.714876 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33849.714876 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16180.829532 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16180.829532 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21014.349668 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21014.349668 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13703.531643 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13703.531643 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20737.885034 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20737.885034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20119.141922 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20119.141922 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184914.579500 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184914.579500 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92444.944737 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92444.944737 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 24740790 # number of replacements +system.cpu.icache.tags.tagsinuse 511.930482 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 432810859 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24741302 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.493455 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20587192500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.930482 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999864 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 466760742 # Number of tag accesses -system.cpu.icache.tags.data_accesses 466760742 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 418063563 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 418063563 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 418063563 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 418063563 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 418063563 # number of overall hits -system.cpu.icache.overall_hits::total 418063563 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24348590 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24348590 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24348590 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24348590 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24348590 # number of overall misses -system.cpu.icache.overall_misses::total 24348590 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 329659145500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 329659145500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 329659145500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 329659145500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 329659145500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 329659145500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 442412153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 442412153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 442412153 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 442412153 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 442412153 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 442412153 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055036 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.055036 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.055036 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.055036 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.055036 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.055036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13539.147257 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13539.147257 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13539.147257 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13539.147257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13539.147257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13539.147257 # average overall miss latency +system.cpu.icache.tags.tag_accesses 482293482 # Number of tag accesses +system.cpu.icache.tags.data_accesses 482293482 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 432810859 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 432810859 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 432810859 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 432810859 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 432810859 # number of overall hits +system.cpu.icache.overall_hits::total 432810859 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24741312 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24741312 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24741312 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24741312 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24741312 # number of overall misses +system.cpu.icache.overall_misses::total 24741312 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 329592002500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 329592002500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 329592002500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 329592002500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 329592002500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 329592002500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 457552171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 457552171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 457552171 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 457552171 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 457552171 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 457552171 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054073 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.054073 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.054073 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.054073 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.054073 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.054073 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13321.524845 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13321.524845 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13321.524845 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13321.524845 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13321.524845 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13321.524845 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 24348068 # number of writebacks -system.cpu.icache.writebacks::total 24348068 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24348590 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24348590 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24348590 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 24348590 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 24348590 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 24348590 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305310556500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 305310556500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305310556500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 305310556500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305310556500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 305310556500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746653000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746653000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746653000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 6746653000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055036 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055036 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055036 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.055036 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055036 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.055036 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12539.147298 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12539.147298 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12539.147298 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12539.147298 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12539.147298 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12539.147298 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128976.906460 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128976.906460 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128976.906460 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128976.906460 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1508622 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65349.873719 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 66336088 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1571990 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 42.198798 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 10459942000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36987.173983 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 327.335267 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 410.823725 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8044.893687 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19579.647057 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.564379 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004995 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006269 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122755 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.298762 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997160 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 289 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63079 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 289 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 541 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2400 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5595 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54498 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004410 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962509 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 577006805 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 577006805 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 916908 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 278918 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1195826 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8297164 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 861 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5993 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55903 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962463 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 587932179 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 587932179 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 928594 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 259345 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7782841501 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7782841501 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25481161022 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25481161022 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 11306022501 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11306022501 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 516791000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 440365500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7782841501 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3276571500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5809931000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9086502500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010196 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782369 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782369 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.118132 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.118132 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.278818 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.278818 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004346 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004346 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043089 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043089 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.431195 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.431195 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006234 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017164 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004346 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.099357 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030370 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006234 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017164 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004346 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.099357 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127272.839253 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126911.936364 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67985.168034 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67985.168034 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122812.641665 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122812.641665 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122437.282746 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122437.282746 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124905.908758 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124905.908758 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69672.880744 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69672.880744 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127272.839253 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122437.282746 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123503.756561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123431.883604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127272.839253 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122437.282746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123503.756561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123431.883604 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113476.772640 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171430.275692 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136182.853522 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113476.772640 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85703.692714 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97839.335238 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 71038022 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 35888421 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4192 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2302 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2302 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.305219 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.305219 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004327 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044412 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044412 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.439635 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.439635 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.107001 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.033073 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.107001 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.033073 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78218.231593 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19083.602484 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19083.602484 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72944.879406 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72944.879406 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72690.640537 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72690.640537 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75552.119164 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75552.119164 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20639.713938 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20639.713938 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72690.640537 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.351916 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73716.178974 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72690.640537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.351916 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73716.178974 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62657.937009 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172411.745504 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 105668.064100 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62657.937009 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.362436 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 75911.899113 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 72719983 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 36740859 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1912 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1912 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1730261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33359239 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 9683600 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24348068 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2741013 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 48305 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1798088 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 34134170 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 10025859 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24740790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2858806 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 34075 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 48306 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2282432 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2282432 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24348590 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7288491 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1345648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1238984 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73149864 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32634714 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 686896 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2163808 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 108635282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3119933760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1143229458 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2270312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7381280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4272814810 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2178284 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 92284400 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 38701577 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018037 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.133086 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 34076 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2397848 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2397848 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24741312 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7596551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1271756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1245987 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 74327998 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33916673 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 673778 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2238495 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 111156944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3170201152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1191384986 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2119720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7481688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4371187546 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2188425 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 94133704 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 39520716 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018595 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.135091 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 38003503 98.20% 98.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 698074 1.80% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 38785811 98.14% 98.14% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 734905 1.86% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 38701577 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 68717300491 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 39520716 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 70288980496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1477390 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1482392 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36605927318 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 37194713363 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15037927648 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15679329987 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 403140932 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 408839447 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1241184926 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1303303960 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40331 # Transaction distribution -system.iobus.trans_dist::ReadResp 40331 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40309 # Transaction distribution +system.iobus.trans_dist::ReadResp 40309 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1314,11 +1333,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231020 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231020 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353804 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353760 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1333,16 +1352,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334512 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492432 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37711500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37793000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 336000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 335000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1352,7 +1371,7 @@ system.iobus.reqLayer10.occupancy 9000 # La system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -1360,75 +1379,75 @@ system.iobus.reqLayer16.occupancy 16000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25249000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25128500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36460500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36456000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567164602 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569339894 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147780000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147736000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115492 # number of replacements -system.iocache.tags.tagsinuse 10.441393 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115470 # number of replacements +system.iocache.tags.tagsinuse 10.448409 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115508 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153371816000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.521310 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.920084 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220082 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432505 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652587 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13140724969000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.519445 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.928964 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219965 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433060 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653026 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039947 # Number of tag accesses -system.iocache.tags.data_accesses 1039947 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039749 # Number of tag accesses +system.iocache.tags.data_accesses 1039749 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8846 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8883 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115510 # number of demand (read+write) misses -system.iocache.demand_misses::total 115550 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115488 # number of demand (read+write) misses +system.iocache.demand_misses::total 115528 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115510 # number of overall misses -system.iocache.overall_misses::total 115550 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1687962584 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1693032584 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115488 # number of overall misses +system.iocache.overall_misses::total 115528 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1631024611 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1636110611 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13411761018 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13411761018 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15099723602 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15105144602 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15099723602 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15105144602 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12739251283 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12739251283 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14370275894 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14375712894 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14370275894 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14375712894 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8846 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8883 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115510 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115550 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115488 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115528 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115510 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115550 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115488 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115528 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1442,53 +1461,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 190816.480217 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190592.433187 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184839.597801 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 184641.757251 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125738.403004 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125738.403004 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130722.219739 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130723.882319 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130722.219739 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130723.882319 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34055 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119433.466615 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119433.466615 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124430.900994 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124434.880670 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124430.900994 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124434.880670 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31942 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3409 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3389 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.989733 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.425199 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8846 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8883 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8824 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8861 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115510 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115550 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115488 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115528 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115510 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115550 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1245662584 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1248882584 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115488 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115528 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1189824611 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1193060611 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073418582 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8073418582 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9319081166 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9322502166 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9319081166 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9322502166 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7399114026 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7399114026 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8588938637 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8592375637 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8588938637 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8592375637 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1502,89 +1521,95 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140816.480217 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 140592.433187 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134839.597801 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 134641.757251 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75690.191461 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75690.191461 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80677.700338 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80679.378330 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80677.700338 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80679.378330 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 86006 # Transaction distribution -system.membus.trans_dist::ReadResp 525005 # Transaction distribution -system.membus.trans_dist::WriteReq 33706 # Transaction distribution -system.membus.trans_dist::WriteResp 33706 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1386407 # Transaction distribution -system.membus.trans_dist::CleanEvict 236604 # Transaction distribution -system.membus.trans_dist::UpgradeReq 38552 # Transaction distribution +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69368.428204 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69368.428204 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74370.831922 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74374.832396 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74370.831922 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74374.832396 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 3617552 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1792214 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3206 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 85991 # Transaction distribution +system.membus.trans_dist::ReadResp 551423 # Transaction distribution +system.membus.trans_dist::WriteReq 33707 # Transaction distribution +system.membus.trans_dist::WriteResp 33707 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1512694 # Transaction distribution +system.membus.trans_dist::CleanEvict 249055 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4641 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 635760 # Transaction distribution -system.membus.trans_dist::ReadExResp 635760 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 438999 # Transaction distribution -system.membus.trans_dist::InvalidateReq 640771 # Transaction distribution +system.membus.trans_dist::ReadExReq 731311 # Transaction distribution +system.membus.trans_dist::ReadExResp 731311 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 465432 # Transaction distribution +system.membus.trans_dist::InvalidateReq 654388 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4321043 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4450695 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4688271 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4683490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4813146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237510 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237510 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5050656 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 153447468 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 153617874 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7242560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7242560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 160860434 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3013 # Total snoops (count) -system.membus.snoopTraffic 192384 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3496836 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 169337260 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 169507674 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7241152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7241152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 176748826 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3012 # Total snoops (count) +system.membus.snoopTraffic 192320 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1975472 # Request fanout histogram +system.membus.snoop_fanout::mean 0.014689 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.120303 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3496836 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1946455 98.53% 98.53% # Request fanout histogram +system.membus.snoop_fanout::1 29017 1.47% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3496836 # Request fanout histogram -system.membus.reqLayer0.occupancy 99852500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1975472 # Request fanout histogram +system.membus.reqLayer0.occupancy 99807500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5614500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5588000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9224879373 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9976212567 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6035081327 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6680987810 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44925690 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44817130 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1627,28 +1652,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |