diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt | 2149 |
1 files changed, 1080 insertions, 1069 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 8edb1ca7a..4adb13d39 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.667490 # Number of seconds simulated -sim_ticks 51667489826000 # Number of ticks simulated -final_tick 51667489826000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.667600 # Number of seconds simulated +sim_ticks 51667599599000 # Number of ticks simulated +final_tick 51667599599000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98445 # Simulator instruction rate (inst/s) -host_op_rate 115675 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5518412939 # Simulator tick rate (ticks/s) -host_mem_usage 676348 # Number of bytes of host memory used -host_seconds 9362.74 # Real time elapsed on the host -sim_insts 921716010 # Number of instructions simulated -sim_ops 1083032845 # Number of ops (including micro ops) simulated +host_inst_rate 178939 # Simulator instruction rate (inst/s) +host_op_rate 210249 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10020424354 # Simulator tick rate (ticks/s) +host_mem_usage 726764 # Number of bytes of host memory used +host_seconds 5156.23 # Real time elapsed on the host +sim_insts 922648651 # Number of instructions simulated +sim_ops 1084091117 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 356224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 294592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10211648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 93641864 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 394368 # Number of bytes read from this memory -system.physmem.bytes_read::total 104898696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10211648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10211648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 87439552 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 355648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 310272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 9988672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94253512 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 413888 # Number of bytes read from this memory +system.physmem.bytes_read::total 105321992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 9988672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 9988672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 87921472 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 87460132 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 5566 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4603 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 159557 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1463167 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1639055 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1366243 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 87942052 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 5557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 156073 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1472724 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6467 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1645669 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1373773 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1368816 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 6895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 197642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1812394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2030265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1692351 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1376346 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 6883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 193326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1824229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2038453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 193326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 193326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1701675 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1692750 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1692351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 6895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1812793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7633 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3723015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1639055 # Number of read requests accepted -system.physmem.writeReqs 1368816 # Number of write requests accepted -system.physmem.readBursts 1639055 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1368816 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 104838592 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 60928 # Total number of bytes read from write queue -system.physmem.bytesWritten 87458560 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 104898696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 87460132 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 952 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 145140 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 96907 # Per bank write bursts -system.physmem.perBankRdBursts::1 103074 # Per bank write bursts -system.physmem.perBankRdBursts::2 99514 # Per bank write bursts -system.physmem.perBankRdBursts::3 96513 # Per bank write bursts -system.physmem.perBankRdBursts::4 97689 # Per bank write bursts -system.physmem.perBankRdBursts::5 108359 # Per bank write bursts -system.physmem.perBankRdBursts::6 97886 # Per bank write bursts -system.physmem.perBankRdBursts::7 97902 # Per bank write bursts -system.physmem.perBankRdBursts::8 96810 # Per bank write bursts -system.physmem.perBankRdBursts::9 157961 # Per bank write bursts -system.physmem.perBankRdBursts::10 100161 # Per bank write bursts -system.physmem.perBankRdBursts::11 104541 # Per bank write bursts -system.physmem.perBankRdBursts::12 94779 # Per bank write bursts -system.physmem.perBankRdBursts::13 97199 # Per bank write bursts -system.physmem.perBankRdBursts::14 94176 # Per bank write bursts -system.physmem.perBankRdBursts::15 94632 # Per bank write bursts -system.physmem.perBankWrBursts::0 82268 # Per bank write bursts -system.physmem.perBankWrBursts::1 85491 # Per bank write bursts -system.physmem.perBankWrBursts::2 84713 # Per bank write bursts -system.physmem.perBankWrBursts::3 83877 # Per bank write bursts -system.physmem.perBankWrBursts::4 85039 # Per bank write bursts -system.physmem.perBankWrBursts::5 91961 # Per bank write bursts -system.physmem.perBankWrBursts::6 84027 # Per bank write bursts -system.physmem.perBankWrBursts::7 85348 # Per bank write bursts -system.physmem.perBankWrBursts::8 84923 # Per bank write bursts -system.physmem.perBankWrBursts::9 91534 # Per bank write bursts -system.physmem.perBankWrBursts::10 85936 # Per bank write bursts -system.physmem.perBankWrBursts::11 89456 # Per bank write bursts -system.physmem.perBankWrBursts::12 82822 # Per bank write bursts -system.physmem.perBankWrBursts::13 84269 # Per bank write bursts -system.physmem.perBankWrBursts::14 82271 # Per bank write bursts -system.physmem.perBankWrBursts::15 82605 # Per bank write bursts +system.physmem.bw_write::total 1702073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1701675 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 6883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 193326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1824627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3740527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1645669 # Number of read requests accepted +system.physmem.writeReqs 1376346 # Number of write requests accepted +system.physmem.readBursts 1645669 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1376346 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 105266752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 56064 # Total number of bytes read from write queue +system.physmem.bytesWritten 87940608 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 105321992 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 87942052 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 876 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2255 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 378251 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 98784 # Per bank write bursts +system.physmem.perBankRdBursts::1 105100 # Per bank write bursts +system.physmem.perBankRdBursts::2 100845 # Per bank write bursts +system.physmem.perBankRdBursts::3 95977 # Per bank write bursts +system.physmem.perBankRdBursts::4 103819 # Per bank write bursts +system.physmem.perBankRdBursts::5 113338 # Per bank write bursts +system.physmem.perBankRdBursts::6 98145 # Per bank write bursts +system.physmem.perBankRdBursts::7 99955 # Per bank write bursts +system.physmem.perBankRdBursts::8 93968 # Per bank write bursts +system.physmem.perBankRdBursts::9 154563 # Per bank write bursts +system.physmem.perBankRdBursts::10 98779 # Per bank write bursts +system.physmem.perBankRdBursts::11 100711 # Per bank write bursts +system.physmem.perBankRdBursts::12 92945 # Per bank write bursts +system.physmem.perBankRdBursts::13 97659 # Per bank write bursts +system.physmem.perBankRdBursts::14 91699 # Per bank write bursts +system.physmem.perBankRdBursts::15 98506 # Per bank write bursts +system.physmem.perBankWrBursts::0 83240 # Per bank write bursts +system.physmem.perBankWrBursts::1 87253 # Per bank write bursts +system.physmem.perBankWrBursts::2 86416 # Per bank write bursts +system.physmem.perBankWrBursts::3 83797 # Per bank write bursts +system.physmem.perBankWrBursts::4 90075 # Per bank write bursts +system.physmem.perBankWrBursts::5 95693 # Per bank write bursts +system.physmem.perBankWrBursts::6 84431 # Per bank write bursts +system.physmem.perBankWrBursts::7 87097 # Per bank write bursts +system.physmem.perBankWrBursts::8 83064 # Per bank write bursts +system.physmem.perBankWrBursts::9 88599 # Per bank write bursts +system.physmem.perBankWrBursts::10 84727 # Per bank write bursts +system.physmem.perBankWrBursts::11 86277 # Per bank write bursts +system.physmem.perBankWrBursts::12 82015 # Per bank write bursts +system.physmem.perBankWrBursts::13 84756 # Per bank write bursts +system.physmem.perBankWrBursts::14 80845 # Per bank write bursts +system.physmem.perBankWrBursts::15 85787 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 26 # Number of times write queue was full causing retry -system.physmem.totGap 51667488071000 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times write queue was full causing retry +system.physmem.totGap 51667597819500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1639040 # Read request sizes (log2) +system.physmem.readPktSize::6 1645654 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1366243 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1313990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 317969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1373773 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1321004 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 317364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 669 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,163 +159,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 65910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 80385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 82507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 82508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 83232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 83418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 85151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 84166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 84814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 89146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 84019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 82787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 91825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 82010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 83266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 79973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 15051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 65956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 81050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 83118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 82838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 83953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 83921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 85569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 84918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 85424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 90109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 84668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 83357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 92346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 82532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 83696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 80480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 648381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.579894 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.167741 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.754919 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 255622 39.42% 39.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 156386 24.12% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 60110 9.27% 72.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34859 5.38% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25315 3.90% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 18876 2.91% 85.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13882 2.14% 87.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 12930 1.99% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 70401 10.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 648381 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 79285 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.660314 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 283.326654 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 79282 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::42 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 31 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 648118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.103938 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.284544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.148793 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 253468 39.11% 39.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 156556 24.16% 63.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 60545 9.34% 72.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 34961 5.39% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 26042 4.02% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 18689 2.88% 84.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14146 2.18% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13035 2.01% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 70676 10.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 648118 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 79768 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.619672 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 282.463170 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 79765 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 79285 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 79285 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.235795 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.792425 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.378813 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 77022 97.15% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 299 0.38% 97.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 59 0.07% 97.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 299 0.38% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 54 0.07% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 317 0.40% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 225 0.28% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 23 0.03% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 58 0.07% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 133 0.17% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 25 0.03% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 40 0.05% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 480 0.61% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 17 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 132 0.17% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 8 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 79768 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 79768 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.225855 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.793439 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.200790 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 77436 97.08% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 326 0.41% 97.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 71 0.09% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 315 0.39% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 43 0.05% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 360 0.45% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 211 0.26% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 25 0.03% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 65 0.08% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 125 0.16% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 20 0.03% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 34 0.04% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 501 0.63% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 33 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 30 0.04% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 120 0.15% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 8 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 23 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 79285 # Writes before turning the bus around for reads -system.physmem.totQLat 26536419219 # Total ticks spent queuing -system.physmem.totMemAccLat 57250850469 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8190515000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16199.48 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 79768 # Writes before turning the bus around for reads +system.physmem.totQLat 26467861730 # Total ticks spent queuing +system.physmem.totMemAccLat 57307730480 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8223965000 # Total ticks spent in databus transfers +system.physmem.avgQLat 16091.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34949.48 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.03 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.69 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.03 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.69 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34841.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.04 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.70 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.70 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing -system.physmem.readRowHits 1330988 # Number of row buffer hits during reads -system.physmem.writeRowHits 1025273 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.03 # Row buffer hit rate for writes -system.physmem.avgGap 17177428.18 # Average gap between requests -system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2459736720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1342118250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6223136400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4424051520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3374668883040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1319911106400 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29842673702250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34551702734580 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.732053 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49645039210452 # Time in different power states -system.physmem_0.memoryStateTime::REF 1725290840000 # Time in different power states +system.physmem.avgWrQLen 23.70 # Average write queue length when enqueuing +system.physmem.readRowHits 1338706 # Number of row buffer hits during reads +system.physmem.writeRowHits 1032034 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes +system.physmem.avgGap 17097068.62 # Average gap between requests +system.physmem.pageHitRate 78.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2524404960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1377403500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6364503600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4523001120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3374676002880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1325410671600 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29837914926750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34552790914410 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.751704 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49637080843701 # Time in different power states +system.physmem_0.memoryStateTime::REF 1725294480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 297159003548 # Time in different power states +system.physmem_0.memoryStateTime::ACT 305218373299 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2442023640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1332453375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6554020200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4431127680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3374668883040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1320412056885 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29842234272000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34552074836820 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.739255 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49644231851772 # Time in different power states -system.physmem_1.memoryStateTime::REF 1725290840000 # Time in different power states +system.physmem_1.actEnergy 2375306640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1296050250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6464827200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4380881760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3374676002880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1318079999925 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29844345348750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34551618417405 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.729010 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49647781129555 # Time in different power states +system.physmem_1.memoryStateTime::REF 1725294480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 297961425728 # Time in different power states +system.physmem_1.memoryStateTime::ACT 294523106445 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -339,15 +337,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 252436095 # Number of BP lookups -system.cpu.branchPred.condPredicted 176405196 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11951074 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 185535740 # Number of BTB lookups -system.cpu.branchPred.BTBHits 131467669 # Number of BTB hits +system.cpu.branchPred.lookups 252640803 # Number of BP lookups +system.cpu.branchPred.condPredicted 176566458 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11942340 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 185523828 # Number of BTB lookups +system.cpu.branchPred.BTBHits 131623059 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.858407 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30937069 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2133020 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.946714 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30927608 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2129490 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -378,63 +376,63 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 560363 # Table walker walks requested -system.cpu.dtb.walker.walksLong 560363 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20601 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178609 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 560363 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 560363 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 560363 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 199210 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 27145.243713 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 23005.972162 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20907.221064 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 196938 98.86% 98.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 98.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1933 0.97% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 52 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 120 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 58 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 84 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 561342 # Table walker walks requested +system.cpu.dtb.walker.walksLong 561342 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20890 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 179371 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 561342 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 561342 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 561342 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 200261 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 26959.987217 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 22796.816332 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20928.483641 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 197960 98.85% 98.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 3 0.00% 98.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1973 0.99% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 53 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 114 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 41 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 90 0.04% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 199210 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -1571833592 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -1571833592 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -1571833592 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 178610 89.66% 89.66% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 20601 10.34% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 199211 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560363 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 200261 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 179372 89.57% 89.57% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 20890 10.43% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 200262 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 561342 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560363 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199211 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 561342 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 200262 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199211 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 759574 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 200262 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 761604 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 178192284 # DTB read hits -system.cpu.dtb.read_misses 462603 # DTB read misses -system.cpu.dtb.write_hits 157870024 # DTB write hits -system.cpu.dtb.write_misses 97760 # DTB write misses +system.cpu.dtb.read_hits 178417728 # DTB read hits +system.cpu.dtb.read_misses 463663 # DTB read misses +system.cpu.dtb.write_hits 158017805 # DTB write hits +system.cpu.dtb.write_misses 97679 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 45300 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 78455 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1375 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14585 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 77601 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1384 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14410 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23059 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 178654887 # DTB read accesses -system.cpu.dtb.write_accesses 157967784 # DTB write accesses +system.cpu.dtb.perms_faults 23069 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 178881391 # DTB read accesses +system.cpu.dtb.write_accesses 158115484 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 336062308 # DTB hits -system.cpu.dtb.misses 560363 # DTB misses -system.cpu.dtb.accesses 336622671 # DTB accesses +system.cpu.dtb.hits 336435533 # DTB hits +system.cpu.dtb.misses 561342 # DTB misses +system.cpu.dtb.accesses 336996875 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -464,183 +462,190 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 134893 # Table walker walks requested -system.cpu.itb.walker.walksLong 134893 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1070 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 117642 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 134893 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 134893 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 134893 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 118712 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 30207.312656 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 25802.029077 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 23121.543530 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 116190 97.88% 97.88% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 6 0.01% 97.88% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 2295 1.93% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 67 0.06% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 109 0.09% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 28 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 118712 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -1572850092 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -1572850092 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -1572850092 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 117642 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1070 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 118712 # Table walker page sizes translated +system.cpu.itb.walker.walks 135051 # Table walker walks requested +system.cpu.itb.walker.walksLong 135051 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1071 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 117673 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 135051 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 135051 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 135051 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 118744 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 30328.088156 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 25835.192345 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 23534.472369 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-32767 58823 49.54% 49.54% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-65535 57227 48.19% 97.73% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-98303 2 0.00% 97.73% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-131071 5 0.00% 97.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-163839 2006 1.69% 99.43% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::163840-196607 464 0.39% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-229375 29 0.02% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::229376-262143 32 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-294911 88 0.07% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::294912-327679 29 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-360447 14 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::360448-393215 13 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-425983 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 118744 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 117673 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1071 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 118744 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134893 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 134893 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135051 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 135051 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118712 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 118712 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 253605 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 438788360 # ITB inst hits -system.cpu.itb.inst_misses 134893 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118744 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 118744 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 253795 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 439141642 # ITB inst hits +system.cpu.itb.inst_misses 135051 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 45300 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 56501 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 55572 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 359579 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 356769 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 438923253 # ITB inst accesses -system.cpu.itb.hits 438788360 # DTB hits -system.cpu.itb.misses 134893 # DTB misses -system.cpu.itb.accesses 438923253 # DTB accesses -system.cpu.numCycles 2560804207 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 439276693 # ITB inst accesses +system.cpu.itb.hits 439141642 # DTB hits +system.cpu.itb.misses 135051 # DTB misses +system.cpu.itb.accesses 439276693 # DTB accesses +system.cpu.numCycles 2565959423 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 921716010 # Number of instructions committed -system.cpu.committedOps 1083032845 # Number of ops (including micro ops) committed -system.cpu.discardedOps 92871017 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7624 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100775316475 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.778301 # CPI: cycles per instruction -system.cpu.ipc 0.359932 # IPC: instructions per cycle +system.cpu.committedInsts 922648651 # Number of instructions committed +system.cpu.committedOps 1084091117 # Number of ops (including micro ops) committed +system.cpu.discardedOps 92858708 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7622 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100770378430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.781080 # CPI: cycles per instruction +system.cpu.ipc 0.359573 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16484 # number of quiesce instructions executed -system.cpu.tickCycles 1740208465 # Number of cycles that the object actually ticked -system.cpu.idleCycles 820595742 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 10718531 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.930101 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320228714 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10719043 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.874749 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7085883500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.930101 # Average occupied blocks per requestor +system.cpu.kern.inst.quiesce 16482 # number of quiesce instructions executed +system.cpu.tickCycles 1742118066 # Number of cycles that the object actually ticked +system.cpu.idleCycles 823841357 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 10735802 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.930082 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 320587267 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10736314 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.860087 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.930082 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1345217745 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1345217745 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 163909013 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 163909013 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 147410694 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 147410694 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 512357 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 512357 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 335795 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 335795 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3851860 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3851860 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4160801 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4160801 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 311319707 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 311319707 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 311832064 # number of overall hits -system.cpu.dcache.overall_hits::total 311832064 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6365428 # 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number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 321814796 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 323726610 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323726610 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037383 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037383 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027251 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027251 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.732005 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.732005 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786762 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786762 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074630 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074630 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 319227057000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 319227057000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 319227057000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 319227057000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 170493031 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 170493031 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 151687445 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 151687445 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1912558 # 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number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 324093034 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037394 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037394 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027248 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027248 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.732453 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.732453 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786540 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786540 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074098 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074098 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032612 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032612 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036743 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036743 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18423.283556 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18423.283556 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.601960 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.601960 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 68167.765715 # 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average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 67964.381395 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 67964.381395 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16654.109245 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16654.109245 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30238.979012 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30238.979012 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26681.201283 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26681.201283 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30377.716313 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30377.716313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26804.514918 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26804.514918 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,155 +654,155 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8229800 # number of writebacks -system.cpu.dcache.writebacks::total 8229800 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 778718 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 778718 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1821021 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1821021 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 152 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 152 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69509 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 69509 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2599739 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2599739 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2599739 # 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number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 95942539500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 95942539500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106127468000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 106127468000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26584469000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26584469000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 83210863500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 83210863500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3483152500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3483152500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96321163500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 96321163500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106904157500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 106904157500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26939627500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26939627500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 82952613500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 82952613500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3468831500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3468831500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202070007500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 202070007500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228654476500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 228654476500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831192500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831192500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5820427500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5820427500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11651620000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11651620000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032810 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032810 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015234 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015234 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.728061 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.728061 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786666 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786666 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057931 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057931 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203225321000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 203225321000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230164948500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230164948500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6198462000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6198462000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207588500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207588500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12406050500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12406050500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032858 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032858 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015240 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015240 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.728498 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.728498 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786450 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786450 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057254 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057254 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024534 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024534 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028689 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028689 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17173.352384 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17173.352384 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45969.691247 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45969.691247 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19099.163169 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19099.163169 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67170.593050 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67170.593050 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14444.583829 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14444.583829 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024563 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024563 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028717 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028717 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17193.824560 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17193.824560 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46243.562813 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46243.562813 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19335.206712 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19335.206712 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 66966.449614 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 66966.449614 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14546.989604 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14546.989604 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25593.546518 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25593.546518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24620.208709 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24620.208709 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173047.823248 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173047.823248 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172682.237584 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172682.237584 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 172865.006009 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 172865.006009 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25679.729391 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25679.729391 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24729.943615 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24729.943615 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183946.998249 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183946.998249 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184168.649499 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184168.649499 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184057.838672 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184057.838672 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24130706 # number of replacements -system.cpu.icache.tags.tagsinuse 511.872431 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 414285199 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24131218 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.168019 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 39477111500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.872431 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 24189642 # number of replacements +system.cpu.icache.tags.tagsinuse 511.872408 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 414582353 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24190154 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.138475 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 39504620500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.872408 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 133 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 462547654 # Number of tag accesses -system.cpu.icache.tags.data_accesses 462547654 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 414285199 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 414285199 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 414285199 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 414285199 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 414285199 # number of overall hits -system.cpu.icache.overall_hits::total 414285199 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24131228 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24131228 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24131228 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24131228 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24131228 # number of overall misses -system.cpu.icache.overall_misses::total 24131228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 326882606500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 326882606500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 326882606500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 326882606500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 326882606500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 326882606500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 438416427 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 438416427 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 438416427 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 438416427 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 438416427 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 438416427 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055042 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.055042 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.055042 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.055042 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.055042 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.055042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13546.041109 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13546.041109 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13546.041109 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13546.041109 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13546.041109 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13546.041109 # average overall miss latency +system.cpu.icache.tags.tag_accesses 462962680 # Number of tag accesses +system.cpu.icache.tags.data_accesses 462962680 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 414582353 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 414582353 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 414582353 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 414582353 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 414582353 # number of overall hits +system.cpu.icache.overall_hits::total 414582353 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24190164 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24190164 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24190164 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24190164 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24190164 # number of overall misses +system.cpu.icache.overall_misses::total 24190164 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 327340789000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 327340789000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 327340789000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 327340789000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 327340789000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 327340789000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 438772517 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 438772517 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 438772517 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 438772517 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 438772517 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13531.978907 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13531.978907 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -806,225 +811,230 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24131228 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24131228 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24131228 # 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average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128749.529981 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126912.324829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126721.485987 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122275.211142 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123498.723449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123406.052460 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126912.324829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126721.485987 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122275.211142 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123498.723449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123406.052460 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.118144 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160545.953646 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 131920.429970 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161163.783896 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161163.783896 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.118144 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 160854.910019 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 140154.161655 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122659.882783 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122659.882783 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122260.477888 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122260.477888 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124612.188374 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124612.188374 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128758.307897 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128758.307897 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126758.663366 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122260.477888 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123319.019255 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123252.158919 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126758.663366 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122260.477888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123319.019255 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123252.158919 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171445.217675 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136191.236658 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172650.551831 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172650.551831 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172047.965224 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146456.687717 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 70442734 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 35592438 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2280 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 70595106 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 35668602 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4412 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2257 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2257 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1728553 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33080077 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1731880 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33156424 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 9596069 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 26854364 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 48128 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 9613409 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24185917 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2732498 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 47963 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 48129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2260770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2260770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24131228 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7228389 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1345463 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1238799 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72494093 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32387839 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 691084 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2167479 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 107740495 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1547746112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1133685906 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2304392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7423736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2691160146 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2148445 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 73231054 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009642 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.097721 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 47964 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2264033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2264033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24190164 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7242479 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1345383 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1238719 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72670859 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32439334 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 687653 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2163740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 107961586 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3099416704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1135424530 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2273208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7370944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4244485386 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2167477 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 38466398 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018246 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.133841 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 72524927 99.04% 99.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 706127 0.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 37764532 98.18% 98.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 701866 1.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 73231054 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 44001619997 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 38466398 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 68278869995 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1484887 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1476392 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36281501081 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36370852681 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14914900069 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14941078957 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 403060948 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 403557888 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1239526970 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1242412419 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40325 # Transaction distribution -system.iobus.trans_dist::ReadResp 40325 # Transaction distribution +system.iobus.trans_dist::ReadReq 40327 # Transaction distribution +system.iobus.trans_dist::ReadResp 40327 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1249,11 +1260,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231012 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231012 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353796 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1270,104 +1281,104 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334480 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42171500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25807000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 170000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 34147000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 120500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 565802629 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565729644 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 42000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147772000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115486 # number of replacements -system.iocache.tags.tagsinuse 10.440024 # Cycle average of tags in use +system.iocache.tags.replacements 115488 # number of replacements +system.iocache.tags.tagsinuse 10.440019 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115504 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13160095292000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 13160148501000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.520841 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.919182 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.919178 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.220053 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.432449 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.652501 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039893 # Number of tag accesses -system.iocache.tags.data_accesses 1039893 # Number of data accesses +system.iocache.tags.tag_accesses 1039911 # Number of tag accesses +system.iocache.tags.data_accesses 1039911 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8842 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8879 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8840 # number of demand (read+write) misses -system.iocache.demand_misses::total 8880 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8842 # number of demand (read+write) misses +system.iocache.demand_misses::total 8882 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8840 # number of overall misses -system.iocache.overall_misses::total 8880 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1641330150 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1646399150 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8842 # number of overall misses +system.iocache.overall_misses::total 8882 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1658170108 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1663256608 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13825092479 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13825092479 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1641330150 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1646750150 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1641330150 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1646750150 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13863609036 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13863609036 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1658170108 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1663607608 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1658170108 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1663607608 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8842 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8879 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8840 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8880 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8842 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8882 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8840 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8880 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8842 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8882 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1381,55 +1392,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 185670.831448 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185467.967782 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 187533.375707 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 187324.767204 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129613.482328 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129613.482328 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 185670.831448 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 185444.836712 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 185670.831448 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 185444.836712 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32333 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129974.584077 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129974.584077 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 187533.375707 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 187301.014186 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 187533.375707 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 187301.014186 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34622 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3346 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3502 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.663180 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.886351 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8842 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8879 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8840 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8880 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8842 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8882 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8840 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8880 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1199330150 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1202549150 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8842 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8882 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1216070108 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1219306608 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8491892479 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8491892479 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1199330150 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1202750150 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1199330150 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1202750150 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8530409036 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8530409036 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1216070108 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1219507608 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1216070108 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1219507608 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1443,73 +1454,73 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135670.831448 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 135467.967782 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137533.375707 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 137324.767204 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79613.482328 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79613.482328 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 135670.831448 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 135444.836712 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 135670.831448 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 135444.836712 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79974.584077 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79974.584077 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 137533.375707 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 137301.014186 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 137533.375707 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 137301.014186 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 86006 # Transaction distribution -system.membus.trans_dist::ReadResp 526484 # Transaction distribution +system.membus.trans_dist::ReadResp 528253 # Transaction distribution system.membus.trans_dist::WriteReq 33706 # Transaction distribution system.membus.trans_dist::WriteResp 33706 # Transaction distribution -system.membus.trans_dist::Writeback 1366243 # Transaction distribution -system.membus.trans_dist::CleanEvict 236394 # Transaction distribution -system.membus.trans_dist::UpgradeReq 38482 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1373773 # Transaction distribution +system.membus.trans_dist::CleanEvict 233285 # Transaction distribution +system.membus.trans_dist::UpgradeReq 38308 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 38483 # Transaction distribution -system.membus.trans_dist::ReadExReq 1149637 # Transaction distribution -system.membus.trans_dist::ReadExResp 1149637 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 440478 # Transaction distribution +system.membus.trans_dist::UpgradeResp 38309 # Transaction distribution +system.membus.trans_dist::ReadExReq 1154179 # Transaction distribution +system.membus.trans_dist::ReadExResp 1154179 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 442247 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4838609 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4968261 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340944 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 340944 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5309205 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4854992 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4984644 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5326203 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185140076 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 185310482 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7218752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7218752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192529234 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3380 # Total snoops (count) -system.membus.snoop_fanout::samples 3460550 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 186025772 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 186196178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7238272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7238272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 193434450 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3077 # Total snoops (count) +system.membus.snoop_fanout::samples 3470793 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3460550 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3470793 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3460550 # Request fanout histogram -system.membus.reqLayer0.occupancy 102447500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3470793 # Request fanout histogram +system.membus.reqLayer0.occupancy 102553500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5490500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5511000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9255992894 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9297161713 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8767241103 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8798501817 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228448107 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 227863618 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted |