diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt | 2806 |
1 files changed, 1408 insertions, 1398 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index 4faaeac69..43d314d14 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 51.327140 # Number of seconds simulated -sim_ticks 51327140089000 # Number of ticks simulated -final_tick 51327140089000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 51327139864000 # Number of ticks simulated +final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155840 # Simulator instruction rate (inst/s) -host_op_rate 183117 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9430836418 # Simulator tick rate (ticks/s) -host_mem_usage 687516 # Number of bytes of host memory used -host_seconds 5442.48 # Real time elapsed on the host -sim_insts 848158120 # Number of instructions simulated -sim_ops 996609834 # Number of ops (including micro ops) simulated +host_inst_rate 122613 # Simulator instruction rate (inst/s) +host_op_rate 144072 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7419967145 # Simulator tick rate (ticks/s) +host_mem_usage 687012 # Number of bytes of host memory used +host_seconds 6917.44 # Real time elapsed on the host +sim_insts 848164321 # Number of instructions simulated +sim_ops 996610207 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 211968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 207872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5637664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 41611720 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 447104 # Number of bytes read from this memory -system.physmem.bytes_read::total 48116328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5637664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5637664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68318336 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 41583048 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 443008 # Number of bytes read from this memory +system.physmem.bytes_read::total 48132008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5661728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5661728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 68386496 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 68338916 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3312 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3248 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 104041 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 650196 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6986 # Number of read requests responded to by this memory -system.physmem.num_reads::total 767783 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1067474 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 68407076 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 104417 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 649748 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6922 # Number of read requests responded to by this memory +system.physmem.num_reads::total 768028 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1068539 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1070047 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 109838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 810716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 937444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 109838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 109838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1331037 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1071112 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 110307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 810157 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 937750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 110307 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 110307 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1332365 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1331438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1331037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 109838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 811117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2268882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 767783 # Number of read requests accepted -system.physmem.writeReqs 1070047 # Number of write requests accepted -system.physmem.readBursts 767783 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1070047 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 49097152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 40960 # Total number of bytes read from write queue -system.physmem.bytesWritten 68336896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 48116328 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 68338916 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 640 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2264 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1332766 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1332365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 110307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 810558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2270516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 768028 # Number of read requests accepted +system.physmem.writeReqs 1071112 # Number of write requests accepted +system.physmem.readBursts 768028 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1071112 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 49106944 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 46848 # Total number of bytes read from write queue +system.physmem.bytesWritten 68406272 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 48132008 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 68407076 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 732 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 44980 # Per bank write bursts -system.physmem.perBankRdBursts::1 51602 # Per bank write bursts -system.physmem.perBankRdBursts::2 47368 # Per bank write bursts -system.physmem.perBankRdBursts::3 43602 # Per bank write bursts -system.physmem.perBankRdBursts::4 45132 # Per bank write bursts -system.physmem.perBankRdBursts::5 50541 # Per bank write bursts -system.physmem.perBankRdBursts::6 45264 # Per bank write bursts -system.physmem.perBankRdBursts::7 48215 # Per bank write bursts -system.physmem.perBankRdBursts::8 45181 # Per bank write bursts -system.physmem.perBankRdBursts::9 71916 # Per bank write bursts -system.physmem.perBankRdBursts::10 43746 # Per bank write bursts -system.physmem.perBankRdBursts::11 51986 # Per bank write bursts -system.physmem.perBankRdBursts::12 43936 # Per bank write bursts -system.physmem.perBankRdBursts::13 46943 # Per bank write bursts -system.physmem.perBankRdBursts::14 42923 # Per bank write bursts -system.physmem.perBankRdBursts::15 43808 # Per bank write bursts -system.physmem.perBankWrBursts::0 64378 # Per bank write bursts -system.physmem.perBankWrBursts::1 68822 # Per bank write bursts -system.physmem.perBankWrBursts::2 67360 # Per bank write bursts -system.physmem.perBankWrBursts::3 65401 # Per bank write bursts -system.physmem.perBankWrBursts::4 67058 # Per bank write bursts -system.physmem.perBankWrBursts::5 69359 # Per bank write bursts -system.physmem.perBankWrBursts::6 64813 # Per bank write bursts -system.physmem.perBankWrBursts::7 68136 # Per bank write bursts -system.physmem.perBankWrBursts::8 65855 # Per bank write bursts -system.physmem.perBankWrBursts::9 70723 # Per bank write bursts -system.physmem.perBankWrBursts::10 64194 # Per bank write bursts -system.physmem.perBankWrBursts::11 71056 # Per bank write bursts -system.physmem.perBankWrBursts::12 64787 # Per bank write bursts -system.physmem.perBankWrBursts::13 67120 # Per bank write bursts -system.physmem.perBankWrBursts::14 64460 # Per bank write bursts -system.physmem.perBankWrBursts::15 64242 # Per bank write bursts +system.physmem.perBankRdBursts::0 45073 # Per bank write bursts +system.physmem.perBankRdBursts::1 51507 # Per bank write bursts +system.physmem.perBankRdBursts::2 47331 # Per bank write bursts +system.physmem.perBankRdBursts::3 43047 # Per bank write bursts +system.physmem.perBankRdBursts::4 45469 # Per bank write bursts +system.physmem.perBankRdBursts::5 51901 # Per bank write bursts +system.physmem.perBankRdBursts::6 46387 # Per bank write bursts +system.physmem.perBankRdBursts::7 47163 # Per bank write bursts +system.physmem.perBankRdBursts::8 43832 # Per bank write bursts +system.physmem.perBankRdBursts::9 71407 # Per bank write bursts +system.physmem.perBankRdBursts::10 44269 # Per bank write bursts +system.physmem.perBankRdBursts::11 52269 # Per bank write bursts +system.physmem.perBankRdBursts::12 42900 # Per bank write bursts +system.physmem.perBankRdBursts::13 46591 # Per bank write bursts +system.physmem.perBankRdBursts::14 43222 # Per bank write bursts +system.physmem.perBankRdBursts::15 44928 # Per bank write bursts +system.physmem.perBankWrBursts::0 64149 # Per bank write bursts +system.physmem.perBankWrBursts::1 68917 # Per bank write bursts +system.physmem.perBankWrBursts::2 66979 # Per bank write bursts +system.physmem.perBankWrBursts::3 64863 # Per bank write bursts +system.physmem.perBankWrBursts::4 67442 # Per bank write bursts +system.physmem.perBankWrBursts::5 70404 # Per bank write bursts +system.physmem.perBankWrBursts::6 66306 # Per bank write bursts +system.physmem.perBankWrBursts::7 67867 # Per bank write bursts +system.physmem.perBankWrBursts::8 65614 # Per bank write bursts +system.physmem.perBankWrBursts::9 70732 # Per bank write bursts +system.physmem.perBankWrBursts::10 65165 # Per bank write bursts +system.physmem.perBankWrBursts::11 71475 # Per bank write bursts +system.physmem.perBankWrBursts::12 63578 # Per bank write bursts +system.physmem.perBankWrBursts::13 66114 # Per bank write bursts +system.physmem.perBankWrBursts::14 64356 # Per bank write bursts +system.physmem.perBankWrBursts::15 64887 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 33 # Number of times write queue was full causing retry -system.physmem.totGap 51327138675500 # Total gap between requests +system.physmem.numWrRetry 30 # Number of times write queue was full causing retry +system.physmem.totGap 51327138450500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 746498 # Read request sizes (log2) +system.physmem.readPktSize::6 746743 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1067474 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 514277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 203743 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1068539 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 514973 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 203448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13041 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -159,125 +159,126 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 69991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 63900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 76806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 64795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 68451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 58974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 57166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 471185 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.230345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 149.487407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.645433 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 207601 44.06% 44.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 122052 25.90% 69.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 43152 9.16% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22522 4.78% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14798 3.14% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9568 2.03% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7612 1.62% 90.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6084 1.29% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 37796 8.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 471185 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 54136 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.170570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 76.787361 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 54130 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 3 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 26679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 69964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 64040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 77106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 64857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 68599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 58973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 57173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 471440 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.263737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 149.464196 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 290.749786 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 207824 44.08% 44.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 122155 25.91% 69.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 42779 9.07% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22709 4.82% 83.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14933 3.17% 87.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9495 2.01% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7568 1.61% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6030 1.28% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 37947 8.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 471440 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 54191 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.158790 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 76.596487 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 54185 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 54136 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 54136 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.723733 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.769647 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.988954 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 40635 75.06% 75.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4496 8.31% 83.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 5195 9.60% 92.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1325 2.45% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 409 0.76% 96.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 232 0.43% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 326 0.60% 97.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 142 0.26% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 398 0.74% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 127 0.23% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 56 0.10% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 67 0.12% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 319 0.59% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 37 0.07% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 24 0.04% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 111 0.21% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 168 0.31% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 5 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 54191 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 54191 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.723718 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.774638 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.948432 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 40576 74.88% 74.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4593 8.48% 83.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 5177 9.55% 92.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1373 2.53% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 420 0.78% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 248 0.46% 96.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 301 0.56% 97.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 130 0.24% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 393 0.73% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 142 0.26% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 38 0.07% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 61 0.11% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 323 0.60% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 40 0.07% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 24 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 111 0.20% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 181 0.33% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 17 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 54136 # Writes before turning the bus around for reads -system.physmem.totQLat 15242803686 # Total ticks spent queuing -system.physmem.totMemAccLat 29626734936 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3835715000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19869.57 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 54191 # Writes before turning the bus around for reads +system.physmem.totQLat 15195806089 # Total ticks spent queuing +system.physmem.totMemAccLat 29582606089 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3836480000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19804.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38619.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38554.36 # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s @@ -286,41 +287,41 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing -system.physmem.readRowHits 579803 # Number of row buffer hits during reads -system.physmem.writeRowHits 783916 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.42 # Row buffer hit rate for writes -system.physmem.avgGap 27928121.03 # Average gap between requests +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing +system.physmem.readRowHits 579763 # Number of row buffer hits during reads +system.physmem.writeRowHits 784939 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.44 # Row buffer hit rate for writes +system.physmem.avgGap 27908228.00 # Average gap between requests system.physmem.pageHitRate 74.32 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1791077400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 977274375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2938244400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3468841200 # Energy for write commands per rank (pJ) +system.physmem_0.actEnergy 1800088920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 982191375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2947417200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3479286960 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1235175473835 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29712796340250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34309586468340 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.449224 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49429866192554 # Time in different power states +system.physmem_0.actBackEnergy 1235810088180 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29712239669250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34309697958765 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.451396 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49428932348966 # Time in different power states system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 183347171196 # Time in different power states +system.physmem_0.memoryStateTime::ACT 184281028534 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1771020720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 966330750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3045424200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3450165840 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 1763997480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 962498625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3037452600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3446848080 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1235608843410 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29712416191500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34309697193300 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.451381 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49429214230967 # Time in different power states +system.physmem_1.actBackEnergy 1235330422065 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29712660420750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34309640856480 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.450284 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49429628001327 # Time in different power states system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 183999255033 # Time in different power states +system.physmem_1.memoryStateTime::ACT 183585648673 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -344,15 +345,19 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 224297572 # Number of BP lookups -system.cpu.branchPred.condPredicted 149902957 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12193787 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158452721 # Number of BTB lookups -system.cpu.branchPred.BTBHits 103491021 # Number of BTB hits +system.cpu.branchPred.lookups 225024609 # Number of BP lookups +system.cpu.branchPred.condPredicted 149819801 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12305268 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158924221 # Number of BTB lookups +system.cpu.branchPred.BTBHits 98148969 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.313502 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30817326 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 343319 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.758345 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30872234 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 343569 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6729545 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4744517 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1985028 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 766036 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -383,45 +388,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 197812 # Table walker walks requested -system.cpu.checker.dtb.walker.walksLong 197812 # Table walker walks initiated with long descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 197812 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 197812 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 197812 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walks 197728 # Table walker walks requested +system.cpu.checker.dtb.walker.walksLong 197728 # Table walker walks initiated with long descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 197728 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 197728 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 197728 # Table walker wait (enqueue to first request) latency system.cpu.checker.dtb.walker.walksPending::samples -1584953796 # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::0 -1584953796 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::total -1584953796 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 154082 91.53% 91.53% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::2M 14256 8.47% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 168338 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 197812 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkPageSizes::4K 154026 91.54% 91.54% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::2M 14228 8.46% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 168254 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 197728 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 197812 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 168338 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 197728 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 168254 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 168338 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 366150 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 168254 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 365982 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 159555068 # DTB read hits -system.cpu.checker.dtb.read_misses 147115 # DTB read misses -system.cpu.checker.dtb.write_hits 144752666 # DTB write hits -system.cpu.checker.dtb.write_misses 50697 # DTB write misses +system.cpu.checker.dtb.read_hits 159555012 # DTB read hits +system.cpu.checker.dtb.read_misses 147105 # DTB read misses +system.cpu.checker.dtb.write_hits 144753445 # DTB write hits +system.cpu.checker.dtb.write_misses 50623 # DTB write misses system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 71773 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 71788 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 6971 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 6683 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 19053 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 159702183 # DTB read accesses -system.cpu.checker.dtb.write_accesses 144803363 # DTB write accesses +system.cpu.checker.dtb.read_accesses 159702117 # DTB read accesses +system.cpu.checker.dtb.write_accesses 144804068 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 304307734 # DTB hits -system.cpu.checker.dtb.misses 197812 # DTB misses -system.cpu.checker.dtb.accesses 304505546 # DTB accesses +system.cpu.checker.dtb.hits 304308457 # DTB hits +system.cpu.checker.dtb.misses 197728 # DTB misses +system.cpu.checker.dtb.accesses 304506185 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -451,26 +456,26 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.walks 119797 # Table walker walks requested -system.cpu.checker.itb.walker.walksLong 119797 # Table walker walks initiated with long descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 119797 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 119797 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 119797 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walks 119805 # Table walker walks requested +system.cpu.checker.itb.walker.walksLong 119805 # Table walker walks initiated with long descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 119805 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 119805 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 119805 # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walksPending::samples -1586149296 # Table walker pending requests distribution system.cpu.checker.itb.walker.walksPending::0 -1586149296 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.itb.walker.walksPending::total -1586149296 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 107938 98.83% 98.83% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::4K 107946 98.83% 98.83% # Table walker page sizes translated system.cpu.checker.itb.walker.walkPageSizes::2M 1280 1.17% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 109218 # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 109226 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119797 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119797 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119805 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119805 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109218 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109218 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 229015 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 848564500 # ITB inst hits -system.cpu.checker.itb.inst_misses 119797 # ITB inst misses +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109226 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109226 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 229031 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 848570685 # ITB inst hits +system.cpu.checker.itb.inst_misses 119805 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits @@ -479,18 +484,18 @@ system.cpu.checker.itb.flush_tlb 20 # Nu system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 51743 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_entries 51713 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 848684297 # ITB inst accesses -system.cpu.checker.itb.hits 848564500 # DTB hits -system.cpu.checker.itb.misses 119797 # DTB misses -system.cpu.checker.itb.accesses 848684297 # DTB accesses -system.cpu.checker.numCycles 997179136 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 848690490 # ITB inst accesses +system.cpu.checker.itb.hits 848570685 # DTB hits +system.cpu.checker.itb.misses 119805 # DTB misses +system.cpu.checker.itb.accesses 848690490 # DTB accesses +system.cpu.checker.numCycles 997179501 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -522,85 +527,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 949838 # Table walker walks requested -system.cpu.dtb.walker.walksLong 949838 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15818 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155419 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 436827 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 513011 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2225.817770 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 14567.134273 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 509618 99.34% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 1930 0.38% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 987 0.19% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 197 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 149 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 32 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 53 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 947007 # Table walker walks requested +system.cpu.dtb.walker.walksLong 947007 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15816 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155482 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 435407 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 511600 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2285.571736 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 14838.819778 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 508020 99.30% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 2030 0.40% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 1046 0.20% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 222 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 147 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 54 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::458752-524287 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 513011 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 485512 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23036.801356 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 18084.539614 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20755.830536 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 474265 97.68% 97.68% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 7843 1.62% 99.30% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2427 0.50% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 166 0.03% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 551 0.11% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 105 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 109 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 485512 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 779669132376 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.722626 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.523315 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 777439658376 99.71% 99.71% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1176099000 0.15% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 488850000 0.06% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 205535000 0.03% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 152105500 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 121751500 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 29187500 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 53249500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2696000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 779669132376 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 155420 90.76% 90.76% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15818 9.24% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 171238 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 949838 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 511600 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 486864 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 22927.774491 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 17879.583197 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20925.745088 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 475438 97.65% 97.65% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 7837 1.61% 99.26% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2530 0.52% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 265 0.05% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 545 0.11% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 113 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 104 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 16 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 486864 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 779668807876 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.725507 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.522451 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 777433889876 99.71% 99.71% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1160253500 0.15% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 513477500 0.07% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 201866500 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 152233500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 119773500 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 32296000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 52448000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2569500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 779668807876 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 155483 90.77% 90.77% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15816 9.23% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 171299 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 947007 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 949838 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171238 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 947007 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171299 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171238 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1121076 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171299 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1118306 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 169331819 # DTB read hits -system.cpu.dtb.read_misses 674131 # DTB read misses -system.cpu.dtb.write_hits 147501461 # DTB write hits -system.cpu.dtb.write_misses 275707 # DTB write misses +system.cpu.dtb.read_hits 169398877 # DTB read hits +system.cpu.dtb.read_misses 674798 # DTB read misses +system.cpu.dtb.write_hits 147332912 # DTB write hits +system.cpu.dtb.write_misses 272209 # DTB write misses system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72020 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10130 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 72102 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69829 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 170005950 # DTB read accesses -system.cpu.dtb.write_accesses 147777168 # DTB write accesses +system.cpu.dtb.perms_faults 69070 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 170073675 # DTB read accesses +system.cpu.dtb.write_accesses 147605121 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 316833280 # DTB hits -system.cpu.dtb.misses 949838 # DTB misses -system.cpu.dtb.accesses 317783118 # DTB accesses +system.cpu.dtb.hits 316731789 # DTB hits +system.cpu.dtb.misses 947007 # DTB misses +system.cpu.dtb.accesses 317678796 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -630,62 +637,65 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 161333 # Table walker walks requested -system.cpu.itb.walker.walksLong 161333 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 121604 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17607 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 143726 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1329.870726 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9693.373994 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 142645 99.25% 99.25% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 592 0.41% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 67 0.05% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 93 0.06% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 270 0.19% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 24 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 162102 # Table walker walks requested +system.cpu.itb.walker.walksLong 162102 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1483 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 120022 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17916 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144186 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1142.128917 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9607.655205 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 143046 99.21% 99.21% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 588 0.41% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 94 0.07% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 159 0.11% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 224 0.16% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 44 0.03% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 143726 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 140644 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29101.756918 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24236.740283 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 22905.442201 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 137486 97.75% 97.75% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 886 0.63% 98.38% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1961 1.39% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 124 0.09% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 124 0.09% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 33 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 140644 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 672291747976 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.944017 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.230261 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 37693655356 5.61% 5.61% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 634541752620 94.38% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 55651000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 688000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 672291747976 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 121604 98.84% 98.84% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 123037 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::229376-262143 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144186 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 139421 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28788.855337 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23782.658152 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24182.866310 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 136254 97.73% 97.73% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 690 0.49% 98.22% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 2101 1.51% 99.73% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 136 0.10% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 151 0.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 47 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 30 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 139421 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 680881393568 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.947864 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.222600 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 35543211356 5.22% 5.22% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 645294358712 94.77% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 43207500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 580000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 36000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 680881393568 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 120022 98.78% 98.78% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1483 1.22% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 121505 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161333 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 161333 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162102 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 162102 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123037 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 123037 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 284370 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 356599136 # ITB inst hits -system.cpu.itb.inst_misses 161333 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121505 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 121505 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 283607 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 357007788 # ITB inst hits +system.cpu.itb.inst_misses 162102 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -694,261 +704,261 @@ system.cpu.itb.flush_tlb 20 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53042 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52913 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 369633 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 357575 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 356760469 # ITB inst accesses -system.cpu.itb.hits 356599136 # DTB hits -system.cpu.itb.misses 161333 # DTB misses -system.cpu.itb.accesses 356760469 # DTB accesses -system.cpu.numCycles 1628081885 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 357169890 # ITB inst accesses +system.cpu.itb.hits 357007788 # DTB hits +system.cpu.itb.misses 162102 # DTB misses +system.cpu.itb.accesses 357169890 # DTB accesses +system.cpu.numCycles 1631144067 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 644023121 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1000825975 # Number of instructions fetch has processed -system.cpu.fetch.Branches 224297572 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 134308347 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 897356081 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26042356 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3815311 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27434 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9297529 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1037208 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 977 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 356212596 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6096332 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 48851 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1568578839 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.747604 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.149571 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 646909214 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1002667158 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225024609 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133765720 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 898024303 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26265536 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3811072 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 29306 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8704800 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1028212 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 873 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 356634442 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6247312 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 47880 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1571640548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.747058 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.149321 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1011708684 64.50% 64.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 213717515 13.62% 78.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70499052 4.49% 82.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 272653588 17.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1013991405 64.52% 64.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 214266060 13.63% 78.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70309362 4.47% 82.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 273073721 17.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1568578839 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.137768 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.614727 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 523834599 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 552751170 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 433009950 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49764409 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9218711 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33629126 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3862659 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1084582874 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28977480 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9218711 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 568372766 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 66217937 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 371830406 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 438295981 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 114643038 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1064838864 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6775021 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5115924 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 336846 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 638712 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 63601510 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20546 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1012729668 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1640391275 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1259385666 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1476745 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 947192806 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65536859 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26910765 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23247835 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 101832167 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173436334 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 151069277 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9864131 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8951241 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1029826470 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27204925 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1045231227 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3279121 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60421557 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33664917 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 313528 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1568578839 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.666356 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.920348 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1571640548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.137955 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.614702 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 526349627 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 552086440 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 434104674 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49724049 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9375758 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33560071 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3814526 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1085977369 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29430616 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9375758 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 571292055 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 65924513 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 371563835 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 438965882 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 114518505 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1065686030 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6908876 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5086020 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 334343 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 634469 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 63514971 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20439 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1013378726 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1640198292 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1259502846 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1473679 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 947186300 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 66192423 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26900223 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23242764 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 101754926 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 173828486 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 150818351 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9879664 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8976205 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1030662331 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27200654 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1045735608 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3378731 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 61252774 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 34075299 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 309098 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1571640548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.665378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.919633 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 921654762 58.76% 58.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 333747896 21.28% 80.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234544221 14.95% 94.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72152324 4.60% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6460263 0.41% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19373 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 924076981 58.80% 58.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 334351644 21.27% 80.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234725096 14.94% 95.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72033056 4.58% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6434251 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19520 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1568578839 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1571640548 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57742950 35.03% 35.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 99825 0.06% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26740 0.02% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 625 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44231739 26.83% 61.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62727458 38.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57663018 35.01% 35.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 100158 0.06% 35.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26751 0.02% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 667 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44277065 26.88% 61.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62625013 38.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 719843938 68.87% 68.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2535420 0.24% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122954 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 380 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 121377 0.01% 69.14% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 720295550 68.88% 68.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2531326 0.24% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122856 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 375 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 119220 0.01% 69.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 173211987 16.57% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 149395124 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 173477536 16.59% 85.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 149188688 14.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1045231227 # Type of FU issued -system.cpu.iq.rate 0.642002 # Inst issue rate -system.cpu.iq.fu_busy_cnt 164829337 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157697 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3824665950 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1116644145 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1027372601 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2483800 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 950168 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 912054 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1208499896 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1560667 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4304106 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1045735608 # Type of FU issued +system.cpu.iq.rate 0.641106 # Inst issue rate +system.cpu.iq.fu_busy_cnt 164692672 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157490 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3828710884 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1118319185 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1027391540 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2472282 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 938392 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 909608 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1208873256 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1555013 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4278408 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13785862 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14456 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 142604 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6312817 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14178366 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14475 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 143083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6061186 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2532139 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1442341 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2527357 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1438792 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9218711 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7060342 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6923682 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1057253447 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9375758 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6990377 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6913711 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1058098003 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173436334 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 151069277 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22822922 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 57401 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6792645 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 142604 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3655399 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5100784 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8756183 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1034064574 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169319677 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10227871 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 173828486 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 150818351 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22818732 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 57696 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6782714 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 143083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3464744 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5492402 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8957146 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1034225316 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 169386893 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10574140 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222052 # number of nop insts executed -system.cpu.iew.exec_refs 316816486 # number of memory reference insts executed -system.cpu.iew.exec_branches 196206176 # Number of branches executed -system.cpu.iew.exec_stores 147496809 # Number of stores executed -system.cpu.iew.exec_rate 0.635143 # Inst execution rate -system.cpu.iew.wb_sent 1029092840 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1028284655 # cumulative count of insts written-back -system.cpu.iew.wb_producers 437786008 # num instructions producing a value -system.cpu.iew.wb_consumers 708231099 # num instructions consuming a value -system.cpu.iew.wb_rate 0.631593 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618140 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 51332329 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 26891397 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8391320 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1556613982 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.640242 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.274821 # Number of insts commited each cycle +system.cpu.iew.exec_nop 235018 # number of nop insts executed +system.cpu.iew.exec_refs 316715121 # number of memory reference insts executed +system.cpu.iew.exec_branches 196182084 # Number of branches executed +system.cpu.iew.exec_stores 147328228 # Number of stores executed +system.cpu.iew.exec_rate 0.634049 # Inst execution rate +system.cpu.iew.wb_sent 1029119140 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1028301148 # cumulative count of insts written-back +system.cpu.iew.wb_producers 437817967 # num instructions producing a value +system.cpu.iew.wb_consumers 708345311 # num instructions consuming a value +system.cpu.iew.wb_rate 0.630417 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618086 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 51892888 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 26891556 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8548258 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1559580721 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.639024 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.273898 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1044975044 67.13% 67.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 287768132 18.49% 85.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120346121 7.73% 93.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36551788 2.35% 95.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28453995 1.83% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14010396 0.90% 98.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8635881 0.55% 98.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4170150 0.27% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11702475 0.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1047836838 67.19% 67.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288037345 18.47% 85.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120098323 7.70% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36644408 2.35% 95.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28496008 1.83% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13936779 0.89% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8648827 0.55% 98.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4175441 0.27% 99.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11706752 0.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1556613982 # Number of insts commited each cycle -system.cpu.commit.committedInsts 848158120 # Number of instructions committed -system.cpu.commit.committedOps 996609834 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1559580721 # Number of insts commited each cycle +system.cpu.commit.committedInsts 848164321 # Number of instructions committed +system.cpu.commit.committedOps 996610207 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 304406931 # Number of memory references committed -system.cpu.commit.loads 159650471 # Number of loads committed -system.cpu.commit.membars 6926449 # Number of memory barriers committed -system.cpu.commit.branches 189300112 # Number of branches committed -system.cpu.commit.fp_insts 898776 # Number of committed floating point instructions. -system.cpu.commit.int_insts 915651780 # Number of committed integer instructions. -system.cpu.commit.function_calls 25280403 # Number of function calls committed. +system.cpu.commit.refs 304407284 # Number of memory references committed +system.cpu.commit.loads 159650119 # Number of loads committed +system.cpu.commit.membars 6926917 # Number of memory barriers committed +system.cpu.commit.branches 189306416 # Number of branches committed +system.cpu.commit.fp_insts 898488 # Number of committed floating point instructions. +system.cpu.commit.int_insts 915651510 # Number of committed integer instructions. +system.cpu.commit.function_calls 25281717 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 689842559 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2150231 0.22% 69.43% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98139 0.01% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 689843263 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2149527 0.22% 69.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98159 0.01% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction @@ -975,537 +985,537 @@ system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 159650471 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 144756460 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 159650119 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 144757165 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 996609834 # Class of committed instruction -system.cpu.commit.bw_lim_events 11702475 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2585312705 # The number of ROB reads -system.cpu.rob.rob_writes 2107755396 # The number of ROB writes -system.cpu.timesIdled 8146940 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59503046 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101026198411 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 848158120 # Number of Instructions Simulated -system.cpu.committedOps 996609834 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.919550 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.919550 # CPI: Total CPI of All Threads -system.cpu.ipc 0.520955 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.520955 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1224113620 # number of integer regfile reads -system.cpu.int_regfile_writes 731134071 # number of integer regfile writes -system.cpu.fp_regfile_reads 1465257 # number of floating regfile reads -system.cpu.fp_regfile_writes 785096 # number of floating regfile writes -system.cpu.cc_regfile_reads 225210240 # number of cc regfile reads -system.cpu.cc_regfile_writes 225863400 # number of cc regfile writes -system.cpu.misc_regfile_reads 2555640420 # number of misc regfile reads -system.cpu.misc_regfile_writes 26930775 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9682749 # number of replacements +system.cpu.commit.op_class_0::total 996610207 # Class of committed instruction +system.cpu.commit.bw_lim_events 11706752 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2588836198 # The number of ROB reads +system.cpu.rob.rob_writes 2108972650 # The number of ROB writes +system.cpu.timesIdled 8176252 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59503519 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101023135782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 848164321 # Number of Instructions Simulated +system.cpu.committedOps 996610207 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.923146 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.923146 # CPI: Total CPI of All Threads +system.cpu.ipc 0.519981 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.519981 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1223740669 # number of integer regfile reads +system.cpu.int_regfile_writes 731349876 # number of integer regfile writes +system.cpu.fp_regfile_reads 1462624 # number of floating regfile reads +system.cpu.fp_regfile_writes 780384 # number of floating regfile writes +system.cpu.cc_regfile_reads 225040074 # number of cc regfile reads +system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes +system.cpu.misc_regfile_reads 2558050181 # number of misc regfile reads +system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9706309 # number of replacements system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 283083620 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9683261 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.234327 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9706821 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.171088 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1236470793 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1236470793 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 147113779 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147113779 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128236098 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128236098 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 377977 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 377977 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 323653 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 323653 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3296961 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3296961 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3691090 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3691090 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 275349877 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 275349877 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 275727854 # number of overall hits -system.cpu.dcache.overall_hits::total 275727854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9547222 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9547222 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11260039 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11260039 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1170114 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1170114 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1233803 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1233803 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 446138 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 446138 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 20807261 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20807261 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21977375 # number of overall misses -system.cpu.dcache.overall_misses::total 21977375 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 168019956500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 168019956500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 444932022751 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 444932022751 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52262346938 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 52262346938 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6889431000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6889431000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 285500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 285500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 612951979251 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 612951979251 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 612951979251 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 612951979251 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 156661001 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 156661001 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 139496137 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 139496137 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548091 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1548091 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1236907465 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1236907465 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 147182281 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147182281 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128244124 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128244124 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 377753 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 377753 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 323466 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 323466 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295516 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3295516 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3691142 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3691142 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 275426405 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 275426405 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 275804158 # number of overall hits +system.cpu.dcache.overall_hits::total 275804158 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9582006 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9582006 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11252664 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11252664 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1170750 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1170750 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1233990 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1233990 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 446459 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 446459 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 20834670 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20834670 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22005420 # number of overall misses +system.cpu.dcache.overall_misses::total 22005420 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 168553352000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 168553352000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 444283559827 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 444283559827 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52343559973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 52343559973 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6881905000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6881905000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 299500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 299500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 612836911827 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 612836911827 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 612836911827 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 612836911827 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 156764287 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 156764287 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 139496788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 139496788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548503 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1548503 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557456 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 1557456 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3743099 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3743099 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691096 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3691096 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 296157138 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 296157138 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 297705229 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 297705229 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060942 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060942 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080719 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080719 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.755843 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.755843 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792191 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.792191 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119189 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119189 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3741975 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3741975 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691149 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3691149 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 296261075 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 296261075 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 297809578 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 297809578 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061124 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061124 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080666 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080666 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756053 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.756053 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792311 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.792311 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119311 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119311 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.070258 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.070258 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.073823 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.073823 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17598.832048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17598.832048 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39514.252371 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39514.252371 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42358.745228 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42358.745228 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15442.376574 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15442.376574 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47583.333333 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47583.333333 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29458.561569 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29458.561569 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27890.136072 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27890.136072 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32144751 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.070325 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.070325 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.073891 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.073891 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17590.612237 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17590.612237 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39482.522523 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39482.522523 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42418.139509 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42418.139509 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15414.416553 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15414.416553 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42785.714286 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42785.714286 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29414.284547 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29414.284547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27849.362195 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27849.362195 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32180640 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1600072 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1601871 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089565 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089408 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7504258 # number of writebacks -system.cpu.dcache.writebacks::total 7504258 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4442516 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4442516 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9255736 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9255736 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7058 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 7058 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218425 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 218425 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13698252 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13698252 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13698252 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13698252 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5104706 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5104706 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2004303 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2004303 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163297 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1163297 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226745 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1226745 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227713 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 227713 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7109009 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7109009 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8272306 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8272306 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7511281 # number of writebacks +system.cpu.dcache.writebacks::total 7511281 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4454269 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4454269 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9249122 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9249122 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7130 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 7130 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218050 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 218050 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13703391 # 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number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50594844438 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3209583500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3209583500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 279500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 279500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162383650390 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 162383650390 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186032339390 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 186032339390 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191842000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191842000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228406964 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228406964 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420248964 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420248964 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032584 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032584 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014368 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014368 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751440 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751440 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787659 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787659 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060835 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060835 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84965736000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 84965736000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77538140437 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77538140437 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23685156500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23685156500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50670413473 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50670413473 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3210622500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3210622500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 292500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 292500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162503876437 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 162503876437 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186189032937 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 186189032937 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192022000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192022000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228178464 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228178464 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420200464 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420200464 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032710 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032710 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014363 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014363 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751653 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751653 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787733 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787733 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061040 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061040 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024004 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024004 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027787 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027787 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16594.683220 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16594.683220 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38752.958704 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38752.958704 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20329.020878 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20329.020878 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41243.163362 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41243.163362 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14094.862832 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14094.862832 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46583.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46583.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22841.953132 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22841.953132 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22488.570828 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22488.570828 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183854.207495 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183854.207495 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184841.137346 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184841.137346 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.804257 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.804257 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024071 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024071 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027854 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027854 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38700.531577 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38700.531577 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20349.173967 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20349.173967 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41300.892908 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41300.892908 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14056.462311 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22787.479839 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22787.479839 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.350783 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.350783 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184834.356125 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184834.356125 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.084395 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.084395 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 15019267 # number of replacements -system.cpu.icache.tags.tagsinuse 511.928693 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 340404778 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15019779 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.663767 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20448016500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.928693 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 15141033 # number of replacements +system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15141545 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.502248 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.928986 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 371211305 # Number of tag accesses -system.cpu.icache.tags.data_accesses 371211305 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 340404778 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 340404778 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 340404778 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 340404778 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 340404778 # number of overall hits -system.cpu.icache.overall_hits::total 340404778 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15786521 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15786521 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15786521 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15786521 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15786521 # number of overall misses -system.cpu.icache.overall_misses::total 15786521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 213423777380 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 213423777380 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 213423777380 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 213423777380 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 213423777380 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 213423777380 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 356191299 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 356191299 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 356191299 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 356191299 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 356191299 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 356191299 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044320 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044320 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044320 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044320 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044320 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044320 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13519.367401 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13519.367401 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13519.367401 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13519.367401 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13519.367401 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13519.367401 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 24648 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 371754919 # Number of tag accesses +system.cpu.icache.tags.data_accesses 371754919 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 340718799 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 340718799 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 340718799 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 340718799 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 340718799 # number of overall hits +system.cpu.icache.overall_hits::total 340718799 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15894345 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15894345 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15894345 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15894345 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15894345 # number of overall misses +system.cpu.icache.overall_misses::total 15894345 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 214960438379 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 214960438379 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 214960438379 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 214960438379 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 214960438379 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 214960438379 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 356613144 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 356613144 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 356613144 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 356613144 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 356613144 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 356613144 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044570 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.044570 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.044570 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.044570 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.044570 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.044570 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13524.334496 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13524.334496 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13524.334496 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13524.334496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13524.334496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13524.334496 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 23721 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1434 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1460 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 17.188285 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.247260 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 15019267 # number of writebacks -system.cpu.icache.writebacks::total 15019267 # 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number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 15141033 # number of writebacks +system.cpu.icache.writebacks::total 15141033 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 752570 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 752570 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 752570 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 752570 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 752570 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 752570 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15141775 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15141775 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15141775 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15141775 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191135995392 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 191135995392 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684938000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684938000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684938000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 2684938000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042168 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042168 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042168 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.042168 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19528.640359 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.567194 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004417 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006864 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119904 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.297983 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996362 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 277 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62375 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 277 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # 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average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124519.613263 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129523.100498 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128943.104737 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124519.613263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129523.100498 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128943.104737 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171348.610369 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148974.778069 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173206.893993 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173206.893993 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172278.000416 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.572427 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129277.111734 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129277.111734 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124885.825844 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124885.825844 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129580.272072 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129580.272072 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69893.357947 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69893.357947 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173199.949549 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173199.949549 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.748093 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.386340 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 50149666 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 25446406 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2163 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2163 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 50432401 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 25583822 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1624231 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23137410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8571764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 15019267 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2370936 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43497 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43503 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1964146 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1964146 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15020006 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6501231 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1333409 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1226745 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45101659 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29271837 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729068 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1925616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 77028180 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1922840864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1021731230 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2408256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6275144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2953255494 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1860303 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 27780180 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025443 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.157467 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8579850 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 15141033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2388844 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43659 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43666 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1963403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1963403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15141775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6525421 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1333524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1226860 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45466959 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29342845 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 722067 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1919121 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 77450992 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1938426848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023681310 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2369528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6237568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2970715254 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1868325 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 27924144 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.156198 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 27073367 97.46% 97.46% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 706813 2.54% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 27225372 97.50% 97.50% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 698772 2.50% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 27780180 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 48093772959 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 27924144 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 48365955497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1496382 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1497386 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22560257433 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22743143976 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13373462829 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13408724401 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 428394234 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 426213261 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1141603196 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1139764793 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40297 # Transaction distribution -system.iobus.trans_dist::ReadResp 40297 # Transaction distribution +system.iobus.trans_dist::ReadReq 40299 # Transaction distribution +system.iobus.trans_dist::ReadResp 40299 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1729,11 +1739,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353740 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1748,12 +1758,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41874500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41885000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1765,83 +1775,83 @@ system.iobus.reqLayer4.occupancy 9500 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25162500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25104500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36499500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36501000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567349755 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567373998 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147716000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115457 # number of replacements -system.iocache.tags.tagsinuse 10.423127 # Cycle average of tags in use +system.iocache.tags.replacements 115459 # number of replacements +system.iocache.tags.tagsinuse 10.423130 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13098803375000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544202 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.878925 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13098783117000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544201 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.878929 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651445 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651446 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039641 # Number of tag accesses -system.iocache.tags.data_accesses 1039641 # Number of data accesses +system.iocache.tags.tag_accesses 1039659 # Number of tag accesses +system.iocache.tags.data_accesses 1039659 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses -system.iocache.demand_misses::total 8852 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses +system.iocache.demand_misses::total 8854 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8812 # number of overall misses -system.iocache.overall_misses::total 8852 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1683110232 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1688179732 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8814 # number of overall misses +system.iocache.overall_misses::total 8854 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1678338975 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1683410975 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13415109023 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13415109023 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1683110232 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1688530732 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1683110232 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1688530732 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13416126023 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13416126023 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5423000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1678338975 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1683761975 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5423000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1678338975 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1683761975 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1855,55 +1865,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 191002.068997 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190776.328625 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 190417.401293 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 190194.438482 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125769.791335 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125769.791335 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 191002.068997 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 190751.325350 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 191002.068997 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 190751.325350 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34444 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125779.325949 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135575 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 190169.638017 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135575 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 190169.638017 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34291 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3506 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3518 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.824301 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.747300 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8814 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8851 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8814 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8854 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1242510232 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1245729732 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8814 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8854 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3222000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237638975 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1240860975 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8076836456 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8076836456 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1242510232 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1245930732 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1242510232 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1245930732 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8077839572 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8077839572 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3423000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1237638975 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1241061975 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3423000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1237638975 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1241061975 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1917,72 +1927,72 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141002.068997 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 140776.328625 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87081.081081 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140417.401293 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 140194.438482 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75722.234831 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75722.234831 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 141002.068997 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 140751.325350 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 141002.068997 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 140751.325350 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 54972 # Transaction distribution -system.membus.trans_dist::ReadResp 409202 # Transaction distribution +system.membus.trans_dist::ReadResp 410008 # Transaction distribution system.membus.trans_dist::WriteReq 33696 # Transaction distribution system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1067474 # Transaction distribution -system.membus.trans_dist::CleanEvict 191385 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34855 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1068539 # Transaction distribution +system.membus.trans_dist::CleanEvict 192763 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34977 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 394790 # Transaction distribution -system.membus.trans_dist::ReadExResp 394790 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 354230 # Transaction distribution -system.membus.trans_dist::InvalidateReq 604321 # Transaction distribution +system.membus.trans_dist::ReadExReq 394295 # Transaction distribution +system.membus.trans_dist::ReadExResp 394295 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 355036 # Transaction distribution +system.membus.trans_dist::InvalidateReq 605480 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3203313 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3332933 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237959 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237959 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3570892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3207653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3337273 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237899 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237899 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3575172 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109183820 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109353790 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7271424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7271424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 116625214 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2530 # Total snoops (count) -system.membus.snoop_fanout::samples 2735759 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109271756 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109441726 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7267328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7267328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 116709054 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2596 # Total snoops (count) +system.membus.snoop_fanout::samples 2739791 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2735759 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2739791 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2735759 # Request fanout histogram -system.membus.reqLayer0.occupancy 103971500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2739791 # Request fanout histogram +system.membus.reqLayer0.occupancy 103925500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 32000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5468000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5584000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7155774176 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7165123486 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4068025704 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4069623687 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44802062 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks |