diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker')
4 files changed, 3584 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini new file mode 100644 index 000000000..a07bdbdd3 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini @@ -0,0 +1,1705 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain +atags_addr=134217728 +boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=timing +mem_ranges=2147483648:2415919103 +memories=system.realview.vram system.physmem system.realview.nvmem +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5.latest/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +LFSTSize=1024 +LQEntries=16 +LSQCheckLoads=true +LSQDepCheckShift=0 +SQEntries=16 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=system.cpu.checker +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=2 +decodeWidth=3 +dispatchWidth=6 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=16 +fetchQueueSize=32 +fetchToDecodeDelay=3 +fetchTrapLatency=1 +fetchWidth=3 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=32 +numPhysCCRegs=640 +numPhysFloatRegs=192 +numPhysIntRegs=128 +numROBEntries=40 +numRobs=1 +numThreads=1 +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=1 +renameToROBDelay=1 +renameWidth=3 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload= +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=2048 +BTBTagSize=18 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=bi-mode + +[system.cpu.checker] +type=O3Checker +children=dstage2_mmu dtb isa istage2_mmu itb tracer +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.checker.dstage2_mmu +dtb=system.cpu.checker.dtb +eventq_index=0 +exitOnError=false +function_trace=false +function_trace_start=0 +interrupts=Null +isa=system.cpu.checker.isa +istage2_mmu=system.cpu.checker.istage2_mmu +itb=system.cpu.checker.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.checker.tracer +updateOnError=true +warnOnlyOnLoadError=true +workload= + +[system.cpu.checker.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb +tlb=system.cpu.checker.dtb + +[system.cpu.checker.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker + +[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[9] + +[system.cpu.checker.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.checker.dtb.walker + +[system.cpu.checker.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[7] + +[system.cpu.checker.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu.checker.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb +tlb=system.cpu.checker.itb + +[system.cpu.checker.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker + +[system.cpu.checker.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[8] + +[system.cpu.checker.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.checker.itb.walker + +[system.cpu.checker.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[6] + +[system.cpu.checker.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 opList2 +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +issueLat=12 +opClass=IntDiv +opLat=12 + +[system.cpu.fuPool.FUList1.opList2] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IprAccess +opLat=3 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList + +[system.cpu.fuPool.FUList2.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemRead +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList + +[system.cpu.fuPool.FUList3.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemWrite +opLat=2 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 + +[system.cpu.fuPool.FUList4.opList00] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAdd +opLat=4 + +[system.cpu.fuPool.FUList4.opList01] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAddAcc +opLat=4 + +[system.cpu.fuPool.FUList4.opList02] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAlu +opLat=4 + +[system.cpu.fuPool.FUList4.opList03] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCmp +opLat=4 + +[system.cpu.fuPool.FUList4.opList04] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCvt +opLat=3 + +[system.cpu.fuPool.FUList4.opList05] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMisc +opLat=3 + +[system.cpu.fuPool.FUList4.opList06] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMult +opLat=5 + +[system.cpu.fuPool.FUList4.opList07] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMultAcc +opLat=5 + +[system.cpu.fuPool.FUList4.opList08] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShift +opLat=3 + +[system.cpu.fuPool.FUList4.opList09] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShiftAcc +opLat=3 + +[system.cpu.fuPool.FUList4.opList10] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdSqrt +opLat=9 + +[system.cpu.fuPool.FUList4.opList11] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAdd +opLat=5 + +[system.cpu.fuPool.FUList4.opList12] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAlu +opLat=5 + +[system.cpu.fuPool.FUList4.opList13] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCmp +opLat=3 + +[system.cpu.fuPool.FUList4.opList14] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCvt +opLat=3 + +[system.cpu.fuPool.FUList4.opList15] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatDiv +opLat=3 + +[system.cpu.fuPool.FUList4.opList16] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMisc +opLat=3 + +[system.cpu.fuPool.FUList4.opList17] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMult +opLat=3 + +[system.cpu.fuPool.FUList4.opList18] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList4.opList19] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatSqrt +opLat=9 + +[system.cpu.fuPool.FUList4.opList20] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatAdd +opLat=5 + +[system.cpu.fuPool.FUList4.opList21] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCmp +opLat=5 + +[system.cpu.fuPool.FUList4.opList22] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCvt +opLat=5 + +[system.cpu.fuPool.FUList4.opList23] +type=OpDesc +eventq_index=0 +issueLat=9 +opClass=FloatDiv +opLat=9 + +[system.cpu.fuPool.FUList4.opList24] +type=OpDesc +eventq_index=0 +issueLat=33 +opClass=FloatSqrt +opLat=33 + +[system.cpu.fuPool.FUList4.opList25] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=true +width=8 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr new file mode 100644 index 000000000..8d34f421c --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr @@ -0,0 +1,91 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: 13842443212000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13881966762000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13882255463000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13882829689000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13883384376000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13883639881500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13885195478000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14119823023500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14121701098000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14127958169500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14128186290500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14128405933500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14128812861500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14129226204500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14167422773000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14205629937000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14448292905000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14448293175500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14456513700500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14456513960000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14464465597000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14464465877500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14464466467500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14464466743000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14464466981000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14472409559000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14472410152500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14472410415000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14472410653000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14472410900000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14477663411000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14483940515000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14483940774000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14493678366500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14504940200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14504941281500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14504941528000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14514859454000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14514859717500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14530591953000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14530592212000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14535730342000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14535730633500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14535731223500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14535731486000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14535731724000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14542816759000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14542817022500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14553011613000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14553012206500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14553012482000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14553012757000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14553013043000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14617580022000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14617580304000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14677231930000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14677232200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14798881767000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14798974404500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14798974754500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799704795000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799705056000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42 +warn: 14799705260500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799777436500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 +warn: 14799777691500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799777962500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 +warn: 14799778533000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799778788500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 +warn: 14799779012000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799779301000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799779810000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799780873500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799781372500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799781674500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14848040219000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 +warn: 14848040537000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14848040839000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14848041113000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14848041396500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14848041675500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout new file mode 100644 index 000000000..4029bb1c2 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout @@ -0,0 +1,17 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:38:57 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 + 0: system.cpu.checker.isa: ISA system set to: 0x48ecb00 0x48ecb00 + 0: system.cpu.isa: ISA system set to: 0x48ecb00 0x48ecb00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80080000 +info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 51557114994500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt new file mode 100644 index 000000000..173ad2168 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -0,0 +1,1771 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 51.557115 # Number of seconds simulated +sim_ticks 51557114994500 # Number of ticks simulated +final_tick 51557114994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 81227 # Simulator instruction rate (inst/s) +host_op_rate 95475 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3758004040 # Simulator tick rate (ticks/s) +host_mem_usage 668380 # Number of bytes of host memory used +host_seconds 13719.28 # Real time elapsed on the host +sim_insts 1114380469 # Number of instructions simulated +sim_ops 1309844804 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::realview.ide 437568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1002304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 1237760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6145632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 128560840 # Number of bytes read from this memory +system.physmem.bytes_read::total 137384104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6145632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6145632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 102180288 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 102783780 # Number of bytes written to this memory +system.physmem.bytes_written::total 211790564 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 6837 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 15661 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 19340 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 111978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2008776 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2162592 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1596567 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 1608248 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3311479 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 8487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 19441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 24008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 119200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2493562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2664697 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 119200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 119200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1981885 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 132406 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1993591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4107882 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1981885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 140894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 19441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 24008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 119200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4487152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6772580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2162592 # Number of read requests accepted +system.physmem.writeReqs 3311479 # Number of write requests accepted +system.physmem.readBursts 2162592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 3311479 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 138204608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 201280 # Total number of bytes read from write queue +system.physmem.bytesWritten 207618304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 137384104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 211790564 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 3145 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 67428 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 48470 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 140382 # Per bank write bursts +system.physmem.perBankRdBursts::1 139333 # Per bank write bursts +system.physmem.perBankRdBursts::2 140658 # Per bank write bursts +system.physmem.perBankRdBursts::3 133921 # Per bank write bursts +system.physmem.perBankRdBursts::4 130324 # Per bank write bursts +system.physmem.perBankRdBursts::5 134612 # Per bank write bursts +system.physmem.perBankRdBursts::6 126217 # Per bank write bursts +system.physmem.perBankRdBursts::7 133097 # Per bank write bursts +system.physmem.perBankRdBursts::8 129592 # Per bank write bursts +system.physmem.perBankRdBursts::9 157619 # Per bank write bursts +system.physmem.perBankRdBursts::10 133394 # Per bank write bursts +system.physmem.perBankRdBursts::11 133867 # Per bank write bursts +system.physmem.perBankRdBursts::12 132326 # Per bank write bursts +system.physmem.perBankRdBursts::13 132284 # Per bank write bursts +system.physmem.perBankRdBursts::14 133117 # Per bank write bursts +system.physmem.perBankRdBursts::15 128704 # Per bank write bursts +system.physmem.perBankWrBursts::0 201659 # Per bank write bursts +system.physmem.perBankWrBursts::1 203665 # Per bank write bursts +system.physmem.perBankWrBursts::2 231223 # Per bank write bursts +system.physmem.perBankWrBursts::3 188549 # Per bank write bursts +system.physmem.perBankWrBursts::4 224931 # Per bank write bursts +system.physmem.perBankWrBursts::5 188791 # Per bank write bursts +system.physmem.perBankWrBursts::6 176287 # Per bank write bursts +system.physmem.perBankWrBursts::7 226882 # Per bank write bursts +system.physmem.perBankWrBursts::8 203233 # Per bank write bursts +system.physmem.perBankWrBursts::9 233524 # Per bank write bursts +system.physmem.perBankWrBursts::10 253232 # Per bank write bursts +system.physmem.perBankWrBursts::11 198347 # Per bank write bursts +system.physmem.perBankWrBursts::12 181957 # Per bank write bursts +system.physmem.perBankWrBursts::13 175879 # Per bank write bursts +system.physmem.perBankWrBursts::14 180282 # Per bank write bursts +system.physmem.perBankWrBursts::15 175595 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 190 # Number of times write queue was full causing retry +system.physmem.totGap 51557113761500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 13 # Read request sizes (log2) +system.physmem.readPktSize::4 21272 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 2141307 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 1 # Write request sizes (log2) +system.physmem.writePktSize::3 2572 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 3308906 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1296550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 764534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 68768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 55343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 88539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 132669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 172060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 179259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 199827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 201826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 215089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 217686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 234764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 216813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 209096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 190795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 202440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 157954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 153989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 157951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 145311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 9323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 7805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 5695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 4548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 3461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 474 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1034839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 334.179783 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.532509 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.014667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 392208 37.90% 37.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 234584 22.67% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 87901 8.49% 69.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 49413 4.77% 73.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38348 3.71% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26689 2.58% 80.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21988 2.12% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25501 2.46% 84.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 158207 15.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1034839 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 135592 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.925969 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 128.724301 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 135587 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-43007 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 135592 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 135592 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.924981 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.930688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.164557 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 101303 74.71% 74.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 7599 5.60% 80.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 12845 9.47% 89.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 3908 2.88% 92.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 2324 1.71% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 925 0.68% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 2932 2.16% 97.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1250 0.92% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 889 0.66% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 249 0.18% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 327 0.24% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 193 0.14% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 473 0.35% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 16 0.01% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 22 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 28 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 17 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 31 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 89 0.07% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 56 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 42 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 15 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 15 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 6 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 5 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 5 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 135592 # Writes before turning the bus around for reads +system.physmem.totQLat 43990891280 # Total ticks spent queuing +system.physmem.totMemAccLat 84480522530 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10797235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20371.37 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 39121.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing +system.physmem.readRowHits 1747291 # Number of row buffer hits during reads +system.physmem.writeRowHits 2621349 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes +system.physmem.avgGap 9418422.55 # Average gap between requests +system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49290195125250 # Time in different power states +system.physmem.memoryStateTime::REF 1721605340000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 545313634750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3951453240 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3871929600 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2156050875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2112660000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 8412588600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 8431020000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 10640075760 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 10381277520 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3367460045040 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3367460045040 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1383947967870 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1368871606665 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29720278968750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29733503847000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34496847150135 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34494632385825 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.099654 # Core power per rank (mW) +system.physmem.averagePower::1 669.056696 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 657217 # Transaction distribution +system.membus.trans_dist::ReadResp 657217 # Transaction distribution +system.membus.trans_dist::WriteReq 33865 # Transaction distribution +system.membus.trans_dist::WriteResp 33865 # Transaction distribution +system.membus.trans_dist::Writeback 1596567 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 1712339 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 1712339 # Transaction distribution +system.membus.trans_dist::UpgradeReq 48473 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 48476 # Transaction distribution +system.membus.trans_dist::ReadExReq 1541174 # Transaction distribution +system.membus.trans_dist::ReadExResp 1541174 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9221519 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9351669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229018 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 229018 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9580687 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341910604 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 342081160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7264064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 349345224 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2022 # Total snoops (count) +system.membus.snoop_fanout::samples 5500895 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 5500895 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 5500895 # Request fanout histogram +system.membus.reqLayer0.occupancy 109641999 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5450500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 32462148974 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 21571101815 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 186532342 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1669 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 40379 # Transaction distribution +system.iobus.trans_dist::ReadResp 40379 # Transaction distribution +system.iobus.trans_dist::WriteReq 136716 # Transaction distribution +system.iobus.trans_dist::WriteResp 136733 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 17 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354224 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492654 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 981079506 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179002658 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 291488483 # Number of BP lookups +system.cpu.branchPred.condPredicted 200150149 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13608043 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 209143322 # Number of BTB lookups +system.cpu.branchPred.BTBHits 138326751 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 66.139693 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37688944 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 403819 # Number of incorrect RAS predictions. +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.inst_hits 0 # ITB inst hits +system.cpu.checker.dtb.inst_misses 0 # ITB inst misses +system.cpu.checker.dtb.read_hits 206311750 # DTB read hits +system.cpu.checker.dtb.read_misses 258027 # DTB read misses +system.cpu.checker.dtb.write_hits 190103200 # DTB write hits +system.cpu.checker.dtb.write_misses 94684 # DTB write misses +system.cpu.checker.dtb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.dtb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 89489 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.dtb.prefetch_faults 10233 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.dtb.perms_faults 24751 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 206569777 # DTB read accesses +system.cpu.checker.dtb.write_accesses 190197884 # DTB write accesses +system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.dtb.hits 396414950 # DTB hits +system.cpu.checker.dtb.misses 352711 # DTB misses +system.cpu.checker.dtb.accesses 396767661 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.inst_hits 1114925280 # ITB inst hits +system.cpu.checker.itb.inst_misses 131008 # ITB inst misses +system.cpu.checker.itb.read_hits 0 # DTB read hits +system.cpu.checker.itb.read_misses 0 # DTB read misses +system.cpu.checker.itb.write_hits 0 # DTB write hits +system.cpu.checker.itb.write_misses 0 # DTB write misses +system.cpu.checker.itb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.itb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 61860 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.itb.read_accesses 0 # DTB read accesses +system.cpu.checker.itb.write_accesses 0 # DTB write accesses +system.cpu.checker.itb.inst_accesses 1115056288 # ITB inst accesses +system.cpu.checker.itb.hits 1114925280 # DTB hits +system.cpu.checker.itb.misses 131008 # DTB misses +system.cpu.checker.itb.accesses 1115056288 # DTB accesses +system.cpu.checker.numCycles 1310563748 # number of cpu cycles simulated +system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 220000246 # DTB read hits +system.cpu.dtb.read_misses 1007031 # DTB read misses +system.cpu.dtb.write_hits 193886106 # DTB write hits +system.cpu.dtb.write_misses 416122 # DTB write misses +system.cpu.dtb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 89690 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 112 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 15179 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 87251 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 221007277 # DTB read accesses +system.cpu.dtb.write_accesses 194302228 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 413886352 # DTB hits +system.cpu.dtb.misses 1423153 # DTB misses +system.cpu.dtb.accesses 415309505 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 465588468 # ITB inst hits +system.cpu.itb.inst_misses 176797 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 63536 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 462381 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 465765265 # ITB inst accesses +system.cpu.itb.hits 465588468 # DTB hits +system.cpu.itb.misses 176797 # DTB misses +system.cpu.itb.accesses 465765265 # DTB accesses +system.cpu.numCycles 2146849645 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 791511347 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1301628389 # Number of instructions fetch has processed +system.cpu.fetch.Branches 291488483 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 176015695 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1268750537 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29307286 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4254748 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 12217982 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1219824 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 381 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 465107423 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6746831 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 53918 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2092636388 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.729302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.142136 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1367675983 65.36% 65.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 280886167 13.42% 78.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 86945610 4.15% 82.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 357128628 17.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 2092636388 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.135775 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.606297 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 614820490 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 852644163 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 531180111 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 83391963 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10599661 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41490545 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4112846 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1415541998 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32718079 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10599661 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 678805488 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 83662136 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 556428904 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 549849830 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 213290369 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1391734034 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 7977079 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7435136 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 893230 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1023922 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 127479585 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 25199 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1342075875 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2217645602 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1652184740 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1639045 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1263873564 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 78202308 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44203192 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39719264 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 172796539 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 223511224 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 198396121 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12647992 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11061331 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1338396177 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 44508712 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1370133902 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4153047 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65240654 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41320787 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 373617 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2092636388 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.654741 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.915536 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1237717942 59.15% 59.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 455529583 21.77% 80.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 292996726 14.00% 94.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96986296 4.63% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9377226 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 28615 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2092636388 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 74528454 34.28% 34.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90672 0.04% 34.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26772 0.01% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 287 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 58830485 27.06% 61.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 83911289 38.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 945793660 69.03% 69.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2946266 0.22% 69.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 129775 0.01% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 114397 0.01% 69.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 224851656 16.41% 85.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 196298100 14.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1370133902 # Type of FU issued +system.cpu.iq.rate 0.638207 # Inst issue rate +system.cpu.iq.fu_busy_cnt 217387959 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.158662 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5052021388 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1447405501 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1347303683 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2423809 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 923681 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 885699 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1585997449 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1524411 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5766333 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 16996131 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24128 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 185382 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8259714 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 3623609 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3385962 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 10599661 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11961718 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7304667 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1383179145 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 223511224 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 198396121 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39177517 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 185228 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6936317 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 185382 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4274350 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5730421 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10004771 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1356817685 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 220004444 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11924579 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 274256 # number of nop insts executed +system.cpu.iew.exec_refs 413901554 # number of memory reference insts executed +system.cpu.iew.exec_branches 257473473 # Number of branches executed +system.cpu.iew.exec_stores 193897110 # Number of stores executed +system.cpu.iew.exec_rate 0.632004 # Inst execution rate +system.cpu.iew.wb_sent 1349182874 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1348189382 # cumulative count of insts written-back +system.cpu.iew.wb_producers 579023420 # num instructions producing a value +system.cpu.iew.wb_consumers 949767765 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.627985 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.609647 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitSquashedInsts 62443917 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 44135095 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9554061 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2078483160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.630193 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.269789 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1396354428 67.18% 67.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 397736022 19.14% 86.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 152396085 7.33% 93.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44287772 2.13% 95.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35996912 1.73% 97.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18656723 0.90% 98.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10905184 0.52% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5449343 0.26% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16700691 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 2078483160 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1114380469 # Number of instructions committed +system.cpu.commit.committedOps 1309844804 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 396651499 # Number of memory references committed +system.cpu.commit.loads 206515092 # Number of loads committed +system.cpu.commit.membars 9189565 # Number of memory barriers committed +system.cpu.commit.branches 249089949 # Number of branches committed +system.cpu.commit.fp_insts 873640 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1196978104 # Number of committed integer instructions. +system.cpu.commit.function_calls 31078874 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 910428363 69.51% 69.51% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2554988 0.20% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 104143 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 105769 0.01% 69.72% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.72% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.72% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.72% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 206515092 15.77% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 190136407 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1309844804 # Class of committed instruction +system.cpu.commit.bw_lim_events 16700691 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 3424556806 # The number of ROB reads +system.cpu.rob.rob_writes 2758622493 # The number of ROB writes +system.cpu.timesIdled 9031521 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 54213257 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100967380384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1114380469 # Number of Instructions Simulated +system.cpu.committedOps 1309844804 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.926496 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.926496 # CPI: Total CPI of All Threads +system.cpu.ipc 0.519077 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.519077 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1611998606 # number of integer regfile reads +system.cpu.int_regfile_writes 948639329 # number of integer regfile writes +system.cpu.fp_regfile_reads 1420015 # number of floating regfile reads +system.cpu.fp_regfile_writes 765124 # number of floating regfile writes +system.cpu.cc_regfile_reads 315259155 # number of cc regfile reads +system.cpu.cc_regfile_writes 316098925 # number of cc regfile writes +system.cpu.misc_regfile_reads 6952427793 # number of misc regfile reads +system.cpu.misc_regfile_writes 45059384 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 28539920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28531649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33865 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33865 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 9369509 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1712344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1605675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 61529 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 61535 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3074731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3074731 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33703094 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37825776 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 810571 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3115869 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 75455310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1077469744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1502191576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2724416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10868120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2593253856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 644632 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 42703026 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9.002705 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.051942 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 42587504 99.73% 99.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 115522 0.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 42703026 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32333793873 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 871500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 25296093441 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 19876823538 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 472614279 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 1760067316 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu.icache.tags.replacements 16829629 # number of replacements +system.cpu.icache.tags.tagsinuse 511.959617 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 447510611 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16830141 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26.589831 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 12236526000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.959617 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 291 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 481916487 # Number of tag accesses +system.cpu.icache.tags.data_accesses 481916487 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 447510611 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 447510611 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 447510611 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 447510611 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 447510611 # number of overall hits +system.cpu.icache.overall_hits::total 447510611 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17575514 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17575514 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17575514 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17575514 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17575514 # number of overall misses +system.cpu.icache.overall_misses::total 17575514 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 231527181766 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 231527181766 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 231527181766 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 231527181766 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 231527181766 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 231527181766 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 465086125 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 465086125 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465086125 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465086125 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465086125 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465086125 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.037790 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.037790 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.037790 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.037790 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.037790 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.037790 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13173.280836 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13173.280836 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13173.280836 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13173.280836 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13173.280836 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13173.280836 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 11084 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 920 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 12.047826 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 745151 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 745151 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 745151 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 745151 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 745151 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 745151 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16830363 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16830363 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16830363 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16830363 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16830363 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16830363 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191394786019 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 191394786019 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191394786019 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 191394786019 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191394786019 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 191394786019 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1413030250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1413030250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1413030250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 1413030250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036188 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.036188 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.036188 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11371.993939 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11371.993939 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11371.993939 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11371.993939 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11371.993939 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11371.993939 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 1866229 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64521.528187 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 35312731 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1928499 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.310993 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 13813873928000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 34323.724648 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 307.320059 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 449.834309 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7078.453286 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 22362.195885 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.523738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004689 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006864 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.108009 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.341220 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.984520 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 496 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 61774 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 485 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2102 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5030 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54369 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.007568 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.942596 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 341864435 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 341864435 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1342854 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 321211 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 16739434 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 8950656 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 27354155 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 9369509 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 9369509 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 13684 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 13684 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1532929 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1532929 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 1342854 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 321211 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 16739434 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 10483585 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 28887084 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 1342854 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 321211 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 16739434 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 10483585 # number of overall hits +system.cpu.l2cache.overall_hits::total 28887084 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 15661 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 19341 # 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average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 13756884 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.985330 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 363427258 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 13757396 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.416864 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1485814250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.985330 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1609448196 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1609448196 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 188132338 # 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number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1225081776243 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1225081776243 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1225081776243 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1225081776243 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 200844617 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 200844617 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 183200948 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 183200948 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2537879 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2537879 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1605675 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1605675 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5398366 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5398366 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5335209 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5335209 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 384045565 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 384045565 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 386583444 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 386583444 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063294 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.063294 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103541 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.103541 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816476 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.816476 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.101960 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.101960 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.082493 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082493 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087311 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087311 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16000.556505 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16000.556505 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53861.197196 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53861.197196 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15672.030311 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15672.030311 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38669.285110 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38669.285110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36295.361841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36295.361841 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 38319499 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2284719 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.772084 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 1605675 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 9369509 # number of writebacks +system.cpu.dcache.writebacks::total 9369509 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5628309 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5628309 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15829986 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15829986 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265840 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 265840 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 21458295 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21458295 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21458295 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21458295 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7083970 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7083970 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3120649 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3120649 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2065320 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2065320 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 284579 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 284579 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 10204619 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 10204619 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 12269939 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 12269939 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 102477717871 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 102477717871 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 148263766896 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 148263766896 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 31611668497 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 31611668497 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 59007365277 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 59007365277 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3751055249 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3751055249 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 104997 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 104997 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250741484767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 250741484767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 282353153264 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 282353153264 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729434750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729434750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587276983 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587276983 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316711733 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316711733 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035271 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035271 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.017034 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.017034 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813798 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813798 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052716 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052716 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026571 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026571 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031739 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031739 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.142272 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.142272 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47510.555303 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47510.555303 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15305.942177 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15305.942177 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13181.068347 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13181.068347 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24571.371530 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24571.371530 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23011.781335 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23011.781335 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.tags.replacements 115458 # number of replacements +system.iocache.tags.tagsinuse 10.450727 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 13090278324000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.528058 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.922669 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220504 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432667 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653170 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 1039786 # Number of tag accesses +system.iocache.tags.data_accesses 1039786 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses +system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses +system.iocache.WriteReq_misses::total 3 # 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number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5886000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1929395843 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1935281843 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5886000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1929395843 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1935281843 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::realview.ethernet 3 # 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miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000159 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000159 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149918.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 218926.114036 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 218637.609379 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 147150 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 218601.812154 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 147150 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 218601.812154 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 53350 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.717668 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 3 # 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number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6546677301 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6546677301 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3806000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1470987863 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1474793863 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3806000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1470987863 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1474793863 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166911.138432 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 166622.696384 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 17164 # number of quiesce instructions executed + +---------- End Simulation Statistics ---------- |