diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt | 6413 |
1 files changed, 3212 insertions, 3201 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 973772ffd..a0d86b26c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,170 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.434893 # Number of seconds simulated -sim_ticks 47434893411000 # Number of ticks simulated -final_tick 47434893411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.395178 # Number of seconds simulated +sim_ticks 47395178174000 # Number of ticks simulated +final_tick 47395178174000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99639 # Simulator instruction rate (inst/s) -host_op_rate 117176 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5152463712 # Simulator tick rate (ticks/s) -host_mem_usage 784704 # Number of bytes of host memory used -host_seconds 9206.25 # Real time elapsed on the host -sim_insts 917301737 # Number of instructions simulated -sim_ops 1078753903 # Number of ops (including micro ops) simulated +host_inst_rate 85380 # Simulator instruction rate (inst/s) +host_op_rate 100389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4378207332 # Simulator tick rate (ticks/s) +host_mem_usage 733200 # Number of bytes of host memory used +host_seconds 10825.25 # Real time elapsed on the host +sim_insts 924259255 # Number of instructions simulated +sim_ops 1086731985 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 208192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 203648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4658336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 45847432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 22095168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 91328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 66368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2323808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 12264528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 10934912 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 422080 # Number of bytes read from this memory -system.physmem.bytes_read::total 99115800 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4658336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2323808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6982144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 83002560 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 173952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 172224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 5051936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 46751112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 21558016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 154688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 128576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2266144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 13742800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 14572608 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 453056 # Number of bytes read from this memory +system.physmem.bytes_read::total 105025112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 5051936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2266144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7318080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 87763520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 83023144 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3253 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3182 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 88739 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 716379 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 345237 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1427 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1037 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 36353 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 191646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 170858 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6595 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1564706 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1296915 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 87784104 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2718 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2691 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 94889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 730499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 336844 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2417 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2009 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 35452 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 214744 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 227697 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7079 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1657039 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1371305 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1299489 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 4293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 98205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 966534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 465800 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 48989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 258555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 230525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2089512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 98205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 48989 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 147194 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1749821 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1373879 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3634 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 106592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 986411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 454857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 289962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 307470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9559 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2215945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 106592 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 154406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1851739 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1750255 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1749821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 4293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 98205 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 966968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 465800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 48989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 258555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 230525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3839767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1564706 # Number of read requests accepted -system.physmem.writeReqs 1299489 # Number of write requests accepted -system.physmem.readBursts 1564706 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1299489 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 100111296 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 29888 # Total number of bytes read from write queue -system.physmem.bytesWritten 83021568 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 99115800 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 83023144 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 467 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1852174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1851739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3634 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 106592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 986845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 454857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 289962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 307470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4068119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1657039 # Number of read requests accepted +system.physmem.writeReqs 1373879 # Number of write requests accepted +system.physmem.readBursts 1657039 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1373879 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 106020736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 29760 # Total number of bytes read from write queue +system.physmem.bytesWritten 87783296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 105025112 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 87784104 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 465 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 228681 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 96105 # Per bank write bursts -system.physmem.perBankRdBursts::1 104079 # Per bank write bursts -system.physmem.perBankRdBursts::2 99076 # Per bank write bursts -system.physmem.perBankRdBursts::3 102555 # Per bank write bursts -system.physmem.perBankRdBursts::4 95026 # Per bank write bursts -system.physmem.perBankRdBursts::5 98411 # Per bank write bursts -system.physmem.perBankRdBursts::6 98571 # Per bank write bursts -system.physmem.perBankRdBursts::7 95349 # Per bank write bursts -system.physmem.perBankRdBursts::8 90083 # Per bank write bursts -system.physmem.perBankRdBursts::9 124090 # Per bank write bursts -system.physmem.perBankRdBursts::10 93867 # Per bank write bursts -system.physmem.perBankRdBursts::11 97434 # Per bank write bursts -system.physmem.perBankRdBursts::12 91060 # Per bank write bursts -system.physmem.perBankRdBursts::13 95554 # Per bank write bursts -system.physmem.perBankRdBursts::14 90000 # Per bank write bursts -system.physmem.perBankRdBursts::15 92979 # Per bank write bursts -system.physmem.perBankWrBursts::0 80467 # Per bank write bursts -system.physmem.perBankWrBursts::1 87240 # Per bank write bursts -system.physmem.perBankWrBursts::2 82424 # Per bank write bursts -system.physmem.perBankWrBursts::3 84720 # Per bank write bursts -system.physmem.perBankWrBursts::4 78521 # Per bank write bursts -system.physmem.perBankWrBursts::5 82917 # Per bank write bursts -system.physmem.perBankWrBursts::6 81751 # Per bank write bursts -system.physmem.perBankWrBursts::7 80612 # Per bank write bursts -system.physmem.perBankWrBursts::8 77294 # Per bank write bursts -system.physmem.perBankWrBursts::9 85251 # Per bank write bursts -system.physmem.perBankWrBursts::10 78271 # Per bank write bursts -system.physmem.perBankWrBursts::11 81127 # Per bank write bursts -system.physmem.perBankWrBursts::12 78007 # Per bank write bursts -system.physmem.perBankWrBursts::13 81137 # Per bank write bursts -system.physmem.perBankWrBursts::14 77706 # Per bank write bursts -system.physmem.perBankWrBursts::15 79767 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 224488 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 100246 # Per bank write bursts +system.physmem.perBankRdBursts::1 102501 # Per bank write bursts +system.physmem.perBankRdBursts::2 99063 # Per bank write bursts +system.physmem.perBankRdBursts::3 111016 # Per bank write bursts +system.physmem.perBankRdBursts::4 103342 # Per bank write bursts +system.physmem.perBankRdBursts::5 111704 # Per bank write bursts +system.physmem.perBankRdBursts::6 101938 # Per bank write bursts +system.physmem.perBankRdBursts::7 100431 # Per bank write bursts +system.physmem.perBankRdBursts::8 95106 # Per bank write bursts +system.physmem.perBankRdBursts::9 125245 # Per bank write bursts +system.physmem.perBankRdBursts::10 101573 # Per bank write bursts +system.physmem.perBankRdBursts::11 106068 # Per bank write bursts +system.physmem.perBankRdBursts::12 95582 # Per bank write bursts +system.physmem.perBankRdBursts::13 100418 # Per bank write bursts +system.physmem.perBankRdBursts::14 101028 # Per bank write bursts +system.physmem.perBankRdBursts::15 101313 # Per bank write bursts +system.physmem.perBankWrBursts::0 83566 # Per bank write bursts +system.physmem.perBankWrBursts::1 87156 # Per bank write bursts +system.physmem.perBankWrBursts::2 83944 # Per bank write bursts +system.physmem.perBankWrBursts::3 90509 # Per bank write bursts +system.physmem.perBankWrBursts::4 85224 # Per bank write bursts +system.physmem.perBankWrBursts::5 91500 # Per bank write bursts +system.physmem.perBankWrBursts::6 84276 # Per bank write bursts +system.physmem.perBankWrBursts::7 85215 # Per bank write bursts +system.physmem.perBankWrBursts::8 82233 # Per bank write bursts +system.physmem.perBankWrBursts::9 88133 # Per bank write bursts +system.physmem.perBankWrBursts::10 85317 # Per bank write bursts +system.physmem.perBankWrBursts::11 88722 # Per bank write bursts +system.physmem.perBankWrBursts::12 80882 # Per bank write bursts +system.physmem.perBankWrBursts::13 85628 # Per bank write bursts +system.physmem.perBankWrBursts::14 84824 # Per bank write bursts +system.physmem.perBankWrBursts::15 84485 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 33 # Number of times write queue was full causing retry -system.physmem.totGap 47434891912500 # Total gap between requests +system.physmem.numWrRetry 14 # Number of times write queue was full causing retry +system.physmem.totGap 47395176675500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1543348 # Read request sizes (log2) +system.physmem.readPktSize::6 1635681 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1296915 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 588411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 392193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 156445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 159831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 99518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 60251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 29617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 26249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 7312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 550 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1371305 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 618737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 421038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 166212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 166706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 103650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 63464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 34359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 32178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 8186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1852 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 561 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -188,163 +188,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 18951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 21518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 33036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 40734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 49908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 58222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 73957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 80711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 84361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 87259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 93166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 91933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 94699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 106371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 99156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 93223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 82575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 69 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 977888 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 187.273406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 115.248079 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 243.900483 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 583799 59.70% 59.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 193375 19.77% 79.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 62560 6.40% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34177 3.49% 89.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24599 2.52% 91.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13672 1.40% 93.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13781 1.41% 94.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7457 0.76% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 44468 4.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 977888 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 73621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.246927 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 254.221432 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 73618 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 20142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 22530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 34959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 43149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 52927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 71450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 78161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 85169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 89148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 92391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 98600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 97124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 100685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 113079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 104553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 98049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 87257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 34 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1046566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 185.180531 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 114.222366 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 242.012748 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 630659 60.26% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 204416 19.53% 79.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 66292 6.33% 86.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 36110 3.45% 89.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 25913 2.48% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14303 1.37% 93.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14388 1.37% 94.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7964 0.76% 95.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 46521 4.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1046566 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 78027 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.230689 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 247.022438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 78024 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 73621 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 73621 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.620136 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.126079 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.628572 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 68415 92.93% 92.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2834 3.85% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 416 0.57% 97.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 328 0.45% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 84 0.11% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 303 0.41% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 179 0.24% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 107 0.15% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 91 0.12% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 122 0.17% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 36 0.05% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 46 0.06% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 419 0.57% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 29 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 25 0.03% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 117 0.16% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 27 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 78027 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 78027 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.578710 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.107570 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.499017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 72603 93.05% 93.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2990 3.83% 96.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 480 0.62% 97.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 334 0.43% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 81 0.10% 98.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 301 0.39% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 173 0.22% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 106 0.14% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 88 0.11% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 126 0.16% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 37 0.05% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 56 0.07% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 406 0.52% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 31 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 24 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 123 0.16% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 13 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 73621 # Writes before turning the bus around for reads -system.physmem.totQLat 78457411069 # Total ticks spent queuing -system.physmem.totMemAccLat 107786892319 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7821195000 # Total ticks spent in databus transfers -system.physmem.avgQLat 50156.92 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::236-239 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 78027 # Writes before turning the bus around for reads +system.physmem.totQLat 82234419314 # Total ticks spent queuing +system.physmem.totMemAccLat 113295181814 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8282870000 # Total ticks spent in databus transfers +system.physmem.avgQLat 49641.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 68906.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.75 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.09 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 68391.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.14 # Average write queue length when enqueuing -system.physmem.readRowHits 1261076 # Number of row buffer hits during reads -system.physmem.writeRowHits 622485 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.99 # Row buffer hit rate for writes -system.physmem.avgGap 16561334.66 # Average gap between requests -system.physmem.pageHitRate 65.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3784611600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2065016250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6155541600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4268064960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3098216175600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1175166619965 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27430083930000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31719739959975 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.700662 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45632003284876 # Time in different power states -system.physmem_0.memoryStateTime::REF 1583955100000 # Time in different power states +system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing +system.physmem.readRowHits 1332435 # Number of row buffer hits during reads +system.physmem.writeRowHits 649185 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.33 # Row buffer hit rate for writes +system.physmem.avgGap 15637234.88 # Average gap between requests +system.physmem.pageHitRate 65.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4004169120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2184814500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6475833000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4480207200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3095622519600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1180796903550 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27401319159750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31694883606720 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.736482 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45584100048214 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582629100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 218928032624 # Time in different power states +system.physmem_0.memoryStateTime::ACT 228448334286 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3608221680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1968771750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6045468000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4137868800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3098216175600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1172302278480 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27432596510250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31718875294560 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.682434 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45636187348814 # Time in different power states -system.physmem_1.memoryStateTime::REF 1583955100000 # Time in different power states +system.physmem_1.actEnergy 3907869840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2132270250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6445397400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4407851520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3095622519600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1181668397355 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27400554691500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31694738997465 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.733431 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45582807436264 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582629100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 214746668686 # Time in different power states +system.physmem_1.memoryStateTime::ACT 229740006236 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -378,15 +379,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 146144434 # Number of BP lookups -system.cpu0.branchPred.condPredicted 97047776 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7141884 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 102585049 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 68142392 # Number of BTB hits +system.cpu0.branchPred.lookups 146971248 # Number of BP lookups +system.cpu0.branchPred.condPredicted 97492286 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7372479 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 103605243 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 68020426 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.425266 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 20061645 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 208019 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.653459 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20148210 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 220615 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -417,85 +418,88 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 627056 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 627056 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13350 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 99805 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 293358 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 333698 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2422.801455 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 15109.123610 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 330908 99.16% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1425 0.43% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 1094 0.33% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 126 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 71 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 333698 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 325671 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 20358.917435 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 16786.442146 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 23186.053079 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 321319 98.66% 98.66% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 949 0.29% 98.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2404 0.74% 99.69% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 140 0.04% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 546 0.17% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 110 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 121 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 45 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 26 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 11 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 325671 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 568195090048 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.606171 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.541778 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 566772056048 99.75% 99.75% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 811255500 0.14% 99.89% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 288193500 0.05% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 133409000 0.02% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 101036500 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 47966000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 17568000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 22933000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 641000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 31500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 568195090048 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 99806 88.20% 88.20% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 13350 11.80% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 113156 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 627056 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 621589 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 621589 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13120 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 97816 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 286624 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 334965 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2330.974878 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14719.833023 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 332297 99.20% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1432 0.43% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 943 0.28% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 131 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 57 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 84 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 13 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 334965 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 317874 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 20050.667875 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 16636.288203 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 22186.320011 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 314157 98.83% 98.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 825 0.26% 99.09% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2043 0.64% 99.73% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 147 0.05% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 407 0.13% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 108 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 100 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 42 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 23 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 13 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::720896-786431 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 317874 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 575732613804 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.609948 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.538779 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 574368413804 99.76% 99.76% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 774580000 0.13% 99.90% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 276702000 0.05% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 125012500 0.02% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 99386000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 49877000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 16787500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 21052000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 785500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 17500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 575732613804 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 97816 88.17% 88.17% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 13120 11.83% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 110936 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 621589 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 627056 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 113156 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 621589 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110936 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 113156 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 740212 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110936 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 732525 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 106442927 # DTB read hits -system.cpu0.dtb.read_misses 452572 # DTB read misses -system.cpu0.dtb.write_hits 87367482 # DTB write hits -system.cpu0.dtb.write_misses 174484 # DTB write misses +system.cpu0.dtb.read_hits 106854280 # DTB read hits +system.cpu0.dtb.read_misses 451291 # DTB read misses +system.cpu0.dtb.write_hits 87452638 # DTB write hits +system.cpu0.dtb.write_misses 170298 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 43076 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 336 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7862 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 41576 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 658 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7382 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 41749 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 106895499 # DTB read accesses -system.cpu0.dtb.write_accesses 87541966 # DTB write accesses +system.cpu0.dtb.perms_faults 40291 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 107305571 # DTB read accesses +system.cpu0.dtb.write_accesses 87622936 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 193810409 # DTB hits -system.cpu0.dtb.misses 627056 # DTB misses -system.cpu0.dtb.accesses 194437465 # DTB accesses +system.cpu0.dtb.hits 194306918 # DTB hits +system.cpu0.dtb.misses 621589 # DTB misses +system.cpu0.dtb.accesses 194928507 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -525,1171 +529,1172 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 89572 # Table walker walks requested -system.cpu0.itb.walker.walksLong 89572 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1024 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63745 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10456 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 79116 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1699.586683 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 13044.450560 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 78197 98.84% 98.84% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 434 0.55% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 37 0.05% 99.43% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 79 0.10% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 275 0.35% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 59 0.07% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 79116 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 75225 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26620.711200 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21926.293248 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 30000.304563 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 72890 96.90% 96.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 127 0.17% 97.06% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1867 2.48% 99.55% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 130 0.17% 99.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 117 0.16% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 47 0.06% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 31 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 75225 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 417841685688 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.859653 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.347613 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 58676119976 14.04% 14.04% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 359136359212 85.95% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 25573000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 3283500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 186000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 60000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 104000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 417841685688 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 63745 98.42% 98.42% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1024 1.58% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 64769 # Table walker page sizes translated +system.cpu0.itb.walker.walks 88821 # Table walker walks requested +system.cpu0.itb.walker.walksLong 88821 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1050 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63713 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10161 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 78660 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1640.999237 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 13001.605750 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 77771 98.87% 98.87% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 446 0.57% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 46 0.06% 99.50% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 60 0.08% 99.57% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 236 0.30% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 63 0.08% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 12 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 78660 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 74924 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26158.080188 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21735.719179 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 28586.196281 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 72785 97.15% 97.15% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 128 0.17% 97.32% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 1706 2.28% 99.59% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 120 0.16% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 108 0.14% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 38 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 23 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 74924 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 438261516832 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.857100 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 62664607652 14.30% 14.30% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 375564750680 85.69% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 27774000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 4139500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 188000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 57000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 438261516832 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 63713 98.38% 98.38% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1050 1.62% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64763 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 89572 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 89572 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88821 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88821 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64769 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64769 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 154341 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 230754760 # ITB inst hits -system.cpu0.itb.inst_misses 89572 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64763 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64763 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 153584 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 231690538 # ITB inst hits +system.cpu0.itb.inst_misses 88821 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 31365 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 30101 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 227814 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 229340 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 230844332 # ITB inst accesses -system.cpu0.itb.hits 230754760 # DTB hits -system.cpu0.itb.misses 89572 # DTB misses -system.cpu0.itb.accesses 230844332 # DTB accesses -system.cpu0.numCycles 860058385 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 231779359 # ITB inst accesses +system.cpu0.itb.hits 231690538 # DTB hits +system.cpu0.itb.misses 88821 # DTB misses +system.cpu0.itb.accesses 231779359 # DTB accesses +system.cpu0.numCycles 863793222 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 93823767 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 647034006 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 146144434 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 88204037 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 713428063 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 15421284 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2142608 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 370377 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6662477 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 811703 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 935488 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 230526197 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1802314 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 29828 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 825885125 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.917836 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.204243 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 99193613 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 650316460 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 146971248 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 88168636 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 710473999 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15870286 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2085677 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 375453 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6582690 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 821108 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 973136 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 231460528 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1900058 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 29560 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 828440819 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.919217 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.204961 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 462725297 56.03% 56.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 141134334 17.09% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 49183945 5.96% 79.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 172841549 20.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 463819781 55.99% 55.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 141489715 17.08% 73.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 49366419 5.96% 79.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 173764904 20.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 825885125 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.169924 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.752314 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 112769742 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 426082666 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 241448796 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 40086734 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5497187 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 21049410 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2256773 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 670218998 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 24585217 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5497187 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 150343342 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 70257974 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 265091659 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 243360217 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 91334746 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 651968055 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6322268 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 11333163 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 398238 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 892987 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 53687870 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 12055 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 623161441 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1008090615 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 769730678 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 803084 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 561865875 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 61295566 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16618595 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14448752 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 81009207 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 106588320 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 90921259 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9791542 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8386441 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 628410475 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16690332 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 633219394 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2873840 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 57472988 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 37517559 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 288712 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 825885125 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.766716 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.051496 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 828440819 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.170146 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.752861 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 116939951 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 422028211 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 244586455 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 39268558 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5617644 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 21189817 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2362286 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 672848975 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 25418616 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5617644 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 154577177 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 70595603 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 261705373 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 245642920 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 90302102 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 654266166 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6467849 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 11101204 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 403453 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 928162 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 53323892 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11721 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 625141147 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1009026275 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 772228505 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 892399 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 562735066 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 62406074 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16247606 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14088158 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 79534921 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 107241964 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 91079408 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9519471 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8265411 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 630985849 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16282634 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 634912655 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2916139 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 58420750 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 38187791 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 288602 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 828440819 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.766395 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.051588 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 480372364 58.16% 58.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 144500445 17.50% 75.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 122618774 14.85% 90.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 70098834 8.49% 99.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8288641 1.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 6067 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 482464203 58.24% 58.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 143786503 17.36% 75.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 123657330 14.93% 90.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 70325398 8.49% 99.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8201627 0.99% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5758 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 825885125 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 828440819 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 65372240 45.40% 45.40% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 70238 0.05% 45.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 24747 0.02% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 29 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 37918627 26.33% 71.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 40615883 28.21% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 65751499 45.58% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 72629 0.05% 45.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 24296 0.02% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 30 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 37784970 26.19% 71.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 40630472 28.16% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 433018605 68.38% 68.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1583156 0.25% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 81666 0.01% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 80947 0.01% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 109728452 17.33% 85.99% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 88726558 14.01% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 434162938 68.38% 68.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1557110 0.25% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 85116 0.01% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 3 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 85507 0.01% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 110176891 17.35% 86.01% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88845090 13.99% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 633219394 # Type of FU issued -system.cpu0.iq.rate 0.736252 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 144001764 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.227412 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2237858803 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 702176142 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 615023589 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1340714 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 546565 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 499647 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 776393889 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 827259 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2940154 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 634912655 # Type of FU issued +system.cpu0.iq.rate 0.735029 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 144263896 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.227218 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2243978291 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 705234549 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 616677073 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1467869 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 599303 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 545442 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 778270494 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 906057 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2895519 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 13228982 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17998 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 150420 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 6097724 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13298175 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 18246 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 145606 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6202009 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2855732 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4944067 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2767326 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4824800 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5497187 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8555370 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 7804154 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 645228891 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5617644 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8735359 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 7907130 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 647396791 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 106588320 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 90921259 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 14154267 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 60797 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 7667643 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 150420 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2190803 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3056972 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5247775 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 624930976 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 106438227 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7669606 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 107241964 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 91079408 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13794371 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 59022 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 7772545 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 145606 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2195305 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3186569 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5381874 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 626447733 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 106847652 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7850968 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 128084 # number of nop insts executed -system.cpu0.iew.exec_refs 193805308 # number of memory reference insts executed -system.cpu0.iew.exec_branches 117788400 # Number of branches executed -system.cpu0.iew.exec_stores 87367081 # Number of stores executed -system.cpu0.iew.exec_rate 0.726615 # Inst execution rate -system.cpu0.iew.wb_sent 616360773 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 615523236 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 299533919 # num instructions producing a value -system.cpu0.iew.wb_consumers 491459888 # num instructions consuming a value +system.cpu0.iew.exec_nop 128308 # number of nop insts executed +system.cpu0.iew.exec_refs 194298385 # number of memory reference insts executed +system.cpu0.iew.exec_branches 118240799 # Number of branches executed +system.cpu0.iew.exec_stores 87450733 # Number of stores executed +system.cpu0.iew.exec_rate 0.725229 # Inst execution rate +system.cpu0.iew.wb_sent 618051464 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 617222515 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 300479191 # num instructions producing a value +system.cpu0.iew.wb_consumers 493067457 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.715676 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609478 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.714549 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609408 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 50152735 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 16401620 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4928429 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 816336878 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.719835 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.528210 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 50926327 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15994032 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 5054980 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 818740070 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.719212 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.525829 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 559210939 68.50% 68.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 132620550 16.25% 84.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 57447612 7.04% 91.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 19359516 2.37% 94.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13667086 1.67% 95.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9472900 1.16% 96.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6300261 0.77% 97.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3865026 0.47% 98.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14392988 1.76% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 561213375 68.55% 68.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 132109065 16.14% 84.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 58113446 7.10% 91.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 19548895 2.39% 94.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13854430 1.69% 95.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9447713 1.15% 97.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6268110 0.77% 97.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3880157 0.47% 98.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14304879 1.75% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 816336878 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 500561663 # Number of instructions committed -system.cpu0.commit.committedOps 587627818 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 818740070 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 501771314 # Number of instructions committed +system.cpu0.commit.committedOps 588847718 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 178182873 # Number of memory references committed -system.cpu0.commit.loads 93359338 # Number of loads committed -system.cpu0.commit.membars 3999106 # Number of memory barriers committed -system.cpu0.commit.branches 111869987 # Number of branches committed -system.cpu0.commit.fp_insts 487433 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 538915028 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14906557 # Number of function calls committed. +system.cpu0.commit.refs 178821180 # Number of memory references committed +system.cpu0.commit.loads 93943789 # Number of loads committed +system.cpu0.commit.membars 3938709 # Number of memory barriers committed +system.cpu0.commit.branches 112215548 # Number of branches committed +system.cpu0.commit.fp_insts 531565 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 540152053 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14962116 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 407981366 69.43% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1327807 0.23% 69.65% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 64470 0.01% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 71302 0.01% 69.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.68% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 93359338 15.89% 85.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 84823535 14.43% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 408576800 69.39% 69.39% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1307130 0.22% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 67517 0.01% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 75091 0.01% 69.63% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.63% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.63% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.63% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 93943789 15.95% 85.59% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 84877391 14.41% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 587627818 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14392988 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1435053387 # The number of ROB reads -system.cpu0.rob.rob_writes 1285071513 # The number of ROB writes -system.cpu0.timesIdled 1102508 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 34173260 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 94009700955 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 500561663 # Number of Instructions Simulated -system.cpu0.committedOps 587627818 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.718187 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.718187 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.582009 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.582009 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 737541509 # number of integer regfile reads -system.cpu0.int_regfile_writes 438217894 # number of integer regfile writes -system.cpu0.fp_regfile_reads 788412 # number of floating regfile reads -system.cpu0.fp_regfile_writes 466436 # number of floating regfile writes -system.cpu0.cc_regfile_reads 137084844 # number of cc regfile reads -system.cpu0.cc_regfile_writes 137795028 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1439828550 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16463907 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6421526 # number of replacements -system.cpu0.dcache.tags.tagsinuse 508.135251 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 165251545 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6422031 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 25.731976 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 588847718 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14304879 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1439565573 # The number of ROB reads +system.cpu0.rob.rob_writes 1289210941 # The number of ROB writes +system.cpu0.timesIdled 1140163 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 35352403 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93926563172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 501771314 # Number of Instructions Simulated +system.cpu0.committedOps 588847718 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.721488 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.721488 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.580893 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.580893 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 739095549 # number of integer regfile reads +system.cpu0.int_regfile_writes 439787902 # number of integer regfile writes +system.cpu0.fp_regfile_reads 872002 # number of floating regfile reads +system.cpu0.fp_regfile_writes 484356 # number of floating regfile writes +system.cpu0.cc_regfile_reads 137161341 # number of cc regfile reads +system.cpu0.cc_regfile_writes 137881500 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1443535644 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16079939 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6407370 # number of replacements +system.cpu0.dcache.tags.tagsinuse 508.018138 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 166146345 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6407881 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.928438 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2962355000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.135251 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992452 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.992452 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 452 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 369713036 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 369713036 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 86498014 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 86498014 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73594824 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73594824 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 223952 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 223952 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 261481 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 261481 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1906554 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1906554 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1959919 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1959919 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 160092838 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 160092838 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 160316790 # number of overall hits -system.cpu0.dcache.overall_hits::total 160316790 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7115044 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7115044 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7950326 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7950326 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 760555 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 760555 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 841390 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 841390 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 287295 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 287295 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195310 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 195310 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 15065370 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 15065370 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15825925 # number of overall misses -system.cpu0.dcache.overall_misses::total 15825925 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 123619441500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 123619441500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 174765170319 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 174765170319 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 99329075406 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 99329075406 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4513560000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4513560000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4763112500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4763112500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4991000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4991000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 298384611819 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 298384611819 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 298384611819 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 298384611819 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 93613058 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 93613058 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81545150 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81545150 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 984507 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 984507 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1102871 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1102871 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2193849 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2193849 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2155229 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2155229 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 175158208 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 175158208 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 176142715 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 176142715 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076005 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.076005 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.097496 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.097496 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.772524 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.772524 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.762909 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.762909 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130955 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130955 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.090621 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.090621 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086010 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.086010 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089847 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.089847 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17374.374846 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17374.374846 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21982.138886 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 21982.138886 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 118053.548778 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 118053.548778 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15710.541430 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15710.541430 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24387.448159 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24387.448159 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.018138 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992223 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.992223 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 248 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 371124901 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 371124901 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 87218466 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 87218466 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73809320 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73809320 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228978 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 228978 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263867 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 263867 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1900288 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1900288 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1938762 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1938762 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 161027786 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 161027786 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 161256764 # number of overall hits +system.cpu0.dcache.overall_hits::total 161256764 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7088028 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7088028 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7798635 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7798635 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 740346 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 740346 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 850980 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 850980 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 273336 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 273336 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194663 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 194663 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 14886663 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 14886663 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 15627009 # number of overall misses +system.cpu0.dcache.overall_misses::total 15627009 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 124519522000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 124519522000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 171455239141 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 171455239141 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 101116390498 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 101116390498 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4428125500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4428125500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4749567500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4749567500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4799500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4799500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 295974761141 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 295974761141 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 295974761141 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 295974761141 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 94306494 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 94306494 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81607955 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81607955 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 969324 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 969324 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1114847 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1114847 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2173624 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2173624 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2133425 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2133425 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 175914449 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 175914449 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 176883773 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 176883773 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075159 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.075159 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.095562 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.095562 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.763776 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.763776 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.763316 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.763316 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.125751 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.125751 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.091244 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.091244 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084624 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.084624 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088346 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.088346 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17567.583254 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 17567.583254 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21985.288341 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21985.288341 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 118823.462946 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 118823.462946 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16200.301095 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16200.301095 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24398.922754 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24398.922754 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19805.992937 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19805.992937 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18854.165669 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18854.165669 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 31101776 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 27008277 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 772694 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 787427 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.251090 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 34.299404 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19881.874208 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19881.874208 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18939.949490 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18939.949490 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 31639371 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 26128725 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 779388 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 763893 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.595148 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 34.204692 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4324525 # number of writebacks -system.cpu0.dcache.writebacks::total 4324525 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3632070 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3632070 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6394266 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6394266 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4384 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4384 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 147311 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 147311 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 10026336 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 10026336 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 10026336 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 10026336 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3482974 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3482974 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1556060 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1556060 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 753575 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 753575 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 837006 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 837006 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139984 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139984 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195309 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 195309 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5039034 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5039034 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5792609 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5792609 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31951 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31951 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31485 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31485 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 63436 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 63436 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56753773500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56753773500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 38838935578 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 38838935578 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 19682576500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 19682576500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 98248508406 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 98248508406 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1973900000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1973900000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4567861500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4567861500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4933000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4933000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95592709078 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 95592709078 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115275285578 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 115275285578 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5771319500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5771319500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5597630000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5597630000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11368949500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368949500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037206 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037206 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019082 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019082 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765434 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765434 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.758934 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.758934 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063807 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063807 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.090621 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.090621 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028768 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028768 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032886 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032886 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16294.630250 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16294.630250 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24959.793053 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24959.793053 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26118.935076 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26118.935076 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 117380.889033 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 117380.889033 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14100.897245 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14100.897245 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23387.869991 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23387.869991 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 4315919 # number of writebacks +system.cpu0.dcache.writebacks::total 4315919 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3584647 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3584647 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6264689 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6264689 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4628 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4628 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 139100 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 139100 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9849336 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9849336 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9849336 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9849336 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3503381 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3503381 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1533946 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1533946 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 733362 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 733362 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 846352 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 846352 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 134236 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 134236 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194661 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 194661 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5037327 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5037327 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5770689 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5770689 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 33238 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33238 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 33405 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33405 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 66643 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 66643 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56780867000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56780867000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 38418617555 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 38418617555 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 19943250500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 19943250500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 100022529998 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 100022529998 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1962249500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1962249500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4554969500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4554969500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4736500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4736500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95199484555 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 95199484555 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115142735055 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 115142735055 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5997592500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5997592500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5944742000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5944742000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11942334500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11942334500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037149 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037149 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018797 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018797 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.756571 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756571 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.759164 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.759164 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061757 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061757 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.091243 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.091243 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028635 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028635 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032624 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032624 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16207.448462 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16207.448462 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25045.612789 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25045.612789 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27194.278542 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27194.278542 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 118180.768756 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 118180.768756 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14617.908013 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14617.908013 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23399.497074 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23399.497074 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18970.443358 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18970.443358 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19900.408534 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19900.408534 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180630.324559 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180630.324559 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177787.200254 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177787.200254 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179219.205183 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179219.205183 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18898.809737 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18898.809737 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19953.030748 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19953.030748 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180443.844395 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180443.844395 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177959.646759 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177959.646759 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179198.633015 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179198.633015 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6358728 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.935177 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 223756411 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6359240 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.186030 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 6757482 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.935144 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 224272608 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6757994 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 33.186269 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 22852216000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.935177 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.935144 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999873 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999873 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 467353436 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 467353436 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 223756411 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 223756411 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 223756411 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 223756411 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 223756411 # number of overall hits -system.cpu0.icache.overall_hits::total 223756411 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6740667 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6740667 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6740667 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6740667 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6740667 # number of overall misses -system.cpu0.icache.overall_misses::total 6740667 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 78361220616 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 78361220616 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 78361220616 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 78361220616 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 78361220616 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 78361220616 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 230497078 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 230497078 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 230497078 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 230497078 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 230497078 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 230497078 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029244 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029244 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029244 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029244 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029244 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029244 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11625.143419 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 11625.143419 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11625.143419 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11625.143419 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11625.143419 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11625.143419 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 12527067 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1547 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 814769 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.374992 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 469620349 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 469620349 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 224272608 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 224272608 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 224272608 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 224272608 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 224272608 # number of overall hits +system.cpu0.icache.overall_hits::total 224272608 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 7158551 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 7158551 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 7158551 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 7158551 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 7158551 # number of overall misses +system.cpu0.icache.overall_misses::total 7158551 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 82703845756 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 82703845756 # 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miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.030932 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030932 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.030932 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030932 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.030932 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11553.154508 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11553.154508 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11553.154508 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11553.154508 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11553.154508 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11553.154508 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 13180342 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1608 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 863819 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.258222 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 114.857143 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 381387 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 381387 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 381387 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 381387 # 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number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 400520 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 400520 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6758031 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6758031 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6758031 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6758031 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6758031 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6758031 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 70398317173 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 70398317173 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 70398317173 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 70398317173 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 70398317173 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 70398317173 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 74295068991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 74295068991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 74295068991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 74295068991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 74295068991 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 74295068991 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939725498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939725498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027589 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027589 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027589 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027589 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027589 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027589 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11070.171021 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11070.171021 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11070.171021 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11070.171021 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11070.171021 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11070.171021 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.029201 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.029201 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.029201 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.029201 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.029201 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10993.596950 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10993.596950 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10993.596950 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10993.596950 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10993.596950 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10993.596950 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138054.170095 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138054.170095 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8863203 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8872058 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7949 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8609545 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8618519 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 8045 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1112734 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2914685 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16233.717637 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 21584031 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2930348 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.365689 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1094401 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2903307 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16246.409963 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 22353900 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2918996 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 7.658078 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 21271828500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7511.186177 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 88.364339 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 96.668630 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4222.815045 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3387.843530 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 926.839916 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.458446 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005393 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005900 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.257740 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.206778 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056570 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.990827 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1335 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 99 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14229 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 95 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 255 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 575 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 410 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 74 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 796 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4905 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4871 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3657 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.081482 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006042 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.868469 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 436831326 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 436831326 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 607592 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 191548 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 799140 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 4324517 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 4324517 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 114203 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 114203 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36958 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 36958 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 970189 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 970189 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5673182 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5673182 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3273926 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 3273926 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 211331 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 211331 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 607592 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 191548 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5673182 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4244115 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10716437 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 607592 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 191548 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5673182 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4244115 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10716437 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13844 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10570 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 24414 # 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average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35453.709413 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19477.722669 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19477.722669 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 749666.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 749666.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62857.073830 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62857.073830 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33413.183246 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39373.096991 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39373.096991 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145707.870573 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145707.870573 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44085.821155 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40647.608610 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44085.821155 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80780.391099 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52336.642247 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.219344 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 46798.068058 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80744.974469 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 80744.974469 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35481.175033 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35481.175033 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19407.494395 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19407.494395 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 426349.900000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 426349.900000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 63957.230354 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 63957.230354 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34279.139469 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39922.636875 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39922.636875 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 146715.192721 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 146715.192721 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44712.842496 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 41238.288069 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44712.842496 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80744.974469 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52555.493944 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172628.571876 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 155801.953235 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170114.005622 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 170114.005622 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172441.873759 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156085.280202 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170296.466607 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 170296.466607 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171380.524734 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 161120.199068 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171366.482106 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 161483.743669 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 26498119 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13615382 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2337 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 550917 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 550892 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 25 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 1014324 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11851775 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31486 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31485 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 5956604 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 10410037 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1088232 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 474368 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351600 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 519661 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1396851 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1324661 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6359280 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5366614 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 842272 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 835494 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19118379 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20677259 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 436050 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1348581 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 41580269 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 407332384 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 648350241 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1616944 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4971488 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1062271057 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6461178 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 33294085 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.028312 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.165866 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 27252548 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13981170 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2244 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 570842 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 570828 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 1016473 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 12252394 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 33406 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33405 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 5923375 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 10861944 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1063583 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 463812 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352945 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 515465 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1384026 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1310731 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6758031 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5399513 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 852147 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 844897 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20314687 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20641650 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 432749 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1348262 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 42737348 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 432852704 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 646893668 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1600696 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4951880 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1086298948 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6525445 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 34111599 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.027918 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.164740 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 32351497 97.17% 97.17% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 942563 2.83% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 25 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 33159285 97.21% 97.21% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 952300 2.79% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 33294085 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 17918792438 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 34111599 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 18295414402 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 208202715 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 218599021 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9565441520 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 10163463729 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9227310290 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9200637125 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 234328206 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 233049222 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 727701378 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 729789968 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 122053066 # Number of BP lookups -system.cpu1.branchPred.condPredicted 81331643 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6140345 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 85523370 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 55672017 # Number of BTB hits +system.cpu1.branchPred.lookups 123149965 # Number of BP lookups +system.cpu1.branchPred.condPredicted 82495484 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5956200 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 86779618 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 56690061 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 65.095677 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16431061 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 166790 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.326470 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16440472 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 156518 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1719,86 +1724,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 513343 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 513343 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10145 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80504 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 231589 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 281754 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2191.677847 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 13834.020871 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 279857 99.33% 99.33% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1045 0.37% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 593 0.21% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 154 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 32 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 54 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 12 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 281754 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 256242 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 18411.043076 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 15820.375131 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14815.596994 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 254819 99.44% 99.44% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 556 0.22% 99.66% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 633 0.25% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 56 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 78 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 63 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::983040-1.04858e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 256242 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 430767474576 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.581742 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.547950 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 429773436576 99.77% 99.77% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 519356000 0.12% 99.89% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 211618500 0.05% 99.94% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 107822000 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 75775500 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 45293000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 13801500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 19976000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 394000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 430767474576 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 80504 88.81% 88.81% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10145 11.19% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 90649 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 513343 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 527411 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 527411 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10595 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86487 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 240409 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 287002 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2359.187392 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 14719.861354 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 284807 99.24% 99.24% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1123 0.39% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 785 0.27% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 158 0.06% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 41 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 63 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 20 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 287002 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 269681 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19234.134032 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 15959.440473 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 20416.372217 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 266977 99.00% 99.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 731 0.27% 99.27% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1349 0.50% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 143 0.05% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 295 0.11% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 94 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 19 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::851968-917503 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 269681 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 429707115240 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.574612 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.551988 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 428613446240 99.75% 99.75% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 584261000 0.14% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 233148000 0.05% 99.94% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 115723000 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 78401000 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 45162000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 15712000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 20912500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 347500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 2000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 429707115240 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 86487 89.09% 89.09% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10595 10.91% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 97082 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 527411 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 513343 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90649 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 527411 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97082 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90649 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 603992 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97082 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 624493 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 90392235 # DTB read hits -system.cpu1.dtb.read_misses 355030 # DTB read misses -system.cpu1.dtb.write_hits 74292452 # DTB write hits -system.cpu1.dtb.write_misses 158313 # DTB write misses +system.cpu1.dtb.read_hits 91393564 # DTB read hits +system.cpu1.dtb.read_misses 362569 # DTB read misses +system.cpu1.dtb.write_hits 75279430 # DTB write hits +system.cpu1.dtb.write_misses 164842 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 34737 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 572 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 5833 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36642 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 200 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 5827 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 38175 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 90747265 # DTB read accesses -system.cpu1.dtb.write_accesses 74450765 # DTB write accesses +system.cpu1.dtb.perms_faults 40054 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 91756133 # DTB read accesses +system.cpu1.dtb.write_accesses 75444272 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 164684687 # DTB hits -system.cpu1.dtb.misses 513343 # DTB misses -system.cpu1.dtb.accesses 165198030 # DTB accesses +system.cpu1.dtb.hits 166672994 # DTB hits +system.cpu1.dtb.misses 527411 # DTB misses +system.cpu1.dtb.accesses 167200405 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1828,1156 +1834,1157 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 79836 # Table walker walks requested -system.cpu1.itb.walker.walksLong 79836 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 812 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57876 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9466 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 70370 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1202.877647 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 9654.881733 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 70178 99.73% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 41 0.06% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 131 0.19% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-327679 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 82282 # Table walker walks requested +system.cpu1.itb.walker.walksLong 82282 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 773 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59282 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9946 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 72336 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1446.824541 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 11538.500060 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 71995 99.53% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 83 0.11% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 237 0.33% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 12 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 70370 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 68154 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 22918.860228 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 20570.604774 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 17513.278330 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 67528 99.08% 99.08% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 75 0.11% 99.19% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 455 0.67% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 42 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 28 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkWaitTime::total 72336 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 70001 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24228.861016 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 20738.037138 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 24674.307569 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 68717 98.17% 98.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 87 0.12% 98.29% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 984 1.41% 99.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 73 0.10% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 83 0.12% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 23 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 22 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 68154 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 396407660708 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.833666 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.372525 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 65955607768 16.64% 16.64% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 330434317940 83.36% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 16293000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1234500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 163500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 44000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 396407660708 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 57876 98.62% 98.62% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 812 1.38% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 58688 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 70001 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 391052327076 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.846616 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.360520 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 60001678208 15.34% 15.34% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 331032470368 84.65% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 15971500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 2073000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 134000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 391052327076 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 59282 98.71% 98.71% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 773 1.29% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 60055 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 79836 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 79836 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82282 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82282 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58688 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58688 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 138524 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 192024896 # ITB inst hits -system.cpu1.itb.inst_misses 79836 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 60055 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 60055 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 142337 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 193960223 # ITB inst hits +system.cpu1.itb.inst_misses 82282 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 24498 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26113 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 203556 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 206259 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 192104732 # ITB inst accesses -system.cpu1.itb.hits 192024896 # DTB hits -system.cpu1.itb.misses 79836 # DTB misses -system.cpu1.itb.accesses 192104732 # DTB accesses -system.cpu1.numCycles 663967264 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 194042505 # ITB inst accesses +system.cpu1.itb.hits 193960223 # DTB hits +system.cpu1.itb.misses 82282 # DTB misses +system.cpu1.itb.accesses 194042505 # DTB accesses +system.cpu1.numCycles 680051209 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 80600357 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 540678400 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 122053066 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 72103078 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 547218750 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13194102 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1722175 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 292741 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 5852987 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 747163 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 786410 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 191800841 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1580435 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 27130 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 643817634 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.987423 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.222838 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 76309039 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 545586843 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 123149965 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 73130533 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 567094976 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 12846360 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1862646 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 285569 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6032568 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 729307 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 772817 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 193732934 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1488213 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 27982 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 659510102 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.972600 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.218843 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 339738489 52.77% 52.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 118160249 18.35% 71.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 40196713 6.24% 77.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 145722183 22.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 352323655 53.42% 53.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 119769188 18.16% 71.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 40581175 6.15% 77.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 146836084 22.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 643817634 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.183824 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.814315 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 95925032 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 307565159 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 202328162 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 33349835 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4649446 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17381659 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1984856 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 561624259 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21210320 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4649446 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 127605464 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 43917048 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 205458777 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 203595973 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 58590926 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 546425758 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5335623 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9251054 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 227617 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 291872 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 27374536 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 10500 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 518347442 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 840457464 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 646223551 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 691924 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 466279930 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 52067506 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14268129 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 12524757 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 67234415 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 90658674 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 77385188 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8528695 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7392702 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 526120257 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 14498185 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 530312729 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2450487 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 49492350 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 31830796 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 264307 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 643817634 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.823700 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.068099 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 659510102 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.181089 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.802273 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 93216709 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 325116567 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 201438015 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 35171632 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4567179 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17405067 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1892222 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 567399835 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 20537774 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4567179 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 125466899 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 47033211 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 215743407 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 203915656 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 62783750 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 552356795 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5241539 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9909237 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 240791 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 292344 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 29944703 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 11393 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 524936389 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 854810992 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 653637843 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 615050 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 473696954 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 51239429 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15119385 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13351935 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 70628253 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 91219643 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 78311402 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8799360 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7480777 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 531265202 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15384643 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 536975559 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2409415 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 48765571 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 31310459 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 261406 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 659510102 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.814204 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.064087 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 353942401 54.98% 54.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 122398683 19.01% 73.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 101611501 15.78% 89.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 58772797 9.13% 98.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7088607 1.10% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 3645 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 364889522 55.33% 55.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 126119203 19.12% 74.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 101926801 15.45% 89.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 59299384 8.99% 98.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7271358 1.10% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3834 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 643817634 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 659510102 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 53425749 43.94% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 46790 0.04% 43.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 9685 0.01% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 19 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 32795787 26.97% 70.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 35319606 29.05% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 53688772 43.65% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 42849 0.03% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 9758 0.01% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 12 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 33350405 27.12% 70.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 35903096 29.19% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 360430820 67.97% 67.97% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1171247 0.22% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 68672 0.01% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 45220 0.01% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 93137728 17.56% 85.77% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 75458910 14.23% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 365127801 68.00% 68.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1207443 0.22% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 64356 0.01% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 5 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 40592 0.01% 68.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 94109837 17.53% 85.77% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 76425394 14.23% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 530312729 # Type of FU issued -system.cpu1.iq.rate 0.798703 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 121597636 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.229294 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1827371450 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 589808611 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 515064806 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1119763 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 442884 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 412109 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 651211996 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 698285 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2417067 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 536975559 # Type of FU issued +system.cpu1.iq.rate 0.789610 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 122994892 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.229051 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1857852304 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 595160433 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 521544916 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1013221 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 400944 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 372548 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 659338375 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 631992 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2462766 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11379314 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 14413 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 141714 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5438356 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11273364 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 14330 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 146929 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5363484 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2432171 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3747564 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2532880 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 4046276 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4649446 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5786949 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2152685 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 540731877 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4567179 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5912411 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2185508 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 546765447 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 90658674 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 77385188 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12325629 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 58000 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2039251 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 141714 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1867697 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2587615 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4455312 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 523333067 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 90385914 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6476972 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 91219643 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 78311402 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13149679 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 62909 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2062449 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 146929 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1850208 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2506307 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4356515 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 530131647 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 91388835 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6328626 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 113435 # number of nop insts executed -system.cpu1.iew.exec_refs 164677509 # number of memory reference insts executed -system.cpu1.iew.exec_branches 98047931 # Number of branches executed -system.cpu1.iew.exec_stores 74291595 # Number of stores executed -system.cpu1.iew.exec_rate 0.788191 # Inst execution rate -system.cpu1.iew.wb_sent 516143321 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 515476915 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 249234254 # num instructions producing a value -system.cpu1.iew.wb_consumers 407965513 # num instructions consuming a value +system.cpu1.iew.exec_nop 115602 # number of nop insts executed +system.cpu1.iew.exec_refs 166669354 # number of memory reference insts executed +system.cpu1.iew.exec_branches 99325061 # Number of branches executed +system.cpu1.iew.exec_stores 75280519 # Number of stores executed +system.cpu1.iew.exec_rate 0.779547 # Inst execution rate +system.cpu1.iew.wb_sent 522591798 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 521917464 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 252132377 # num instructions producing a value +system.cpu1.iew.wb_consumers 413034686 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.776359 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610920 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.767468 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610439 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 43327267 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14233878 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4192740 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 635627275 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.772664 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.570415 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 42738935 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15123237 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4100199 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 651431241 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.764293 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.565341 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 419865335 66.06% 66.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 112371204 17.68% 83.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 47717309 7.51% 91.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15913228 2.50% 93.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11392527 1.79% 95.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 7668933 1.21% 96.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5369975 0.84% 97.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3184156 0.50% 98.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12144608 1.91% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 432003686 66.32% 66.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 115523895 17.73% 84.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 47761812 7.33% 91.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15857432 2.43% 93.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11422302 1.75% 95.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7738049 1.19% 96.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5451213 0.84% 97.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3205095 0.49% 98.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12467757 1.91% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 635627275 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 416740074 # Number of instructions committed -system.cpu1.commit.committedOps 491126085 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 651431241 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 422487941 # Number of instructions committed +system.cpu1.commit.committedOps 497884267 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 151226191 # Number of memory references committed -system.cpu1.commit.loads 79279359 # Number of loads committed -system.cpu1.commit.membars 3502305 # Number of memory barriers committed -system.cpu1.commit.branches 92953281 # Number of branches committed -system.cpu1.commit.fp_insts 403468 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 451237639 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12195676 # Number of function calls committed. +system.cpu1.commit.refs 152894196 # Number of memory references committed +system.cpu1.commit.loads 79946278 # Number of loads committed +system.cpu1.commit.membars 3616952 # Number of memory barriers committed +system.cpu1.commit.branches 94285217 # Number of branches committed +system.cpu1.commit.fp_insts 364520 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 457066504 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12254498 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 338863536 69.00% 69.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 941904 0.19% 69.19% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 54586 0.01% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 39826 0.01% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 79279359 16.14% 85.35% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 71946832 14.65% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 343931170 69.08% 69.08% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 972359 0.20% 69.27% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 50623 0.01% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 35877 0.01% 69.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.29% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 79946278 16.06% 85.35% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 72947918 14.65% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 491126085 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12144608 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1154417922 # The number of ROB reads -system.cpu1.rob.rob_writes 1077060232 # The number of ROB writes -system.cpu1.timesIdled 910594 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 20149630 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94205821171 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 416740074 # Number of Instructions Simulated -system.cpu1.committedOps 491126085 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.593241 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.593241 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.627652 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.627652 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 618723699 # number of integer regfile reads -system.cpu1.int_regfile_writes 366638237 # number of integer regfile writes -system.cpu1.fp_regfile_reads 681038 # number of floating regfile reads -system.cpu1.fp_regfile_writes 305796 # number of floating regfile writes -system.cpu1.cc_regfile_reads 111144597 # number of cc regfile reads -system.cpu1.cc_regfile_writes 111901561 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1146158029 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14345264 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5008277 # number of replacements -system.cpu1.dcache.tags.tagsinuse 444.234833 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 141116395 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5008789 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.173755 # Average number of references to valid blocks. +system.cpu1.commit.op_class_0::total 497884267 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12467757 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1176002301 # The number of ROB reads +system.cpu1.rob.rob_writes 1089287670 # The number of ROB writes +system.cpu1.timesIdled 891748 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 20541107 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94110305176 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 422487941 # Number of Instructions Simulated +system.cpu1.committedOps 497884267 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.609635 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.609635 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.621259 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.621259 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 627139214 # number of integer regfile reads +system.cpu1.int_regfile_writes 370414988 # number of integer regfile writes +system.cpu1.fp_regfile_reads 604419 # number of floating regfile reads +system.cpu1.fp_regfile_writes 299356 # number of floating regfile writes +system.cpu1.cc_regfile_reads 113711382 # number of cc regfile reads +system.cpu1.cc_regfile_writes 114470989 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1170516156 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15242864 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5157965 # number of replacements +system.cpu1.dcache.tags.tagsinuse 429.133488 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 142089244 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5158477 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.544805 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8487531137500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 444.234833 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.867646 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.867646 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 429.133488 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.838151 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.838151 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 378 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 313835409 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 313835409 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 73808968 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 73808968 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 63012404 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 63012404 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 166300 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 166300 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 49799 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 49799 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1689842 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1689842 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1700596 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1700596 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 136821372 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 136821372 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 136987672 # number of overall hits -system.cpu1.dcache.overall_hits::total 136987672 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 5891473 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 5891473 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6580040 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6580040 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 617645 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 617645 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 417038 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 417038 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243108 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 243108 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 189778 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 189778 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 12471513 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 12471513 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 13089158 # number of overall misses -system.cpu1.dcache.overall_misses::total 13089158 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92058874500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 92058874500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 133118807489 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 133118807489 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16001999882 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 16001999882 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3690480000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3690480000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4542175000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4542175000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4462000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4462000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 225177681989 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 225177681989 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 225177681989 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 225177681989 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 79700441 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 79700441 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 69592444 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 69592444 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 783945 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 783945 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 466837 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 466837 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1932950 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1932950 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1890374 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1890374 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 149292885 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 149292885 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 150076830 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 150076830 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.073920 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.073920 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094551 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.094551 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787868 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787868 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.893327 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.893327 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125770 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125770 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100392 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100392 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083537 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.083537 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087216 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.087216 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15625.782296 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15625.782296 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20230.698824 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20230.698824 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 38370.603835 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 38370.603835 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15180.413643 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15180.413643 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23934.149375 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23934.149375 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 317144363 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 317144363 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 74103111 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 74103111 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 63551574 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 63551574 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 164336 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 164336 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50299 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 50299 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1740316 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1740316 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1762571 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1762571 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 137654685 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 137654685 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 137819021 # number of overall hits +system.cpu1.dcache.overall_hits::total 137819021 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6065944 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6065944 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6987777 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6987777 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 664365 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 664365 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 405961 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 405961 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 258244 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 258244 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193910 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 193910 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13053721 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13053721 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13718086 # number of overall misses +system.cpu1.dcache.overall_misses::total 13718086 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 97739183000 # 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number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5341000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 243496043728 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 243496043728 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 243496043728 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 243496043728 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 80169055 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 80169055 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 70539351 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 70539351 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828701 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 828701 # 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number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075664 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.075664 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.099062 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.099062 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.801694 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.801694 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.889758 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.889758 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.129215 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.129215 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099112 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099112 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086616 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.086616 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090526 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.090526 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16112.773708 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16112.773708 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20858.831174 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20858.831174 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 39667.681654 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 39667.681654 # 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average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 4151520 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 21118604 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 339495 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 658226 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.228516 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 32.084123 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18653.381954 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18653.381954 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17750.001256 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17750.001256 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4190229 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 23645788 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 332306 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 708476 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.609550 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 33.375567 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3259663 # number of writebacks -system.cpu1.dcache.writebacks::total 3259663 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 2995366 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 2995366 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5317058 # 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number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4405000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4405000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69408796161 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 69408796161 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83588377161 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 83588377161 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 764918000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 764918000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 914224500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 914224500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1679142500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1679142500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036337 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036337 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018148 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018148 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787785 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787785 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.885046 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.885046 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060652 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060652 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100391 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100391 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027859 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027859 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031828 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031828 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14492.690187 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14492.690187 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21723.519940 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21723.519940 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22959.909647 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22959.909647 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 37337.151070 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 37337.151070 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14353.007156 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14353.007156 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22934.575844 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22934.575844 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3362559 # number of writebacks +system.cpu1.dcache.writebacks::total 3362559 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3121386 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3121386 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5664444 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5664444 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3068 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3068 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 133009 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 133009 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8785830 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8785830 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8785830 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8785830 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2944558 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2944558 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1323333 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1323333 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 664291 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 664291 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 402893 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 402893 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125235 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125235 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193904 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 193904 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4267891 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4267891 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4932182 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4932182 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5159 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5159 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4882 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4882 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10041 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10041 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44629208000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44629208000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 29351732295 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 29351732295 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15227596000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15227596000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 15536076712 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 15536076712 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1817525500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1817525500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4430771000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4430771000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5279000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5279000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73980940295 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 73980940295 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 89208536295 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 89208536295 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 520581000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 520581000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 549653500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 549653500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1070234500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1070234500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036729 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036729 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018760 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018760 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.801605 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.801605 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.883034 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.883034 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062663 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062663 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099109 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099109 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028319 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028319 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032548 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032548 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15156.504983 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15156.504983 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22180.155936 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22180.155936 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22923.080397 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22923.080397 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 38561.297198 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 38561.297198 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14512.919711 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14512.919711 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22850.333155 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22850.333155 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16688.461382 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16688.461382 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17499.302791 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17499.302791 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112059.478465 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 112059.478465 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 127489.122856 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 127489.122856 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 119964.456669 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 119964.456669 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17334.308748 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17334.308748 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18087.032533 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18087.032533 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100907.346385 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 100907.346385 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 112587.771405 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 112587.771405 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 106586.445573 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 106586.445573 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5544230 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.780204 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 185921865 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5544742 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 33.531202 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 5202817 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.771617 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 188211208 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5203329 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 36.171306 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8527218243000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.780204 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980039 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.980039 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.771617 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980023 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980023 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 389132386 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 389132386 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 185921865 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 185921865 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 185921865 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 185921865 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 185921865 # number of overall hits -system.cpu1.icache.overall_hits::total 185921865 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5871956 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5871956 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5871956 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5871956 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5871956 # number of overall misses -system.cpu1.icache.overall_misses::total 5871956 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64156067699 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 64156067699 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 64156067699 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 64156067699 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 64156067699 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 64156067699 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 191793821 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 191793821 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 191793821 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 191793821 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 191793821 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 191793821 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030616 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030616 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030616 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030616 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030616 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030616 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10925.842717 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10925.842717 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10925.842717 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10925.842717 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10925.842717 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10925.842717 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 9696468 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 348 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 701587 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.820763 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 69.600000 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 392655056 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 392655056 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 188211208 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 188211208 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 188211208 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 188211208 # 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number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 61642094935 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 61642094935 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 193725859 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 193725859 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 193725859 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 193725859 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 193725859 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 193725859 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028466 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.028466 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028466 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.028466 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028466 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.028466 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11177.877790 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 11177.877790 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11177.877790 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 11177.877790 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11177.877790 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 11177.877790 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 9398442 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 360 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 665033 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.132294 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 60 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 327212 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 327212 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 327212 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 327212 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 327212 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 327212 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5544744 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5544744 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5544744 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5544744 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5544744 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5544744 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 311313 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 311313 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 311313 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 311313 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 311313 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 311313 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5203338 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5203338 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5203338 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5203338 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5203338 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5203338 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 57863828928 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 57863828928 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 57863828928 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 57863828928 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 57863828928 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 57863828928 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 55550609345 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 55550609345 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 55550609345 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 55550609345 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 55550609345 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 55550609345 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8907998 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8907998 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8907998 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 8907998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028910 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028910 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028910 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.028910 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028910 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.028910 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10435.798105 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10435.798105 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10435.798105 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10435.798105 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10435.798105 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10435.798105 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026859 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026859 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026859 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.026859 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026859 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.026859 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10675.956347 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10675.956347 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10675.956347 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10675.956347 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10675.956347 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10675.956347 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132955.194030 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132955.194030 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6820164 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6823757 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 3326 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7284852 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7288644 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 3499 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 803331 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 1997658 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13422.615868 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 18456162 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2013697 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 9.165312 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9617415490500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 3897.343042 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.015363 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 51.895680 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3723.378261 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 4768.192327 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 915.791195 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.237875 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004029 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003167 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.227257 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.291027 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055895 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.819251 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1310 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14644 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 29 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 243 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 653 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 377 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 38 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1361 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5328 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4585 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3240 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.079956 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.893799 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 360770404 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 360770404 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 497732 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168884 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 666616 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3259650 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3259650 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 66819 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 66819 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31621 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 31621 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 793791 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 793791 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4983800 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4983800 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2698278 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2698278 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 190326 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 190326 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 497732 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 168884 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4983800 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3492069 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9142485 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 497732 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168884 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4983800 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3492069 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9142485 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10518 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7585 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 18103 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 13 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 13 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 142287 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 142287 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158148 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 158148 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 268312 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 268312 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 560943 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 560943 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 929119 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 929119 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 221533 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 221533 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10518 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7585 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 560943 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1197431 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1776477 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10518 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7585 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 560943 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1197431 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1776477 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 440507000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 317156000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 757663000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 4278657000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 4278657000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3704095999 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3704095999 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4317497 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4317497 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13921759999 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 13921759999 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 19818008500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 19818008500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34488387987 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34488387987 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 13205591500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 13205591500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 440507000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 317156000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 19818008500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 48410147986 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 68985819486 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 440507000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 317156000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 19818008500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 48410147986 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 68985819486 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 508250 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 176469 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 684719 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3259663 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3259663 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 209106 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 209106 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 189769 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 189769 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1062103 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1062103 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5544743 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 5544743 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3627397 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3627397 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 411859 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 411859 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 508250 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 176469 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5544743 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4689500 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10918962 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 508250 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 176469 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5544743 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4689500 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10918962 # 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Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 83.839548 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 89.493119 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2981.742674 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3164.985598 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 912.317885 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.362298 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005117 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005462 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.181991 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.193175 # 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number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 524142000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 406910000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16715141000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 43432624477 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 61078817477 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 524142000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 406910000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16715141000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 43432624477 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46701535932 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 107780353409 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8404500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 710244000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 718648500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 860387000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 860387000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 479244000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 487648500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 512985500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 512985500 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8404500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1570631000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1579035500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020679 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.042058 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026189 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 992229500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1000634000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022614 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.047216 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028954 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.680454 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.680454 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.833371 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.833371 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.647921 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.647921 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825645 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825645 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219320 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219320 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.101167 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101167 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.254968 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254968 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.537852 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.537852 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020679 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.042058 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.101167 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246894 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159052 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020679 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.042058 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.101167 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246894 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.215298 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.215298 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.110574 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110574 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.262911 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.262911 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.555707 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.555707 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022614 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047216 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.110574 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.251947 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.169061 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022614 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047216 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.110574 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.251947 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.219807 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 35692.532902 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55678.903673 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55678.903673 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32979.671319 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32979.671319 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18419.859853 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18419.859853 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 496937.125000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 496937.125000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45685.429720 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45685.429720 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29329.808020 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31064.411200 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31064.411200 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53610.629337 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53610.629337 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34006.016519 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32513.032004 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34006.016519 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55678.903673 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 38916.070629 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.236233 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 46295.659092 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64713.594163 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 64713.594163 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32826.799579 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32826.799579 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18485.698746 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18485.698746 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 802083 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 802083 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48485.514714 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48485.514714 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29051.975048 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32412.588508 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32412.588508 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 54126.588312 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 54126.588312 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35575.463241 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33627.728921 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35575.463241 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64713.594163 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42466.849098 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104049.809552 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 104257.725228 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 119981.453075 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 119981.453075 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 92894.747044 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 93311.997704 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 105076.915199 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 105076.915199 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 112211.973994 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 112274.992890 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 98817.797032 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 98994.261971 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 21930537 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11284587 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1296 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 520648 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 520636 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 12 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 828450 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10092423 # Transaction distribution +system.cpu1.toL2Bus.snoop_filter.tot_requests 21572446 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11121796 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 524506 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 524489 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 17 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 847854 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9869269 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 7171 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7171 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 4200793 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 9135588 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 838070 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 423377 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 345989 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 462829 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1138657 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1069017 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5544744 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4688366 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 419379 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 411859 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16633313 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16198816 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 385145 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1121131 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 34338405 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 354864624 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 515112392 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1411752 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4066000 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 875454768 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5438478 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 27571945 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.031057 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.173474 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::WriteReq 4882 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4882 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 4416651 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 8880510 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 907695 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 13 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 421769 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350236 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 471619 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1189775 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1122660 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5203338 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4763767 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 409409 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 401778 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15609171 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16649345 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 393406 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1143795 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 33795717 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 333013936 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 531452177 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1432064 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4124520 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 870022697 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5627139 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 27397107 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.032027 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.176075 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 26715663 96.89% 96.89% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 856270 3.11% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 12 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 26519684 96.80% 96.80% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 877406 3.20% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 17 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 27571945 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 14479823475 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 27397107 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 14402314458 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 180399406 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 173479331 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8321735869 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7809268085 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7455510168 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7687735490 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 208987874 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 214700392 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 613445865 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 628828296 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40368 # Transaction distribution -system.iobus.trans_dist::ReadResp 40368 # Transaction distribution +system.iobus.trans_dist::ReadReq 40404 # Transaction distribution +system.iobus.trans_dist::ReadResp 40404 # Transaction distribution system.iobus.trans_dist::WriteReq 136681 # Transaction distribution system.iobus.trans_dist::WriteResp 136681 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47892 # Packet count per connected master and slave (bytes) @@ -2996,11 +3003,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122826 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231192 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231192 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354098 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354170 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3017,11 +3024,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155933 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496803 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7497091 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36369000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -3050,71 +3057,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 565777885 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 566086533 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92876000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147888000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147960000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115577 # number of replacements -system.iocache.tags.tagsinuse 11.305567 # Cycle average of tags in use +system.iocache.tags.replacements 115614 # number of replacements +system.iocache.tags.tagsinuse 11.301705 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115593 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9126912991000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.834509 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.471058 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239657 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466941 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706598 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9126915715000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.837722 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.463983 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239858 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466499 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706357 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040721 # Number of tag accesses -system.iocache.tags.data_accesses 1040721 # Number of data accesses +system.iocache.tags.tag_accesses 1041045 # Number of tag accesses +system.iocache.tags.data_accesses 1041045 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8868 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8905 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8941 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8868 # number of demand (read+write) misses -system.iocache.demand_misses::total 8908 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8904 # number of demand (read+write) misses +system.iocache.demand_misses::total 8944 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8868 # number of overall misses -system.iocache.overall_misses::total 8908 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1707562057 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1712757057 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8904 # number of overall misses +system.iocache.overall_misses::total 8944 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5199000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1751682968 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1756881968 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13922427828 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13922427828 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1707562057 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1713126057 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1707562057 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1713126057 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13928366565 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13928366565 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5568000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1751682968 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1757250968 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5568000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1751682968 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1757250968 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8868 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8941 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8868 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8908 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8904 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8944 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8868 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8908 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3128,55 +3135,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 192553.231507 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 192336.558899 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140513.513514 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 196729.893082 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 196497.256235 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130447.753429 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130447.753429 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 192553.231507 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 192313.208015 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 192553.231507 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 192313.208015 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 35527 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130503.397094 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130503.397094 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139200 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 196729.893082 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 196472.603757 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139200 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 196729.893082 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 196472.603757 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 36915 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3511 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3596 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.118770 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.265573 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106695 # number of writebacks +system.iocache.writebacks::total 106695 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8868 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8905 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8904 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8941 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8868 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8908 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8904 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8944 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8868 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8908 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1264162057 # 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number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1264162057 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1267726057 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1264162057 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1267726057 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8591966565 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8591966565 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3568000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1306482968 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1310050968 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3568000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1306482968 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1310050968 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3190,617 +3197,621 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142553.231507 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 142336.558899 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90513.513514 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 146729.893082 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 146497.256235 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80447.753429 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80447.753429 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 142553.231507 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 142313.208015 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 142553.231507 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 142313.208015 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80503.397094 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80503.397094 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89200 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 146729.893082 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 146472.603757 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89200 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 146729.893082 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 146472.603757 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1523284 # number of replacements -system.l2c.tags.tagsinuse 63784.617798 # Cycle average of tags in use -system.l2c.tags.total_refs 5785768 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1584080 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.652447 # Average number of references to valid blocks. +system.l2c.tags.replacements 1633941 # number of replacements +system.l2c.tags.tagsinuse 63813.673701 # Cycle average of tags in use +system.l2c.tags.total_refs 5902225 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1694519 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.483127 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17262.204967 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 288.051541 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 383.464514 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4972.263689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 12806.585942 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17387.012671 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 85.287470 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 93.857044 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2455.379438 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4782.512624 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3267.997898 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.263400 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004395 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.005851 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075871 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.195413 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.265305 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001301 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001432 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.037466 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.072975 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.049866 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.973276 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10918 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 244 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49634 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1058 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 384 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9467 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 18421.604397 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 145.885026 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 177.213344 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5018.050694 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 11022.844294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.408023 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 214.913940 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 271.296665 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2354.078258 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5504.302098 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10936.076961 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.281091 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002226 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002704 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.076569 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.168195 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148734 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003279 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.004140 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.035920 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.083989 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.166871 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.973719 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 11165 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 256 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49157 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1008 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 549 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9608 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2538 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5035 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 41740 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.166595 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.757355 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 71725289 # Number of tag accesses -system.l2c.tags.data_accesses 71725289 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2493194 # number of Writeback hits -system.l2c.Writeback_hits::total 2493194 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 29135 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 32441 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 61576 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6380 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5628 # 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number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 294077 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2919876 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6589 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 618480 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 796832 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 297252 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5967 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4162 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 524459 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 693950 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 294077 # number of demand (read+write) hits -system.l2c.demand_hits::total 3246125 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6589 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4357 # number of overall hits -system.l2c.overall_hits::cpu0.inst 618480 # number of overall hits -system.l2c.overall_hits::cpu0.data 796832 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 297252 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5967 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4162 # number of overall hits -system.l2c.overall_hits::cpu1.inst 524459 # number of overall hits -system.l2c.overall_hits::cpu1.data 693950 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 294077 # number of overall hits -system.l2c.overall_hits::total 3246125 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 49689 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 45204 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 94893 # 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mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.275073 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.365824 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.105927 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.483273 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537434 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.279035 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.315088 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.061517 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.229048 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.437597 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.332404 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73616.390294 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73553.635707 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73586.071387 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76461.516819 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76478.098585 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76469.084354 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 168609.821410 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139760.614749 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 163870.610859 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127419.322885 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137909.099139 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127550.149743 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134512.466714 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 156548.463338 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127419.322885 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 161222.616076 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127550.149743 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 137149.843686 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 159534.904503 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127419.322885 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 161222.616076 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127550.149743 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 137149.843686 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 159534.904503 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154627.836374 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154441.302124 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 86074.662954 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131897.898098 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153111.943243 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102979.361316 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 143811.944666 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 74922.726391 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132599.588326 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153294.552702 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88074.559607 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 144978.309426 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153875.457674 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153866.490599 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 94736.584494 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 136559.706586 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81318.507820 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 137433.631498 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 60136 # Transaction distribution -system.membus.trans_dist::ReadResp 965246 # Transaction distribution -system.membus.trans_dist::WriteReq 38656 # Transaction distribution -system.membus.trans_dist::WriteResp 38656 # Transaction distribution -system.membus.trans_dist::Writeback 1296915 # Transaction distribution -system.membus.trans_dist::CleanEvict 243951 # Transaction distribution -system.membus.trans_dist::UpgradeReq 452760 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 304384 # Transaction distribution -system.membus.trans_dist::UpgradeResp 121976 # Transaction distribution +system.membus.trans_dist::ReadReq 59756 # Transaction distribution +system.membus.trans_dist::ReadResp 1037606 # Transaction distribution +system.membus.trans_dist::WriteReq 38287 # Transaction distribution +system.membus.trans_dist::WriteResp 38287 # Transaction distribution +system.membus.trans_dist::Writeback 1371305 # Transaction distribution +system.membus.trans_dist::CleanEvict 262648 # Transaction distribution +system.membus.trans_dist::UpgradeReq 440849 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 306045 # Transaction distribution +system.membus.trans_dist::UpgradeResp 117782 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 662340 # Transaction distribution -system.membus.trans_dist::ReadExResp 641281 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 905110 # Transaction distribution +system.membus.trans_dist::ReadExReq 681386 # Transaction distribution +system.membus.trans_dist::ReadExResp 660425 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 977850 # Transaction distribution system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122826 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26816 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5450054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5599774 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342030 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342030 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5941804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25318 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5711814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5860036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343033 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 343033 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6203069 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155933 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53632 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174888448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 175098585 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7250496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7250496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 182349081 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 659296 # Total snoops (count) -system.membus.snoop_fanout::samples 4073524 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50636 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 185527680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 185734821 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7281536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 193016357 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 652692 # Total snoops (count) +system.membus.snoop_fanout::samples 4246933 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4073524 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4246933 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4073524 # Request fanout histogram -system.membus.reqLayer0.occupancy 98143499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4246933 # Request fanout histogram +system.membus.reqLayer0.occupancy 98658999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22747469 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21380469 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9016528809 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9518454911 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8432717951 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8904498116 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 230475062 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 230513312 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3854,56 +3865,56 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 11519638 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5862055 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2048796 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 167370 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 156134 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11236 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 60138 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4755206 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38656 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38656 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3790142 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1500041 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 506577 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 316392 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 822969 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1127077 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1127077 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4702306 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 11772030 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5986527 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2060183 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 193514 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 180675 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 12839 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 59758 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4863251 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38287 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38287 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3950228 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1568757 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 493482 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 318513 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 811995 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1145198 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1145198 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4810734 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9146865 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6326733 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15473598 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 285949105 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 180962856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 466911961 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3420267 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 13372960 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.331842 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.472656 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9122705 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6709100 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15831805 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 283955252 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 196820081 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 480775333 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3520564 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 13735314 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.326662 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.470981 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 8946480 66.90% 66.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4415244 33.02% 99.92% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11236 0.08% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9261350 67.43% 67.43% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4461125 32.48% 99.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 12839 0.09% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13372960 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8776402150 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 13735314 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9000721880 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2601544 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2650288 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5338662327 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5320683808 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3896618177 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4098533956 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 14407 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 13032 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 7094 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5368 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |