diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt | 6110 |
1 files changed, 3160 insertions, 2950 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index e64b12ad0..828771ce9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,178 +1,178 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.422278 # Number of seconds simulated -sim_ticks 47422277747000 # Number of ticks simulated -final_tick 47422277747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.345385 # Number of seconds simulated +sim_ticks 47345385235500 # Number of ticks simulated +final_tick 47345385235500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91986 # Simulator instruction rate (inst/s) -host_op_rate 108182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4717167353 # Simulator tick rate (ticks/s) -host_mem_usage 870208 # Number of bytes of host memory used -host_seconds 10053.13 # Real time elapsed on the host -sim_insts 924745220 # Number of instructions simulated -sim_ops 1087564829 # Number of ops (including micro ops) simulated +host_inst_rate 106392 # Simulator instruction rate (inst/s) +host_op_rate 125133 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5453309126 # Simulator tick rate (ticks/s) +host_mem_usage 767036 # Number of bytes of host memory used +host_seconds 8681.96 # Real time elapsed on the host +sim_insts 923688991 # Number of instructions simulated +sim_ops 1086395427 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 123008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 83392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1145824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 12461528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 54523392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 250240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 244864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 679904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 13804768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 35481280 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 451200 # Number of bytes read from this memory -system.physmem.bytes_read::total 119249400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1145824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 679904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1825728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 92428416 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 161152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 146432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4268768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 16023832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 20180672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 179840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 156416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3463536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 11559072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 14510464 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 437312 # Number of bytes read from this memory +system.physmem.bytes_read::total 71087496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4268768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3463536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7732304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 86253568 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 92449232 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1922 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 33856 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 194733 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 851928 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3826 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10667 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 215714 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 554395 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 7050 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1879304 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1444194 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 86274384 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2518 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2288 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 82652 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 250394 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 315323 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2810 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2444 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 54162 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 180625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 226726 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6833 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1126775 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1347712 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1446797 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 24162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 262778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 1149742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 5277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 5163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 291103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 748199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2514628 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 24162 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14337 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 38499 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1949051 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1350315 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 90162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 338445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 426244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 73155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 244144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 306481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1501466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 90162 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 73155 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 163317 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1821795 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 440 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1949489 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1949051 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 24162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 263217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 1149742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 5277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 5163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 291103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 748199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4464118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1879304 # Number of read requests accepted -system.physmem.writeReqs 1600997 # Number of write requests accepted -system.physmem.readBursts 1879304 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1600997 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 120227392 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 48064 # Total number of bytes read from write queue -system.physmem.bytesWritten 101998144 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 119249400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 102318032 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 751 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7249 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 97584 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 111371 # Per bank write bursts -system.physmem.perBankRdBursts::1 133364 # Per bank write bursts -system.physmem.perBankRdBursts::2 107237 # Per bank write bursts -system.physmem.perBankRdBursts::3 129396 # Per bank write bursts -system.physmem.perBankRdBursts::4 116369 # Per bank write bursts -system.physmem.perBankRdBursts::5 129089 # Per bank write bursts -system.physmem.perBankRdBursts::6 116664 # Per bank write bursts -system.physmem.perBankRdBursts::7 120571 # Per bank write bursts -system.physmem.perBankRdBursts::8 118226 # Per bank write bursts -system.physmem.perBankRdBursts::9 133705 # Per bank write bursts -system.physmem.perBankRdBursts::10 98234 # Per bank write bursts -system.physmem.perBankRdBursts::11 110272 # Per bank write bursts -system.physmem.perBankRdBursts::12 110364 # Per bank write bursts -system.physmem.perBankRdBursts::13 124983 # Per bank write bursts -system.physmem.perBankRdBursts::14 111960 # Per bank write bursts -system.physmem.perBankRdBursts::15 106748 # Per bank write bursts -system.physmem.perBankWrBursts::0 99185 # Per bank write bursts -system.physmem.perBankWrBursts::1 109011 # Per bank write bursts -system.physmem.perBankWrBursts::2 97054 # Per bank write bursts -system.physmem.perBankWrBursts::3 108172 # Per bank write bursts -system.physmem.perBankWrBursts::4 98286 # Per bank write bursts -system.physmem.perBankWrBursts::5 106076 # Per bank write bursts -system.physmem.perBankWrBursts::6 100140 # Per bank write bursts -system.physmem.perBankWrBursts::7 103851 # Per bank write bursts -system.physmem.perBankWrBursts::8 98795 # Per bank write bursts -system.physmem.perBankWrBursts::9 98239 # Per bank write bursts -system.physmem.perBankWrBursts::10 89198 # Per bank write bursts -system.physmem.perBankWrBursts::11 97505 # Per bank write bursts -system.physmem.perBankWrBursts::12 95822 # Per bank write bursts -system.physmem.perBankWrBursts::13 102116 # Per bank write bursts -system.physmem.perBankWrBursts::14 95043 # Per bank write bursts -system.physmem.perBankWrBursts::15 95228 # Per bank write bursts +system.physmem.bw_write::total 1822234 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1821795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 90162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 338885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 426244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 73155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 244144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 306481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3323700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1126775 # Number of read requests accepted +system.physmem.writeReqs 2040290 # Number of write requests accepted +system.physmem.readBursts 1126775 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2040290 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 72094336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19264 # Total number of bytes read from write queue +system.physmem.bytesWritten 130093376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 71087496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 130432784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 301 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7556 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 121134 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 65675 # Per bank write bursts +system.physmem.perBankRdBursts::1 75833 # Per bank write bursts +system.physmem.perBankRdBursts::2 67256 # Per bank write bursts +system.physmem.perBankRdBursts::3 67290 # Per bank write bursts +system.physmem.perBankRdBursts::4 71240 # Per bank write bursts +system.physmem.perBankRdBursts::5 82191 # Per bank write bursts +system.physmem.perBankRdBursts::6 67013 # Per bank write bursts +system.physmem.perBankRdBursts::7 67787 # Per bank write bursts +system.physmem.perBankRdBursts::8 61707 # Per bank write bursts +system.physmem.perBankRdBursts::9 85775 # Per bank write bursts +system.physmem.perBankRdBursts::10 61014 # Per bank write bursts +system.physmem.perBankRdBursts::11 72520 # Per bank write bursts +system.physmem.perBankRdBursts::12 65793 # Per bank write bursts +system.physmem.perBankRdBursts::13 74631 # Per bank write bursts +system.physmem.perBankRdBursts::14 69278 # Per bank write bursts +system.physmem.perBankRdBursts::15 71471 # Per bank write bursts +system.physmem.perBankWrBursts::0 122526 # Per bank write bursts +system.physmem.perBankWrBursts::1 130111 # Per bank write bursts +system.physmem.perBankWrBursts::2 125889 # Per bank write bursts +system.physmem.perBankWrBursts::3 127486 # Per bank write bursts +system.physmem.perBankWrBursts::4 126972 # Per bank write bursts +system.physmem.perBankWrBursts::5 136977 # Per bank write bursts +system.physmem.perBankWrBursts::6 126845 # Per bank write bursts +system.physmem.perBankWrBursts::7 128268 # Per bank write bursts +system.physmem.perBankWrBursts::8 123854 # Per bank write bursts +system.physmem.perBankWrBursts::9 125736 # Per bank write bursts +system.physmem.perBankWrBursts::10 125360 # Per bank write bursts +system.physmem.perBankWrBursts::11 131761 # Per bank write bursts +system.physmem.perBankWrBursts::12 119984 # Per bank write bursts +system.physmem.perBankWrBursts::13 126166 # Per bank write bursts +system.physmem.perBankWrBursts::14 125889 # Per bank write bursts +system.physmem.perBankWrBursts::15 128885 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 47422276363500 # Total gap between requests +system.physmem.numWrRetry 614 # Number of times write queue was full causing retry +system.physmem.totGap 47345383810500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) -system.physmem.readPktSize::4 21333 # Read request sizes (log2) +system.physmem.readPktSize::4 21334 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1857934 # Read request sizes (log2) +system.physmem.readPktSize::6 1105404 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1598394 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 506038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 360780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 256406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 156907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 129304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 95738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 81613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 74114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 66527 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 41507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 23594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 21466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2037687 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 495851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 234383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 118863 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 70028 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 51854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 39852 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 34830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -188,184 +188,141 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 29130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 37353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 51054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 76742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 83422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 92810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 99100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 114191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 124207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 117512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 121939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 125600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 118087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 27656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 21524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 15466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 10008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 975956 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.699905 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.562466 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 280.517231 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 518192 53.10% 53.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 197775 20.26% 73.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 73464 7.53% 80.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 39205 4.02% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 32875 3.37% 88.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 20645 2.12% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14690 1.51% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16974 1.74% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 62136 6.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 975956 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 85700 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.919883 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 65.914571 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 85693 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 30752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 58821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 69578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 77864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 89177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 97306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 106336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 112038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 121912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 121861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 124135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 125483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 131449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 118558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 117002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 113440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 105060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 29238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 25813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 22998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 20720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 18797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 16980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 15279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 13444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 11652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 10311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 9180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 8124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 7426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 6654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 6134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 5597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 5145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 4620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 4249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 3863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 3550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 3131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1502 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1131657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.664737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 108.493979 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 249.059793 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 718344 63.48% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 219262 19.38% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 56669 5.01% 87.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 25497 2.25% 90.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20148 1.78% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11584 1.02% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9545 0.84% 93.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8895 0.79% 94.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 61713 5.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1131657 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 74075 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.207155 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 65.468886 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 74072 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 85700 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 85700 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.596511 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.559355 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.221946 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 76419 89.17% 89.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4825 5.63% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 861 1.00% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 776 0.91% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 493 0.58% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 137 0.16% 97.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 117 0.14% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 137 0.16% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 585 0.68% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 72 0.08% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 76 0.09% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 72 0.08% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 110 0.13% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 48 0.06% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 42 0.05% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 81 0.09% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 124 0.14% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 28 0.03% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 35 0.04% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 50 0.06% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 194 0.23% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 14 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 23 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 14 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 54 0.06% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 16 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 21 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 26 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 106 0.12% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 28 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 8 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 9 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 15 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 15 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 11 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 6 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 4 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 6 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 85700 # Writes before turning the bus around for reads -system.physmem.totQLat 131185455773 # Total ticks spent queuing -system.physmem.totMemAccLat 166408324523 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9392765000 # Total ticks spent in databus transfers -system.physmem.avgQLat 69833.25 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 74075 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 74075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.441228 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.793858 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 451.068024 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-1023 74039 99.95% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1024-2047 13 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2048-3071 9 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3072-4095 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4096-5119 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5120-6143 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26624-27647 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33792-34815 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64512-65535 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 74075 # Writes before turning the bus around for reads +system.physmem.totQLat 56140564025 # Total ticks spent queuing +system.physmem.totMemAccLat 77261951525 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5632370000 # Total ticks spent in databus transfers +system.physmem.avgQLat 49837.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 88583.25 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.54 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.15 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 68587.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.75 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.75 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.84 # Average write queue length when enqueuing -system.physmem.readRowHits 1529879 # Number of row buffer hits during reads -system.physmem.writeRowHits 966437 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.64 # Row buffer hit rate for writes -system.physmem.avgGap 13625912.35 # Average gap between requests -system.physmem.pageHitRate 71.89 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45568926392500 # Time in different power states -system.physmem.memoryStateTime::REF 1583533900000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 269814192000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3837713040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3540506760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2093990250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1931824125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7519675800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 7132967400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 5325102000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5002210080 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3097392308400 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3097392308400 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1175879799405 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1172220553305 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27421890099000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27425099964000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31713938687895 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31712320334070 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.756196 # Core power per rank (mW) -system.physmem.averagePower::1 668.722070 # Core power per rank (mW) +system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing +system.physmem.readRowHits 851046 # Number of row buffer hits during reads +system.physmem.writeRowHits 1176475 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.88 # Row buffer hit rate for writes +system.physmem.avgGap 14949293.37 # Average gap between requests +system.physmem.pageHitRate 64.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4318120800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2356117500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4401423000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6642421200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3092370278400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1163515422960 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27386602512000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31660206295860 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.707358 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45559855793000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1580966400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 204562609000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 4237153200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2311938750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4385027400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6529429440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3092370278400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1165548686490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27384818947500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31660201461180 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.707256 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45556862760500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1580966400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 207555509500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -398,16 +355,24 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 136692903 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91051024 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6675955 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 96641264 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 62499971 # Number of BTB hits +system.cpu0.branchPred.lookups 145356452 # Number of BP lookups +system.cpu0.branchPred.condPredicted 96435082 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7088203 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 101789401 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 67765064 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 64.672137 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 18343531 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 188881 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.573792 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20004195 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 205158 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -429,27 +394,97 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 580611 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 580611 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13679 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 93135 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 259311 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 321300 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 1669.368192 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 10492.971715 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-32767 317448 98.80% 98.80% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-65535 2037 0.63% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-98303 845 0.26% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-131071 576 0.18% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-163839 232 0.07% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::163840-196607 45 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-229375 28 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::229376-262143 26 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-294911 42 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::294912-327679 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-360447 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 321300 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 293805 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 15781.864128 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 13334.413537 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14277.098383 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 291279 99.14% 99.14% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1809 0.62% 99.76% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 367 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 189 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 105 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 293805 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 521650035508 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.610400 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.526555 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 520697119508 99.82% 99.82% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 543124000 0.10% 99.92% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 195186500 0.04% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 85165500 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 70245500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 34070500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 11934000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 12740000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 448500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 521650035508 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 93135 87.19% 87.19% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 13679 12.81% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 106814 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 580611 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 580611 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106814 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106814 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 687425 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 98285730 # DTB read hits -system.cpu0.dtb.read_misses 371363 # DTB read misses -system.cpu0.dtb.write_hits 82429878 # DTB write hits -system.cpu0.dtb.write_misses 160428 # DTB write misses +system.cpu0.dtb.read_hits 105404836 # DTB read hits +system.cpu0.dtb.read_misses 420652 # DTB read misses +system.cpu0.dtb.write_hits 86890500 # DTB write hits +system.cpu0.dtb.write_misses 159959 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 34259 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 6211 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 40944 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 605 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8089 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 37781 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 98657093 # DTB read accesses -system.cpu0.dtb.write_accesses 82590306 # DTB write accesses +system.cpu0.dtb.perms_faults 40127 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 105825488 # DTB read accesses +system.cpu0.dtb.write_accesses 87050459 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 180715608 # DTB hits -system.cpu0.dtb.misses 531791 # DTB misses -system.cpu0.dtb.accesses 181247399 # DTB accesses +system.cpu0.dtb.hits 192295336 # DTB hits +system.cpu0.dtb.misses 580611 # DTB misses +system.cpu0.dtb.accesses 192875947 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -471,533 +506,588 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 214588445 # ITB inst hits -system.cpu0.itb.inst_misses 81035 # ITB inst misses +system.cpu0.itb.walker.walks 84622 # Table walker walks requested +system.cpu0.itb.walker.walksLong 84622 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 994 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61729 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 9515 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 75107 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1146.297948 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 8819.384812 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 74551 99.26% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 182 0.24% 99.50% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 223 0.30% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 112 0.15% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 5 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 12 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 75107 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 72238 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 20242.257302 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17307.169845 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18587.015651 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 70635 97.78% 97.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1318 1.82% 99.61% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 148 0.20% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 80 0.11% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 29 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 72238 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 405678068016 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.851697 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.355553 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 60184359568 14.84% 14.84% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 345473805948 85.16% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 18871000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1025500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 405678068016 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 61729 98.42% 98.42% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 994 1.58% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 62723 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84622 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84622 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 62723 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 62723 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 147345 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 229226252 # ITB inst hits +system.cpu0.itb.inst_misses 84622 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24176 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 29308 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 217359 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 225641 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 214669480 # ITB inst accesses -system.cpu0.itb.hits 214588445 # DTB hits -system.cpu0.itb.misses 81035 # DTB misses -system.cpu0.itb.accesses 214669480 # DTB accesses -system.cpu0.numCycles 723605959 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 229310874 # ITB inst accesses +system.cpu0.itb.hits 229226252 # DTB hits +system.cpu0.itb.misses 84622 # DTB misses +system.cpu0.itb.accesses 229310874 # DTB accesses +system.cpu0.numCycles 787784387 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 84128505 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 603958712 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 136692903 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 80843502 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 610845531 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14389096 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1590613 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 145998 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6064926 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 691327 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 308415 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 214371554 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1629958 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 26989 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 710969863 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.995603 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.223531 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 93175923 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 642526185 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 145356452 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 87769259 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 654798115 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15283958 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1702071 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 255624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6308926 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 745987 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 671334 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 229000663 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1782311 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 27660 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 765299959 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.983676 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.220176 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 371943625 52.31% 52.31% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 132005479 18.57% 70.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 45223870 6.36% 77.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 161796889 22.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 404626902 52.87% 52.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 139960190 18.29% 71.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 49291261 6.44% 77.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 171421606 22.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 710969863 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.188905 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.834651 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 100859820 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 341670501 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 226894689 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 36450722 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5094131 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19684552 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2143149 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 625299942 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23465263 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5094131 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 135677386 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 49836875 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 228336608 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 227963533 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 64061330 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 608231586 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 5949574 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 8548374 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 231810 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 263882 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 30185355 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 12581 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 579905224 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 937754781 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 718843517 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 1013139 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 522903039 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 57002179 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15055979 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13152707 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 73956769 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 99026206 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 85770687 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 8763922 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 7686093 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 586686508 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15156086 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 590156830 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2681738 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 50409396 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 34542071 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 266225 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 710969863 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.830073 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.072195 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 765299959 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.184513 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.815612 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 110781464 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 368356745 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 241543971 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 39160465 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5457314 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 20998766 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2230758 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 666506782 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 24554495 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5457314 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 147799214 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 53385858 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 247347968 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 243020975 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 68288630 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 648373688 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6354822 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 9340488 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 358878 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 691420 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 31770877 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 13042 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 618836498 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1000163983 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 765756832 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 980941 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 557557100 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 61279388 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16104693 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13959035 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 79116837 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 106280749 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90455195 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9698755 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8363084 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 625354037 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16149817 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 628774014 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2896491 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 54006760 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 37569824 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 287316 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 765299959 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.821605 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.068919 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 390297771 54.90% 54.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 132320625 18.61% 73.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 115120103 16.19% 89.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 65333726 9.19% 98.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7893369 1.11% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 4269 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 423230722 55.30% 55.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 141522259 18.49% 73.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 122647115 16.03% 89.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 69647275 9.10% 98.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8247243 1.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5342 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 3 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 710969863 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 765299959 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 61459839 45.63% 45.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 50531 0.04% 45.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 24866 0.02% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 22 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 34471783 25.59% 71.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 38693635 28.73% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 65414267 45.68% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 59912 0.04% 45.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 17829 0.01% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 19 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 37349884 26.08% 71.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 40363750 28.19% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 403696370 68.40% 68.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1373917 0.23% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 72713 0.01% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 2 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 82685 0.01% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 101222055 17.15% 85.82% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 83709039 14.18% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 430163495 68.41% 68.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1578221 0.25% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 81407 0.01% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 125 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 78656 0.01% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 108646479 17.28% 85.97% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88225631 14.03% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 590156830 # Type of FU issued -system.cpu0.iq.rate 0.815578 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 134700676 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228246 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2027250728 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 651818194 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 574107974 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1415207 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 570288 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 525567 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 723981962 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 875543 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2649036 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 628774014 # Type of FU issued +system.cpu0.iq.rate 0.798155 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 143205661 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.227754 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2167577171 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 695106277 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 611404783 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1372966 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 554126 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 508083 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 771129089 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 850586 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2930031 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12005066 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 15997 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 137574 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5832630 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13213228 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17078 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 150900 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6091069 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2633268 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 3783846 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2819130 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4221569 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5094131 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6289107 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 4809356 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 601961701 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5457314 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7826815 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 3783393 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 641629807 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 99026206 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 85770687 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 12881584 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 63147 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4682481 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 137574 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 1984191 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2898838 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4883029 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 582493668 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 98279194 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7144205 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 106280749 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90455195 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13677015 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 59030 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3651240 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 150900 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2214888 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3025224 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5240112 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 620548589 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 105398618 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7653008 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119107 # number of nop insts executed -system.cpu0.iew.exec_refs 180711366 # number of memory reference insts executed -system.cpu0.iew.exec_branches 110157991 # Number of branches executed -system.cpu0.iew.exec_stores 82432172 # Number of stores executed -system.cpu0.iew.exec_rate 0.804987 # Inst execution rate -system.cpu0.iew.wb_sent 575359382 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 574633541 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 278757047 # num instructions producing a value -system.cpu0.iew.wb_consumers 457962623 # num instructions consuming a value +system.cpu0.iew.exec_nop 125953 # number of nop insts executed +system.cpu0.iew.exec_refs 192287971 # number of memory reference insts executed +system.cpu0.iew.exec_branches 117275797 # Number of branches executed +system.cpu0.iew.exec_stores 86889353 # Number of stores executed +system.cpu0.iew.exec_rate 0.787714 # Inst execution rate +system.cpu0.iew.wb_sent 612710943 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 611912866 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 297952907 # num instructions producing a value +system.cpu0.iew.wb_consumers 488842231 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.794125 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.608690 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.776752 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609507 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 46943290 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14889861 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4575538 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 702085405 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.780670 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.579297 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 50177444 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15862501 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4903538 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 755787028 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.772749 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.571704 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 463334360 65.99% 65.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 122538358 17.45% 83.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 53278812 7.59% 91.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 18006181 2.56% 93.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13261797 1.89% 95.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8597155 1.22% 96.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5895517 0.84% 97.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3809437 0.54% 98.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 13363788 1.90% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 501065306 66.30% 66.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 130810768 17.31% 83.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 56911365 7.53% 91.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 19253126 2.55% 93.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13929285 1.84% 95.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9339201 1.24% 96.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6281388 0.83% 97.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 4033068 0.53% 98.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14163521 1.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 702085405 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 466411686 # Number of instructions committed -system.cpu0.commit.committedOps 548096953 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 755787028 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 497564314 # Number of instructions committed +system.cpu0.commit.committedOps 584033993 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 166959196 # Number of memory references committed -system.cpu0.commit.loads 87021139 # Number of loads committed -system.cpu0.commit.membars 3711025 # Number of memory barriers committed -system.cpu0.commit.branches 104496556 # Number of branches committed -system.cpu0.commit.fp_insts 513447 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 502627891 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13679873 # Number of function calls committed. +system.cpu0.commit.refs 177431645 # Number of memory references committed +system.cpu0.commit.loads 93067519 # Number of loads committed +system.cpu0.commit.membars 3925399 # Number of memory barriers committed +system.cpu0.commit.branches 111370146 # Number of branches committed +system.cpu0.commit.fp_insts 496516 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 535821487 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14891305 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 379865208 69.31% 69.31% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1141082 0.21% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 57492 0.01% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 73933 0.01% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 87021139 15.88% 85.42% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 79938057 14.58% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 405157799 69.37% 69.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1311833 0.22% 69.60% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 63039 0.01% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 69677 0.01% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 93067519 15.94% 85.55% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 84364126 14.45% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 548096953 # Class of committed instruction -system.cpu0.commit.bw_lim_events 13363788 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 584033993 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14163521 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 1279505618 # The number of ROB reads -system.cpu0.rob.rob_writes 1198929363 # The number of ROB writes -system.cpu0.timesIdled 780048 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 12636096 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 94120949562 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 466411686 # Number of Instructions Simulated -system.cpu0.committedOps 548096953 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.551432 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.551432 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.644566 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.644566 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 688144011 # number of integer regfile reads -system.cpu0.int_regfile_writes 408577767 # number of integer regfile writes -system.cpu0.fp_regfile_reads 842658 # number of floating regfile reads -system.cpu0.fp_regfile_writes 455584 # number of floating regfile writes -system.cpu0.cc_regfile_reads 127446024 # number of cc regfile reads -system.cpu0.cc_regfile_writes 128164594 # number of cc regfile writes -system.cpu0.misc_regfile_reads 2855519856 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15107964 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 5838402 # number of replacements -system.cpu0.dcache.tags.tagsinuse 504.465464 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155155227 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5838912 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.572626 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1750084500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 504.465464 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.985284 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.985284 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 372 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 346167633 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 346167633 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 80535549 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80535549 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69641264 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69641264 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 207056 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 207056 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 203093 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 203093 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877400 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1877400 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1900232 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1900232 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 150176813 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 150176813 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 150383869 # number of overall hits -system.cpu0.dcache.overall_hits::total 150383869 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6642832 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6642832 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7191098 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7191098 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 692118 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 692118 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 798159 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 798159 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 243998 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 243998 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 184133 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 184133 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 13833930 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 13833930 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 14526048 # number of overall misses -system.cpu0.dcache.overall_misses::total 14526048 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 99514286008 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 99514286008 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 115098035706 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 115098035706 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 53560236062 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 53560236062 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3359260407 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3359260407 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3823760481 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3823760481 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2172500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2172500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 214612321714 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 214612321714 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 214612321714 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 214612321714 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87178381 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 87178381 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 76832362 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 76832362 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899174 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 899174 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1001252 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1001252 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2121398 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2121398 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2084365 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2084365 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 164010743 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 164010743 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164909917 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 164909917 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076198 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.076198 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.093595 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.093595 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.769726 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.769726 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.797161 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.797161 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.115018 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.115018 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.088340 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.088340 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084348 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.084348 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088085 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.088085 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14980.701907 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14980.701907 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16005.627472 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 16005.627472 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 67104.719814 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 67104.719814 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13767.573533 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13767.573533 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20766.296541 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20766.296541 # average StoreCondReq miss latency +system.cpu0.rob.rob_reads 1371348086 # The number of ROB reads +system.cpu0.rob.rob_writes 1277898548 # The number of ROB writes +system.cpu0.timesIdled 1050969 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 22484428 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93902986117 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 497564314 # Number of Instructions Simulated +system.cpu0.committedOps 584033993 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.583282 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.583282 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.631600 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.631600 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 732616408 # number of integer regfile reads +system.cpu0.int_regfile_writes 435784003 # number of integer regfile writes +system.cpu0.fp_regfile_reads 812591 # number of floating regfile reads +system.cpu0.fp_regfile_writes 450624 # number of floating regfile writes +system.cpu0.cc_regfile_reads 135724425 # number of cc regfile reads +system.cpu0.cc_regfile_writes 136350840 # number of cc regfile writes +system.cpu0.misc_regfile_reads 3048491910 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15942846 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6332598 # number of replacements +system.cpu0.dcache.tags.tagsinuse 484.098749 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 164710199 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6333110 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.007791 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1750140500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.098749 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.945505 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.945505 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 368140426 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 368140426 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 86285504 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86285504 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73342402 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73342402 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 227851 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 227851 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 264480 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 264480 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878345 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1878345 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1911240 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1911240 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 159627906 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 159627906 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 159855757 # number of overall hits +system.cpu0.dcache.overall_hits::total 159855757 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7088092 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7088092 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7774496 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7774496 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 746133 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 746133 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 842824 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 842824 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 281020 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 281020 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 209055 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 209055 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 14862588 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 14862588 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 15608721 # number of overall misses +system.cpu0.dcache.overall_misses::total 15608721 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 105859717159 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 105859717159 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137077029934 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 137077029934 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 45622327717 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 45622327717 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4025426932 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4025426932 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4395434712 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4395434712 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3232000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3232000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 242936747093 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 242936747093 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 242936747093 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 242936747093 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 93373596 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 93373596 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81116898 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81116898 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 973984 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 973984 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1107304 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1107304 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2159365 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2159365 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2120295 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2120295 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 174490494 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 174490494 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 175464478 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 175464478 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075911 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.075911 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.095843 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.095843 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766063 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766063 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.761150 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.761150 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130140 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130140 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098597 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098597 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085177 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.085177 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088957 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.088957 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14934.867826 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14934.867826 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17631.629103 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17631.629103 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 54130.313941 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 54130.313941 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14324.343221 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14324.343221 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21025.255134 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21025.255134 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15513.474603 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15513.474603 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14774.309001 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14774.309001 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 16118603 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 16176348 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 692801 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 696412 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.265848 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 23.228129 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16345.521190 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16345.521190 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15564.167435 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15564.167435 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 13488103 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 19786702 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 752105 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 757651 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.933803 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 26.115853 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3975125 # number of writebacks -system.cpu0.dcache.writebacks::total 3975125 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3497983 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3497983 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5763188 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 5763188 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4492 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4492 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 123982 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 123982 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9261171 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9261171 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9261171 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9261171 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3144849 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3144849 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1427910 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1427910 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 685927 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 685927 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 793667 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 793667 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120016 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120016 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 184129 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 184129 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4572759 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4572759 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5258686 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5258686 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40981205496 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40981205496 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22755476630 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22755476630 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17996613568 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17996613568 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 51855736982 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 51855736982 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1434297417 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1434297417 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3446370519 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3446370519 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2070500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2070500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 63736682126 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 63736682126 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81733295694 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 81733295694 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5581760391 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5581760391 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5277895398 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5277895398 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10859655789 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10859655789 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036074 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036074 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018585 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018585 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762841 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.762841 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.792675 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.792675 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056574 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056574 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.088338 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.088338 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027881 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027881 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031888 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031888 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13031.215647 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13031.215647 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15936.212107 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15936.212107 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26236.922541 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26236.922541 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 65336.894418 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 65336.894418 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11950.885024 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11950.885024 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18717.152209 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18717.152209 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 4276528 # number of writebacks +system.cpu0.dcache.writebacks::total 4276528 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3664529 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3664529 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6233308 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6233308 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4741 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4741 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 141328 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 141328 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9897837 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9897837 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9897837 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9897837 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3423563 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3423563 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1541188 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1541188 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 739665 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 739665 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 838083 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 838083 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139692 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139692 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 209050 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 209050 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4964751 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4964751 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5704416 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5704416 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44975748199 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44975748199 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28501279892 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28501279892 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16804666332 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16804666332 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 43773018566 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 43773018566 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1737566757 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1737566757 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3967184288 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3967184288 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3082000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3082000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 73477028091 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 73477028091 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 90281694423 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 90281694423 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5575976491 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5575976491 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5325987989 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5325987989 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10901964480 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10901964480 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036665 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036665 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019000 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019000 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759422 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759422 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.756868 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.756868 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064691 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064691 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098595 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098595 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028453 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028453 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032510 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032510 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13137.117149 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13137.117149 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18493.058531 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18493.058531 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22719.293642 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22719.293642 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 52229.932556 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 52229.932556 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12438.555945 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12438.555945 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18977.203004 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18977.203004 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # 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average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1005,463 +1095,461 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6042830 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.967320 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 208050611 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6043342 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.426417 # 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Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999925 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999925 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 434737408 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 434737408 # 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number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 55127710497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 55127710497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 55127710497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 55127710497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 55127710497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 214347024 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 214347024 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 214347024 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 214347024 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 214347024 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 214347024 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029375 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029375 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029375 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029375 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029375 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029375 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8755.415265 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8755.415265 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8755.415265 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8755.415265 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8755.415265 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8755.415265 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4477144 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 62 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 570538 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.847232 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 62 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 464315009 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 464315009 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 222275153 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 222275153 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 222275153 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 222275153 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 222275153 # number of overall hits +system.cpu0.icache.overall_hits::total 222275153 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6697664 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6697664 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6697664 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6697664 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6697664 # number of overall misses +system.cpu0.icache.overall_misses::total 6697664 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 70928372732 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 70928372732 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 70928372732 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 70928372732 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 70928372732 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 70928372732 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 228972817 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 228972817 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 228972817 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 228972817 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 228972817 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 228972817 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029251 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029251 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029251 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029251 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029251 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029251 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10590.016569 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10590.016569 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10590.016569 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10590.016569 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10590.016569 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10590.016569 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8781241 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 821 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 708037 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.402235 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 74.636364 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 253053 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 253053 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 253053 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 253053 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 253053 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 253053 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6043360 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6043360 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6043360 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6043360 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6043360 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6043360 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 44707631164 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 44707631164 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 44707631164 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 44707631164 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 44707631164 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 44707631164 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1699559498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 1699559498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028194 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028194 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028194 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028194 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028194 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028194 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7397.810351 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7397.810351 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7397.810351 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 328289 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 328289 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 328289 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 328289 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 328289 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 328289 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6369375 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6369375 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6369375 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6369375 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6369375 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6369375 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 57966761800 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 57966761800 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 57966761800 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 57966761800 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 57966761800 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 57966761800 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1699560248 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1699560248 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1699560248 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1699560248 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027817 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027817 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027817 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9100.855547 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9100.855547 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9100.855547 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 60184765 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 4393414 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 48808124 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 3087530 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 452633 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3443064 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 5114963 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 4158550 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16214.275256 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 12594287 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 4174696 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.016815 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 9944532000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 3315.303513 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 38.862270 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 22.140550 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 967.067959 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2910.372119 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8960.528846 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.202350 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002372 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001351 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.059025 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.177635 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.546907 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989641 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8340 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7728 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 111 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 951 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3646 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 2631 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1001 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 51 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1103 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3816 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2122 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 566 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.509033 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.471680 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 280330704 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 280330704 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522125 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 166946 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5796903 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2821623 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 9307597 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3975115 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3975115 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 222232 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 222232 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 121282 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 121282 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 38571 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 38571 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 940340 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 940340 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 522125 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 166946 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5796903 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3761963 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10247937 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 522125 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 166946 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5796903 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3761963 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10247937 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13861 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9822 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 246435 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1125045 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1395163 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 7 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 7 # number of Writeback misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 570059 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 570059 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 122791 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 122791 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 145551 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 145551 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 254425 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 254425 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13861 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9822 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 246435 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1379470 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1649588 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13861 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9822 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 246435 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1379470 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1649588 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 480401321 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 335313359 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 6760403458 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 39140642193 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 46716760331 # number of ReadReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 45434423993 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 45434423993 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2483631237 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2483631237 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2949204388 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2949204388 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2019500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2019500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 11373473627 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 11373473627 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 480401321 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 335313359 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 6760403458 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 50514115820 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 58090233958 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 480401321 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 335313359 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 6760403458 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 50514115820 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 58090233958 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 535986 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 176768 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6043338 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3946668 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 10702760 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3975122 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3975122 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 792291 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 792291 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 244073 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 244073 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 184122 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 184122 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1194765 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1194765 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 535986 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 176768 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 6043338 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5141433 # 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miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.719507 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.719507 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.503091 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.503091 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.790514 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.790514 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8232125 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8569505 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 292099 # 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number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 312895441 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15722901634 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 42799610918 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 55041075389 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 114256010592 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1519174250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5322353508 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6841527758 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5082599974 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5082599974 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1519174250 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10404953482 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11924127732 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.258030 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.160084 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.129074 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.129074 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.503091 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.503091 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.790514 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.790514 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762335 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.762335 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.546175 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.546175 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.823890 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.823890 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.185504 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.185504 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256912 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128447 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256912 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.207527 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.207527 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.246303 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.164920 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.246303 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.417806 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27642.980057 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27083.574890 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55593.563487 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32521.484628 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32521.484628 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17427.856472 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17427.856472 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13830.282341 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13830.282341 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 237500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 237500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 33377.085578 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 33377.085578 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28605.109356 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27996.319261 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28605.109356 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47109.300568 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229475 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 28489.841187 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26188.713793 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66837.897451 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 56932.579225 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 56932.579225 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17437.518651 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17437.518651 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13547.478192 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13547.478192 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 496400 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 496400 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41446.125704 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41446.125704 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31024.642284 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28146.040729 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31024.642284 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39030.566104 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1471,69 +1559,77 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 15173335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11005084 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31316 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31316 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3975122 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 5222365 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 963549 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 792291 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 491639 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 333223 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 494297 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1332515 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1202467 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12129286 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16997895 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390025 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1185916 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 30703122 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 387114336 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 641181457 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1414144 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4287888 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1033997825 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 10518238 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 27441081 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.371527 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.483213 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 13921371 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11750633 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31686 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31686 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 4276525 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1274288 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1162561 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 836505 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 509905 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 381643 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 535354 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 87 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1437620 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1309284 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12781022 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18390339 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414542 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1294088 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 32879991 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 407960480 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 693234728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1535584 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4758096 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1107488888 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4767578 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 22911203 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.193957 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.395396 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 17245975 62.85% 62.85% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 10195106 37.15% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 18467409 80.60% 80.60% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 4443794 19.40% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 27441081 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 13452656135 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 22911203 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14408211332 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 192867736 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 208870495 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9099601288 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9596174213 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8421572630 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9165770534 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 213967447 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 223497560 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 651243914 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 700918244 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 133961841 # Number of BP lookups -system.cpu1.branchPred.condPredicted 89061347 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6618163 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 94585757 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 62217505 # Number of BTB hits +system.cpu1.branchPred.lookups 124370032 # Number of BP lookups +system.cpu1.branchPred.condPredicted 83075187 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6189003 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 87824878 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 56905034 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 65.778936 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 18340774 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 186545 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 64.793752 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16687776 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 168367 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1555,27 +1651,98 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 538943 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 538943 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11373 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87574 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 237839 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 301104 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 1852.353340 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 11107.804354 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-32767 297190 98.70% 98.70% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-65535 2030 0.67% 99.37% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-98303 795 0.26% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-131071 637 0.21% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-163839 257 0.09% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::163840-196607 66 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-229375 39 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::229376-262143 29 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-294911 48 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 301104 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 268131 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 15772.437909 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 12981.371112 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15992.673962 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 265367 98.97% 98.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1941 0.72% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 396 0.15% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 232 0.09% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 106 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 37 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 35 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 268131 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 435751861088 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.614829 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.532518 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 434859464588 99.80% 99.80% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 474800000 0.11% 99.90% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 202701000 0.05% 99.95% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 89682000 0.02% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 62866500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 34103000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 13310500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 14713000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 214000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 435751861088 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 87574 88.51% 88.51% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11373 11.49% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 98947 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 538943 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 538943 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98947 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98947 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 637890 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 98830623 # DTB read hits -system.cpu1.dtb.read_misses 443426 # DTB read misses -system.cpu1.dtb.write_hits 80619639 # DTB write hits -system.cpu1.dtb.write_misses 165440 # DTB write misses +system.cpu1.dtb.read_hits 91392867 # DTB read hits +system.cpu1.dtb.read_misses 373745 # DTB read misses +system.cpu1.dtb.write_hits 75805429 # DTB write hits +system.cpu1.dtb.write_misses 165198 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 44150 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 612 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6848 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 37451 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 309 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 5879 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 42554 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 99274049 # DTB read accesses -system.cpu1.dtb.write_accesses 80785079 # DTB write accesses +system.cpu1.dtb.perms_faults 40297 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 91766612 # DTB read accesses +system.cpu1.dtb.write_accesses 75970627 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 179450262 # DTB hits -system.cpu1.dtb.misses 608866 # DTB misses -system.cpu1.dtb.accesses 180059128 # DTB accesses +system.cpu1.dtb.hits 167198296 # DTB hits +system.cpu1.dtb.misses 538943 # DTB misses +system.cpu1.dtb.accesses 167737239 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1597,163 +1764,217 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 211899162 # ITB inst hits -system.cpu1.itb.inst_misses 88988 # ITB inst misses +system.cpu1.itb.walker.walks 85244 # Table walker walks requested +system.cpu1.itb.walker.walksLong 85244 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 675 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61262 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9941 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 75303 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1139.330438 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8399.837182 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 74771 99.29% 99.29% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 180 0.24% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 193 0.26% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 128 0.17% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 12 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 6 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 75303 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 71878 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 20268.763168 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 17115.147893 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 19721.935997 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 70231 97.71% 97.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1324 1.84% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 179 0.25% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 68 0.09% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 46 0.06% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 71878 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 397094361424 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.878531 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.326828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 48253813024 12.15% 12.15% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 348822790900 87.84% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 16535000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1219500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 397094361424 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61262 98.91% 98.91% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 675 1.09% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 61937 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85244 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85244 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61937 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61937 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 147181 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 196146030 # ITB inst hits +system.cpu1.itb.inst_misses 85244 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 32114 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26780 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 230833 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 213163 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 211988150 # ITB inst accesses -system.cpu1.itb.hits 211899162 # DTB hits -system.cpu1.itb.misses 88988 # DTB misses -system.cpu1.itb.accesses 211988150 # DTB accesses -system.cpu1.numCycles 705261968 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 196231274 # ITB inst accesses +system.cpu1.itb.hits 196146030 # DTB hits +system.cpu1.itb.misses 85244 # DTB misses +system.cpu1.itb.accesses 196231274 # DTB accesses +system.cpu1.numCycles 664388878 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 81258744 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 595261780 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 133961841 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 80558279 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 597026773 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 14270848 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1888771 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 137791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6543938 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 793820 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 311963 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 211646234 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1619349 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 28847 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 695097224 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.005850 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.225976 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 79880322 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 552169788 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 124370032 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 73592810 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 551328487 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13340182 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1707326 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 246511 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6080767 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 727313 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 602439 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 195911596 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1586691 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 28723 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 647243256 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.003235 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.226187 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 360486788 51.86% 51.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 129920524 18.69% 70.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 44826389 6.45% 77.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 159863523 23.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 336573756 52.00% 52.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 120960986 18.69% 70.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 40749741 6.30% 76.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 148958773 23.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 695097224 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.189946 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.844029 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 99752260 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 332349824 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 219841712 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 38085588 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5067840 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 18995502 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2109796 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 616514692 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22877728 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5067840 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 135033848 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 48639647 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 225189127 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 222148294 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 59018468 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 599774214 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5804898 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 8803158 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 361913 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 923044 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 23085631 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 14113 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 571116000 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 927515458 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 708750961 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 721490 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 514023695 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 57092304 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 16265387 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 14239236 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 76589893 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 99537313 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 83963206 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 9607701 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 8257946 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 576970515 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 16478044 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 581773999 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2685793 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 50643585 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 34938077 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 295595 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 695097224 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.836968 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.068825 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 647243256 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.187195 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.831094 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 96356177 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 306396299 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 204571849 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 35206357 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4712574 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17589142 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1996203 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 573391383 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21361954 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4712574 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 129172911 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 40460241 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 212107385 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 206565063 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 54225082 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 557977037 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5352379 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8193976 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 222351 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 303036 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 21276416 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 13923 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 530659712 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 862978619 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 659902858 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 766208 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 478267677 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 52392029 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15246817 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13453544 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 71065053 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 91863812 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 78915989 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8629555 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7664780 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 536633802 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15513444 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 541699362 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2485495 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 46695905 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 31776612 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 271399 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 647243256 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.836933 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.069144 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 375720628 54.05% 54.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 136500819 19.64% 73.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 111041420 15.97% 89.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 64151608 9.23% 98.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7678235 1.10% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4508 0.00% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 6 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 349912497 54.06% 54.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 127097301 19.64% 73.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 103346931 15.97% 89.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 59640858 9.21% 98.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7242720 1.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 2949 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 695097224 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 647243256 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 58467261 44.14% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 65736 0.05% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 8975 0.01% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 28 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 36077917 27.24% 71.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 37847209 28.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 54464030 43.99% 43.99% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 55578 0.04% 44.03% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 15828 0.01% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 9 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 33234382 26.84% 70.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 36043585 29.11% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 396486231 68.15% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1392625 0.24% 68.39% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 78812 0.01% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 369233279 68.16% 68.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1193564 0.22% 68.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 69127 0.01% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 2 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 1 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued @@ -1763,367 +1984,367 @@ system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Ty system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 42928 0.01% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 101899765 17.52% 85.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 81873638 14.07% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 46847 0.01% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 94164053 17.38% 85.79% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 76992429 14.21% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 581773999 # Type of FU issued -system.cpu1.iq.rate 0.824905 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 132467126 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.227695 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1992741902 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 643831652 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 565540483 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1056239 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 418449 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 388115 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 713583395 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 657730 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2682619 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 541699362 # Type of FU issued +system.cpu1.iq.rate 0.815335 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 123813412 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.228565 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1855831634 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 598546046 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 526634223 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1109251 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 439129 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 408402 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 664822270 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 690492 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2431611 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 12570649 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16823 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 158978 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5834378 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11396985 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 16347 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 143339 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5491640 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2724944 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3729174 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2526857 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3486247 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5067840 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 8144414 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2028582 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 593577386 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4712574 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5829545 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1427417 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 552265728 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 99537313 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 83963206 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 14010879 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 57965 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1901764 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 158978 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2040667 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2820650 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4861317 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 574179310 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 98827451 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6993764 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 91863812 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 78915989 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13236985 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 56254 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1314129 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 143339 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1858186 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2653609 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4511795 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 534690067 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 91388435 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6481283 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 128827 # number of nop insts executed -system.cpu1.iew.exec_refs 179445358 # number of memory reference insts executed -system.cpu1.iew.exec_branches 107524158 # Number of branches executed -system.cpu1.iew.exec_stores 80617907 # Number of stores executed -system.cpu1.iew.exec_rate 0.814136 # Inst execution rate -system.cpu1.iew.wb_sent 566651750 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 565928598 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 274900610 # num instructions producing a value -system.cpu1.iew.wb_consumers 450009146 # num instructions consuming a value +system.cpu1.iew.exec_nop 118482 # number of nop insts executed +system.cpu1.iew.exec_refs 167194328 # number of memory reference insts executed +system.cpu1.iew.exec_branches 100087893 # Number of branches executed +system.cpu1.iew.exec_stores 75805893 # Number of stores executed +system.cpu1.iew.exec_rate 0.804785 # Inst execution rate +system.cpu1.iew.wb_sent 527704335 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 527042625 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 254576573 # num instructions producing a value +system.cpu1.iew.wb_consumers 416898701 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.802437 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610878 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.793274 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610644 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 47337627 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 16182449 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4550579 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 686146419 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.786229 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.582193 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 43642021 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15242045 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4231486 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 638973832 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.786200 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.579868 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 448874592 65.42% 65.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 124520992 18.15% 83.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 51724584 7.54% 91.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 17115210 2.49% 93.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 12441515 1.81% 95.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8692682 1.27% 96.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5812900 0.85% 97.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3666336 0.53% 98.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 13297608 1.94% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 417556945 65.35% 65.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 116379063 18.21% 83.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 48152991 7.54% 91.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 16068254 2.51% 93.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11811974 1.85% 95.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7886914 1.23% 96.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5403679 0.85% 97.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3345009 0.52% 98.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12369003 1.94% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 686146419 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 458333534 # Number of instructions committed -system.cpu1.commit.committedOps 539467876 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 638973832 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 426124677 # Number of instructions committed +system.cpu1.commit.committedOps 502361434 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 165095491 # Number of memory references committed -system.cpu1.commit.loads 86966664 # Number of loads committed -system.cpu1.commit.membars 3858042 # Number of memory barriers committed -system.cpu1.commit.branches 101991370 # Number of branches committed -system.cpu1.commit.fp_insts 379596 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 495494093 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13607824 # Number of function calls committed. +system.cpu1.commit.refs 153891175 # Number of memory references committed +system.cpu1.commit.loads 80466826 # Number of loads committed +system.cpu1.commit.membars 3635433 # Number of memory barriers committed +system.cpu1.commit.branches 94895008 # Number of branches committed +system.cpu1.commit.fp_insts 399904 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 461321486 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12405087 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 373132612 69.17% 69.17% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1140635 0.21% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 62088 0.01% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 37050 0.01% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 86966664 16.12% 85.52% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 78128827 14.48% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 347396188 69.15% 69.15% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 977319 0.19% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 55389 0.01% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 41321 0.01% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 80466826 16.02% 85.38% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 73424349 14.62% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 539467876 # Class of committed instruction -system.cpu1.commit.bw_lim_events 13297608 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 502361434 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12369003 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 1255653176 # The number of ROB reads -system.cpu1.rob.rob_writes 1182522736 # The number of ROB writes -system.cpu1.timesIdled 784634 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 10164744 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94139293558 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 458333534 # Number of Instructions Simulated -system.cpu1.committedOps 539467876 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.538753 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.538753 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.649877 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.649877 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 678371688 # number of integer regfile reads -system.cpu1.int_regfile_writes 402814905 # number of integer regfile writes -system.cpu1.fp_regfile_reads 627803 # number of floating regfile reads -system.cpu1.fp_regfile_writes 323588 # number of floating regfile writes -system.cpu1.cc_regfile_reads 123299886 # number of cc regfile reads -system.cpu1.cc_regfile_writes 123979632 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2817640596 # number of misc regfile reads -system.cpu1.misc_regfile_writes 16155257 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5719154 # number of replacements -system.cpu1.dcache.tags.tagsinuse 428.720007 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 153241322 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5719665 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 26.792010 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8515430590500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 428.720007 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.837344 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.837344 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 342874086 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 342874086 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 80584085 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 80584085 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 68058878 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 68058878 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187635 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 187635 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 112453 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 112453 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1764554 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1764554 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1816897 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1816897 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 148642963 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 148642963 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 148830598 # number of overall hits -system.cpu1.dcache.overall_hits::total 148830598 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6869643 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6869643 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7494314 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7494314 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 706318 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 706318 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 458418 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 458418 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 288948 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 288948 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 190861 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 190861 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 14363957 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 14363957 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 15070275 # number of overall misses -system.cpu1.dcache.overall_misses::total 15070275 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 105402463849 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 105402463849 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 121649241613 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 121649241613 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 17403154350 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 17403154350 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4078869410 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 4078869410 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3937390159 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3937390159 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1956500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1956500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 227051705462 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 227051705462 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 227051705462 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 227051705462 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 87453728 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 87453728 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 75553192 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 75553192 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 893953 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 893953 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 570871 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 570871 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2053502 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2053502 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2007758 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2007758 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 163006920 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 163006920 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 163900873 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 163900873 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078552 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.078552 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.099193 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.099193 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790106 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790106 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.803015 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.803015 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140710 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140710 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095062 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095062 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088119 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.088119 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.091947 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.091947 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15343.222908 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15343.222908 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16232.205057 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16232.205057 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 37963.505687 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 37963.505687 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14116.274935 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14116.274935 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20629.621342 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20629.621342 # average StoreCondReq miss latency +system.cpu1.rob.rob_reads 1168820475 # The number of ROB reads +system.cpu1.rob.rob_writes 1100237743 # The number of ROB writes +system.cpu1.timesIdled 913492 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 17145622 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94026381638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 426124677 # Number of Instructions Simulated +system.cpu1.committedOps 502361434 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.559142 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.559142 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.641378 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.641378 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 632226075 # number of integer regfile reads +system.cpu1.int_regfile_writes 374528717 # number of integer regfile writes +system.cpu1.fp_regfile_reads 661926 # number of floating regfile reads +system.cpu1.fp_regfile_writes 331836 # number of floating regfile writes +system.cpu1.cc_regfile_reads 114587184 # number of cc regfile reads +system.cpu1.cc_regfile_writes 115385602 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2619636946 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15333141 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5236220 # number of replacements +system.cpu1.dcache.tags.tagsinuse 457.332610 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 143091306 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5236730 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.324553 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8478701081000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.332610 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893228 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.893228 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 319394188 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 319394188 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 74655263 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 74655263 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 64023189 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 64023189 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 163779 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 163779 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 39797 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 39797 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1738928 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1738928 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1751406 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1751406 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 138678452 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 138678452 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 138842231 # number of overall hits +system.cpu1.dcache.overall_hits::total 138842231 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6126939 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6126939 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6982821 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6982821 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 659533 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 659533 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 425377 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 425377 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 260578 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 260578 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 204152 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 204152 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13109760 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13109760 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13769293 # number of overall misses +system.cpu1.dcache.overall_misses::total 13769293 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92549514245 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 92549514245 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 116311286360 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 116311286360 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11708163921 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11708163921 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3758503444 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3758503444 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4320848660 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4320848660 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3489000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3489000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 208860800605 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 208860800605 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 208860800605 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 208860800605 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 80782202 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 80782202 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 71006010 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 71006010 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 823312 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 823312 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 465174 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 465174 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1999506 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1999506 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1955558 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1955558 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 151788212 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 151788212 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 152611524 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 152611524 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075845 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.075845 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098341 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.098341 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.801073 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.801073 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.914447 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.914447 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130321 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130321 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104396 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104396 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086369 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.086369 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090224 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.090224 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15105.342855 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15105.342855 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16656.776160 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16656.776160 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27524.205401 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27524.205401 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14423.717444 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14423.717444 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21164.860790 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21164.860790 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15807.044358 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15807.044358 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15066.195239 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15066.195239 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 4622048 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18188306 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 368036 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 754235 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.558684 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 24.114906 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15931.702839 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15931.702839 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15168.592941 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15168.592941 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 2855420 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 17544431 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 337066 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 700468 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.471397 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 25.046727 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3658567 # number of writebacks -system.cpu1.dcache.writebacks::total 3658567 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3579229 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3579229 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6058526 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 6058526 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3270 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3270 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 146042 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 146042 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 9637755 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 9637755 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 9637755 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 9637755 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3290414 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3290414 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1435788 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1435788 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 706224 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 706224 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 455148 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 455148 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 142906 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 142906 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 190858 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 190858 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4726202 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4726202 # 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number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1722097666 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1722097666 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3546227841 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3546227841 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1864500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1864500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68181902853 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 68181902853 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84541015329 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 84541015329 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 790979694 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 790979694 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 944680456 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 944680456 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1735660150 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1735660150 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037625 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037625 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019004 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019004 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790001 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790001 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.797287 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.797287 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069591 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069591 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095060 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095060 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028994 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028994 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033145 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033145 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13615.312541 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13615.312541 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16285.055910 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16285.055910 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23164.197869 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23164.197869 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 36064.190674 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 36064.190674 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12050.562370 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12050.562370 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18580.451650 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18580.451650 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3392584 # number of writebacks +system.cpu1.dcache.writebacks::total 3392584 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3127909 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3127909 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5647115 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5647115 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3296 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3296 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 132105 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 132105 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8775024 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8775024 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8775024 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8775024 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2999030 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2999030 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1335706 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1335706 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 659449 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 659449 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 422081 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 422081 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 128473 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 128473 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 204145 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 204145 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4334736 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4334736 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4994185 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4994185 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38225367292 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38225367292 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21845579142 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21845579142 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15240654080 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15240654080 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10753431338 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10753431338 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1629520255 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1629520255 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3904363340 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3904363340 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3325000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3325000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60070946434 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 60070946434 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75311600514 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 75311600514 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 796916503 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 796916503 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 897774501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 897774501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1694691004 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1694691004 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037125 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037125 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018811 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018811 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.800971 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.800971 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.907362 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.907362 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064252 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064252 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104392 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104392 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028558 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028558 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032725 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032725 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12745.910275 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12745.910275 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16355.080491 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16355.080491 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23111.194467 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23111.194467 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25477.174613 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25477.174613 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12683.756548 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12683.756548 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19125.441916 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19125.441916 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # 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number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 50254087338 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50254087338 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 50254087338 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50254087338 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 50254087338 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5802498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5802498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5802498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5802498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028192 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.028192 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.028192 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9099.148450 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9099.148450 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9099.148450 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 56932742 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2823095 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 47812216 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2677811 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 382726 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 3236886 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4916498 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 4092617 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13780.930785 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 12621619 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 4108487 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 3.072084 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9637211064000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 3757.362843 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.809020 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 56.863279 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 599.057552 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3491.075179 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5813.762913 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.229331 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003834 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003471 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036564 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.213078 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.354844 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.841121 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8933 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6853 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 68 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 777 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3625 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2921 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1542 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 64 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3137 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2007 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 750 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.545227 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005127 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.418274 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 271640392 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 271640392 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 596119 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 184681 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5616426 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2971260 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 9368486 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3658557 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3658557 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 182266 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 182266 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 95807 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 95807 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 41710 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 41710 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 960995 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 960995 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 596119 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 184681 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5616426 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3932255 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 10329481 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 596119 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 184681 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5616426 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3932255 # number of overall hits -system.cpu1.l2cache.overall_hits::total 10329481 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 16104 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 12169 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 265788 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 1166045 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1460106 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 9 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 9 # number of Writeback misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 271820 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 271820 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 129531 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 129531 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 149141 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 149141 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 255657 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 255657 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 16104 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 12169 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 265788 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1421702 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1715763 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 16104 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 12169 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 265788 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1421702 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1715763 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 666484538 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 571688851 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 6944017926 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 40559833009 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 48742024324 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 11677447356 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 11677447356 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2603211060 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2603211060 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3027794367 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3027794367 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1818500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1818500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11891425269 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 11891425269 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 666484538 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 571688851 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 6944017926 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 52451258278 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 60633449593 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 666484538 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 571688851 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 6944017926 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 52451258278 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 60633449593 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 612223 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 196850 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5882214 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4137305 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 10828592 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3658566 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3658566 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 454086 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 454086 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 225338 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 225338 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 190851 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 190851 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1216652 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1216652 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 612223 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 196850 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5882214 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5353957 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 12045244 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 612223 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 196850 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5882214 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5353957 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 12045244 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026304 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.061819 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.045185 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.281837 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.134838 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.598609 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.598609 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.574830 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.574830 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.781453 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.781453 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7021877 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7194867 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 149461 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 884477 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2159012 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13531.891931 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 11463233 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2175036 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.270365 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9606894527000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5515.011217 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.352016 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.650961 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3854.550779 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3125.340880 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 867.986079 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.336610 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004965 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005350 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.235263 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.190756 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.052978 # 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mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000005 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.198134 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.198134 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.574830 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.574830 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.781453 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.781453 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.544047 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.544047 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.669881 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.669881 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.845860 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.845860 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.180399 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.180399 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.257106 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132931 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.257106 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.211837 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.211837 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.251276 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.166458 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.251276 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.401623 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27705.527306 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27112.291240 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36830.440224 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31073.249872 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31073.249872 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17075.365387 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17075.365387 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13826.798875 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13826.798875 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213785.714286 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213785.714286 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33235.203246 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33235.203246 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28587.212018 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27951.592092 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28587.212018 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33891.685533 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.229614 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27088.613218 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25479.272145 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55953.826735 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30220.826364 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30220.826364 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17019.129327 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17019.129327 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13344.779958 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13344.779958 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 205307.692308 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 205307.692308 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31462.643936 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31462.643936 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27934.849621 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26247.125426 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27934.849621 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34417.992621 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2598,66 +2816,66 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 15325840 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 11081361 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 7210 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7210 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3658566 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 4807205 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 18 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 637593 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 454086 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 471082 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 336358 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 477965 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1352070 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1222067 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11764566 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16293479 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 431287 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1341589 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 29830921 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 376462768 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 612089908 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1574800 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4897784 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 995025260 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 10166385 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 26584709 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.370632 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.482974 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 12802922 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10291743 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3392582 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1076196 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 13 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1156933 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 420701 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 464615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 376292 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 486818 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1296360 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1132878 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11046012 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15089863 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 415115 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1210522 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27761512 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353468736 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 564735319 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1532736 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4394080 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 924130871 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5316111 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 20559073 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.243524 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.429209 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 16731578 62.94% 62.94% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 9853131 37.06% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 15552442 75.65% 75.65% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 5006631 24.35% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 26584709 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 12493291014 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 20559073 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 11602796673 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 175961487 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 182870488 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8832336643 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8299279905 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8528127192 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7848510644 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 235484276 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 224378946 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 730977975 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 662954125 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40396 # Transaction distribution -system.iobus.trans_dist::ReadResp 40396 # Transaction distribution -system.iobus.trans_dist::WriteReq 136775 # Transaction distribution -system.iobus.trans_dist::WriteResp 30047 # Transaction distribution +system.iobus.trans_dist::ReadReq 40399 # Transaction distribution +system.iobus.trans_dist::ReadResp 40399 # Transaction distribution +system.iobus.trans_dist::WriteReq 136785 # Transaction distribution +system.iobus.trans_dist::WriteResp 30057 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2672,13 +2890,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354342 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48148 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354368 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48174 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2693,13 +2911,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156169 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156195 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497071 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36581000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7497097 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36604000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2727,27 +2945,27 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1043032876 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1043087367 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93018000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93034000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179190812 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179187461 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115581 # number of replacements -system.iocache.tags.tagsinuse 11.295325 # Cycle average of tags in use +system.iocache.tags.replacements 115604 # number of replacements +system.iocache.tags.tagsinuse 11.301402 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115597 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115620 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9153631711000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.835501 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.459825 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239719 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466239 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705958 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9117040369000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.419209 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.882193 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463701 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.242637 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706338 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2767,18 +2985,18 @@ system.iocache.overall_misses::realview.ethernet 40 system.iocache.overall_misses::realview.ide 8872 # number of overall misses system.iocache.overall_misses::total 8912 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1960529318 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1966236318 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 365000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 365000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28841569746 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28841569746 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6072000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1960529318 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1966601318 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6072000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1960529318 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1966601318 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1954318592 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1960025592 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28939092314 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28939092314 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1954318592 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1960382592 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1954318592 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1960382592 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses) @@ -2806,28 +3024,28 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 220979.409152 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 220702.246941 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 121666.666667 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 121666.666667 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270234.331628 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270234.331628 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151800 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 220979.409152 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220668.909111 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151800 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 220979.409152 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220668.909111 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 224453 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 220279.372408 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 220005.117522 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271148.080298 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 271148.080298 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 220279.372408 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 219971.116697 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 220279.372408 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 219971.116697 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 228427 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27297 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27535 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.222625 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.295878 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106702 # number of writebacks +system.iocache.writebacks::total 106702 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::realview.ide 8872 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 8909 # number of ReadReq MSHR misses @@ -2842,18 +3060,18 @@ system.iocache.overall_mshr_misses::realview.ethernet 40 system.iocache.overall_mshr_misses::realview.ide 8872 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8912 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1499010380 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1502793380 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 209000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 209000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23291152308 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23291152308 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3992000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1499010380 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1503002380 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3992000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1499010380 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1503002380 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1492830122 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1496613122 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23388843706 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23388843706 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1492830122 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1496814122 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1492830122 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1496814122 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2868,569 +3086,561 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168959.691163 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 168682.610843 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 69666.666667 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 69666.666667 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.071172 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.071172 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99800 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 168959.691163 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168649.279623 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99800 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 168959.691163 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168649.279623 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168263.088593 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 167988.901336 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219144.401713 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219144.401713 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 168263.088593 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 167954.905969 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 168263.088593 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 167954.905969 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1916125 # number of replacements -system.l2c.tags.tagsinuse 64884.880884 # Cycle average of tags in use -system.l2c.tags.total_refs 8755676 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1978999 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.424295 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 3437261500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 8337.656958 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 17.346754 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 14.129416 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 627.039592 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3445.654069 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15412.309931 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 351.392171 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 435.207962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 621.389971 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11403.863316 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 24218.890744 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.127223 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000265 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000216 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.009568 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.052577 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.235173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005362 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006641 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.009482 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.174009 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.369551 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.990065 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 38428 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 201 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 24245 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 143 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 2926 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6291 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29058 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 187 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1447 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2670 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 19923 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.586365 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003067 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.369949 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 93004482 # Number of tag accesses -system.l2c.tags.data_accesses 93004482 # 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average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 95234.409236 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 88505.270864 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 142986.908047 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 147184.723697 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 89319 # number of cycles access was blocked +system.l2c.tags.replacements 1613331 # number of replacements +system.l2c.tags.tagsinuse 64339.343113 # Cycle average of tags in use +system.l2c.tags.total_refs 4797018 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1673818 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.865914 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 3243842500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 19101.398352 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3090 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3968 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 42149 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.163010 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003738 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.756210 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 64781750 # Number of tag accesses +system.l2c.tags.data_accesses 64781750 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6508 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4319 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 640995 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 651108 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 307248 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 112198.907686 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48918.341561 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27337.914593 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 45381.957713 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10183.407896 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10261.080288 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10221.673772 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10188.880770 # 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average ReadReq mshr uncacheable latency @@ -3445,57 +3655,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1817706 # Transaction distribution -system.membus.trans_dist::ReadResp 1817706 # Transaction distribution -system.membus.trans_dist::WriteReq 38526 # Transaction distribution -system.membus.trans_dist::WriteResp 38526 # Transaction distribution -system.membus.trans_dist::Writeback 1444194 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 154200 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 154200 # Transaction distribution -system.membus.trans_dist::UpgradeReq 434662 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 279066 # Transaction distribution -system.membus.trans_dist::UpgradeResp 97607 # Transaction distribution -system.membus.trans_dist::ReadExReq 117028 # Transaction distribution -system.membus.trans_dist::ReadExResp 102726 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123062 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1032278 # Transaction distribution +system.membus.trans_dist::ReadResp 1032278 # Transaction distribution +system.membus.trans_dist::WriteReq 38581 # Transaction distribution +system.membus.trans_dist::WriteResp 38581 # Transaction distribution +system.membus.trans_dist::Writeback 1347712 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 689975 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 689975 # Transaction distribution +system.membus.trans_dist::UpgradeReq 447979 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 332386 # Transaction distribution +system.membus.trans_dist::UpgradeResp 121150 # Transaction distribution +system.membus.trans_dist::ReadExReq 152231 # Transaction distribution +system.membus.trans_dist::ReadExResp 135895 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123088 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25796 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6008493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6157429 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336112 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336112 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6493541 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156169 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25972 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5571157 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5720295 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6056198 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156195 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 207457224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 207665557 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14110208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14110208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 221775765 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 633029 # Total snoops (count) -system.membus.snoop_fanout::samples 4186947 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 187423448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 187632159 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14096832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 201728991 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 678374 # Total snoops (count) +system.membus.snoop_fanout::samples 3943213 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4186947 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3943213 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4186947 # Request fanout histogram -system.membus.reqLayer0.occupancy 98514469 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3943213 # Request fanout histogram +system.membus.reqLayer0.occupancy 98700492 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21244987 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21600991 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 16738053981 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 19952700228 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 17312327015 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 11115498245 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187280188 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 187180539 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3539,49 +3749,49 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 8653355 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 8646086 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38526 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38526 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3063024 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 248029 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 141301 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 493306 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 294608 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 787914 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 273153 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 273153 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10956928 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10351144 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 21308072 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 369780529 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 344544100 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 714324629 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1644746 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 12968411 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.008917 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.094008 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4932840 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4925609 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38581 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38581 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2564009 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 955023 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 848293 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 504313 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 344758 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 849071 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 157 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 306644 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 306644 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8600677 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6275419 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 14876096 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 289885704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198430935 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 488316639 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1740265 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9550575 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012108 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.109370 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 12852771 99.11% 99.11% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115640 0.89% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9434933 98.79% 98.79% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115642 1.21% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 12968411 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 19352517195 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9550575 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 18722164156 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7381500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 7552500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20456793572 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 13115425494 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 20083133002 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 11201753623 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13518 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 13602 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5604 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5345 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |