diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt | 6744 |
1 files changed, 3369 insertions, 3375 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index df40a85e7..7c01d248f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.384351 # Number of seconds simulated -sim_ticks 47384351300000 # Number of ticks simulated -final_tick 47384351300000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.383918 # Number of seconds simulated +sim_ticks 47383917710000 # Number of ticks simulated +final_tick 47383917710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183431 # Simulator instruction rate (inst/s) -host_op_rate 207694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7126665146 # Simulator tick rate (ticks/s) -host_mem_usage 777076 # Number of bytes of host memory used -host_seconds 6648.88 # Real time elapsed on the host -sim_insts 1219610005 # Number of instructions simulated -sim_ops 1380933056 # Number of ops (including micro ops) simulated +host_inst_rate 126839 # Simulator instruction rate (inst/s) +host_op_rate 149150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6559041658 # Simulator tick rate (ticks/s) +host_mem_usage 782584 # Number of bytes of host memory used +host_seconds 7224.21 # Real time elapsed on the host +sim_insts 916315151 # Number of instructions simulated +sim_ops 1077489368 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 205248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 202880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4270112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 16788488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 21729728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 123968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 83584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3109600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10061712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12393536 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 438400 # Number of bytes read from this memory -system.physmem.bytes_read::total 69407256 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4270112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3109600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7379712 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 85545984 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 217728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 211200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4242016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 16335944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 21100544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 95616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 61568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3171760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9979472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12170752 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 426688 # Number of bytes read from this memory +system.physmem.bytes_read::total 68013288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4242016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3171760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7413776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 84160640 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 85566568 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3207 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 82673 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 262333 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 339527 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1937 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1306 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 48631 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 157227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 193649 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6850 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1100510 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1336656 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 84181224 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3402 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3300 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 82234 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 255262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 329696 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1494 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 49603 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 155942 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 190168 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6667 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1078730 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1315010 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1339230 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 4282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 90117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 354304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 458584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 65625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 212343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 261553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1464772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 90117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 65625 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155742 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1805364 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1317584 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4595 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 89524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 344757 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 445310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 66937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 210609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 256854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1435366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 89524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 66937 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 156462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1776144 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1805798 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1805364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 4282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 90117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 354739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 458584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2616 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 65625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 212343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 261553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3270570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1100510 # Number of read requests accepted -system.physmem.writeReqs 1339230 # Number of write requests accepted -system.physmem.readBursts 1100510 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1339230 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 70408640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue -system.physmem.bytesWritten 85564992 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 69407256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 85566568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1776578 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1776144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 89524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 345191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 445310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 66937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 210609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 256854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3211944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1078730 # Number of read requests accepted +system.physmem.writeReqs 1317584 # Number of write requests accepted +system.physmem.readBursts 1078730 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1317584 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 69010688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 28032 # Total number of bytes read from write queue +system.physmem.bytesWritten 84179968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 68013288 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 84181224 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 438 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 70416 # Per bank write bursts -system.physmem.perBankRdBursts::1 75191 # Per bank write bursts -system.physmem.perBankRdBursts::2 64063 # Per bank write bursts -system.physmem.perBankRdBursts::3 69912 # Per bank write bursts -system.physmem.perBankRdBursts::4 59812 # Per bank write bursts -system.physmem.perBankRdBursts::5 69643 # Per bank write bursts -system.physmem.perBankRdBursts::6 65430 # Per bank write bursts -system.physmem.perBankRdBursts::7 68144 # Per bank write bursts -system.physmem.perBankRdBursts::8 61950 # Per bank write bursts -system.physmem.perBankRdBursts::9 89644 # Per bank write bursts -system.physmem.perBankRdBursts::10 68037 # Per bank write bursts -system.physmem.perBankRdBursts::11 70586 # Per bank write bursts -system.physmem.perBankRdBursts::12 61163 # Per bank write bursts -system.physmem.perBankRdBursts::13 71056 # Per bank write bursts -system.physmem.perBankRdBursts::14 65094 # Per bank write bursts -system.physmem.perBankRdBursts::15 69994 # Per bank write bursts -system.physmem.perBankWrBursts::0 85481 # Per bank write bursts -system.physmem.perBankWrBursts::1 90029 # Per bank write bursts -system.physmem.perBankWrBursts::2 81966 # Per bank write bursts -system.physmem.perBankWrBursts::3 85433 # Per bank write bursts -system.physmem.perBankWrBursts::4 77921 # Per bank write bursts -system.physmem.perBankWrBursts::5 84076 # Per bank write bursts -system.physmem.perBankWrBursts::6 83054 # Per bank write bursts -system.physmem.perBankWrBursts::7 85039 # Per bank write bursts -system.physmem.perBankWrBursts::8 78873 # Per bank write bursts -system.physmem.perBankWrBursts::9 84297 # Per bank write bursts -system.physmem.perBankWrBursts::10 83224 # Per bank write bursts -system.physmem.perBankWrBursts::11 86586 # Per bank write bursts -system.physmem.perBankWrBursts::12 79852 # Per bank write bursts -system.physmem.perBankWrBursts::13 85124 # Per bank write bursts -system.physmem.perBankWrBursts::14 80745 # Per bank write bursts -system.physmem.perBankWrBursts::15 85253 # Per bank write bursts +system.physmem.perBankRdBursts::0 67696 # Per bank write bursts +system.physmem.perBankRdBursts::1 73149 # Per bank write bursts +system.physmem.perBankRdBursts::2 67549 # Per bank write bursts +system.physmem.perBankRdBursts::3 71981 # Per bank write bursts +system.physmem.perBankRdBursts::4 66956 # Per bank write bursts +system.physmem.perBankRdBursts::5 73789 # Per bank write bursts +system.physmem.perBankRdBursts::6 64889 # Per bank write bursts +system.physmem.perBankRdBursts::7 66635 # Per bank write bursts +system.physmem.perBankRdBursts::8 57075 # Per bank write bursts +system.physmem.perBankRdBursts::9 82656 # Per bank write bursts +system.physmem.perBankRdBursts::10 58467 # Per bank write bursts +system.physmem.perBankRdBursts::11 69413 # Per bank write bursts +system.physmem.perBankRdBursts::12 60741 # Per bank write bursts +system.physmem.perBankRdBursts::13 63810 # Per bank write bursts +system.physmem.perBankRdBursts::14 67156 # Per bank write bursts +system.physmem.perBankRdBursts::15 66330 # Per bank write bursts +system.physmem.perBankWrBursts::0 82175 # Per bank write bursts +system.physmem.perBankWrBursts::1 87404 # Per bank write bursts +system.physmem.perBankWrBursts::2 82364 # Per bank write bursts +system.physmem.perBankWrBursts::3 86039 # Per bank write bursts +system.physmem.perBankWrBursts::4 82832 # Per bank write bursts +system.physmem.perBankWrBursts::5 88693 # Per bank write bursts +system.physmem.perBankWrBursts::6 80795 # Per bank write bursts +system.physmem.perBankWrBursts::7 83065 # Per bank write bursts +system.physmem.perBankWrBursts::8 76149 # Per bank write bursts +system.physmem.perBankWrBursts::9 79916 # Per bank write bursts +system.physmem.perBankWrBursts::10 77037 # Per bank write bursts +system.physmem.perBankWrBursts::11 82986 # Per bank write bursts +system.physmem.perBankWrBursts::12 77147 # Per bank write bursts +system.physmem.perBankWrBursts::13 80171 # Per bank write bursts +system.physmem.perBankWrBursts::14 84038 # Per bank write bursts +system.physmem.perBankWrBursts::15 84501 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 51215 # Number of times write queue was full causing retry -system.physmem.totGap 47384349786500 # Total gap between requests +system.physmem.numWrRetry 50212 # Number of times write queue was full causing retry +system.physmem.totGap 47383916196500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) -system.physmem.readPktSize::4 21333 # Read request sizes (log2) +system.physmem.readPktSize::4 21334 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1079152 # Read request sizes (log2) +system.physmem.readPktSize::6 1057371 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1336656 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 480448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 272774 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 88894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 67384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 42690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 36411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 7595 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 590 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1315010 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 477824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 264556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 85571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 63109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 41587 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 35911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2354 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -189,136 +189,136 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 38198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 43791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 48248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 52275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 57744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 67593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 69901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 75312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 79272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 77429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 80341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 90816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 80863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 73646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 69003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 6200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 120342 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1069816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 145.794462 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.799028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 192.755385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 712470 66.60% 66.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 211048 19.73% 86.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55044 5.15% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23596 2.21% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18557 1.73% 95.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10547 0.99% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7452 0.70% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5550 0.52% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25552 2.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1069816 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 62458 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.613853 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 71.325725 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 62454 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 22527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 36837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 42274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 46464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 50322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 56496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 66561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 68608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 74012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 78194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 76215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 79218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 90231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 80845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 75138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 70175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 2035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 2934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 118579 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1002120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 152.866515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.517170 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.697434 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 641919 64.06% 64.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 209293 20.89% 84.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 56817 5.67% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24891 2.48% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19538 1.95% 95.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11144 1.11% 96.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7510 0.75% 96.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6154 0.61% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24854 2.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1002120 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61846 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.434870 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 71.484606 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 61843 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 62458 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 62458 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.405633 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.660061 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 609.107080 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-4095 62456 100.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45056-49151 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61846 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61846 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.267535 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.561626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 606.950117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-4095 61844 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40960-45055 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 62458 # Writes before turning the bus around for reads -system.physmem.totQLat 48895390505 # Total ticks spent queuing -system.physmem.totMemAccLat 69522921755 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5500675000 # Total ticks spent in databus transfers -system.physmem.avgQLat 44444.90 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 61846 # Writes before turning the bus around for reads +system.physmem.totQLat 51075620081 # Total ticks spent queuing +system.physmem.totMemAccLat 71293595081 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5391460000 # Total ticks spent in databus transfers +system.physmem.avgQLat 47367.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 63194.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.46 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 66117.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.21 # Average write queue length when enqueuing -system.physmem.readRowHits 830166 # Number of row buffer hits during reads -system.physmem.writeRowHits 537104 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.17 # Row buffer hit rate for writes -system.physmem.avgGap 19421885.03 # Average gap between requests -system.physmem.pageHitRate 56.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4087639080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2230358625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4232326800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4361033520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3094915112640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1166279241240 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27407555547000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31683661258905 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.652499 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45594888254330 # Time in different power states -system.physmem_0.memoryStateTime::REF 1582267440000 # Time in different power states +system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.55 # Average write queue length when enqueuing +system.physmem.readRowHits 810741 # Number of row buffer hits during reads +system.physmem.writeRowHits 580742 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 44.15 # Row buffer hit rate for writes +system.physmem.avgGap 19773667.47 # Average gap between requests +system.physmem.pageHitRate 58.13 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3929423400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2144030625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4310615400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4363418160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3094887141840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1164748800645 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27408641092500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31683024522570 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.645104 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45596671664426 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582253140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 207195159170 # Time in different power states +system.physmem_0.memoryStateTime::ACT 204992820574 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4000169880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2182632375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4348679400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4302421920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3094915112640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1168435080135 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27405664460250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31683848556600 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.656452 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45591701065782 # Time in different power states -system.physmem_1.memoryStateTime::REF 1582267440000 # Time in different power states +system.physmem_1.actEnergy 3646603800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1989714375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4100054400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4159803600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3094887141840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1159320938310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27413402375250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31681506631575 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.613070 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45604605403923 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582253140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 210382633218 # Time in different power states +system.physmem_1.memoryStateTime::ACT 197059081077 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -345,30 +345,30 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 199183431 # Number of BP lookups -system.cpu0.branchPred.condPredicted 140489040 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7036065 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 156342542 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 99990575 # Number of BTB hits +system.cpu0.branchPred.lookups 139955722 # Number of BP lookups +system.cpu0.branchPred.condPredicted 92576910 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6767718 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 98409045 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 61922323 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 63.956089 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 20013017 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 198399 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4618183 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2919648 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1698535 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 412858 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 62.923406 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 19026711 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 185987 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4326684 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2749366 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1577318 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 397214 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -398,86 +398,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 607513 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 607513 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13877 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 97395 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 289192 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 318321 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2219.643065 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 12711.673990 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 315923 99.25% 99.25% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1786 0.56% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 409 0.13% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 127 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 41 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 31 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 318321 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 324666 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 20482.457356 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17703.017560 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16938.599592 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 320665 98.77% 98.77% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2783 0.86% 99.62% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 369 0.11% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 625 0.19% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 139 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 57 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 611788 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 611788 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13108 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 98298 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 292807 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 318981 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2428.828049 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 13543.109769 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 316274 99.15% 99.15% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 2036 0.64% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 442 0.14% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 53 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 29 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 318981 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 326187 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22022.583671 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18838.451550 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 17664.426007 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 321608 98.60% 98.60% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3320 1.02% 99.61% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 429 0.13% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 611 0.19% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 146 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 45 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 324666 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 513372677252 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.571567 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.552695 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 512028975252 99.74% 99.74% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 726675000 0.14% 99.88% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 290458500 0.06% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 129299000 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 102361000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 55725500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 16517000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 21785000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 858500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 22500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 513372677252 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 97395 87.53% 87.53% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 13877 12.47% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 111272 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 607513 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 326187 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 530119453936 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.586335 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.554664 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 528635854936 99.72% 99.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 807711000 0.15% 99.87% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 321496500 0.06% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 138249500 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 109943500 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 58618500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 20610000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 26013000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 940000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 17000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 530119453936 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 98298 88.23% 88.23% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 13108 11.77% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 111406 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 611788 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 607513 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111272 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 611788 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111406 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111272 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 718785 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111406 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 723194 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 141538315 # DTB read hits -system.cpu0.dtb.read_misses 437252 # DTB read misses -system.cpu0.dtb.write_hits 86796370 # DTB write hits -system.cpu0.dtb.write_misses 170261 # DTB write misses +system.cpu0.dtb.read_hits 102674478 # DTB read hits +system.cpu0.dtb.read_misses 445170 # DTB read misses +system.cpu0.dtb.write_hits 82832935 # DTB write hits +system.cpu0.dtb.write_misses 166618 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 43183 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 271 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 6902 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 42795 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 479 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7037 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 42288 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 141975567 # DTB read accesses -system.cpu0.dtb.write_accesses 86966631 # DTB write accesses +system.cpu0.dtb.perms_faults 40072 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 103119648 # DTB read accesses +system.cpu0.dtb.write_accesses 82999553 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 228334685 # DTB hits -system.cpu0.dtb.misses 607513 # DTB misses -system.cpu0.dtb.accesses 228942198 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 185507413 # DTB hits +system.cpu0.dtb.misses 611788 # DTB misses +system.cpu0.dtb.accesses 186119201 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,1194 +507,1182 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 87943 # Table walker walks requested -system.cpu0.itb.walker.walksLong 87943 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1130 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 62851 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10253 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 77690 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1458.353713 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 10159.922633 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 76707 98.73% 98.73% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 405 0.52% 99.26% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 337 0.43% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 198 0.25% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 85546 # Table walker walks requested +system.cpu0.itb.walker.walksLong 85546 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1054 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59782 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10366 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 75180 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1322.160149 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 9414.531253 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 74314 98.85% 98.85% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 448 0.60% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 228 0.30% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 153 0.20% 99.95% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::131072-163839 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 14 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 77690 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 74234 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26234.178409 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23080.051735 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 21732.027543 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 71871 96.82% 96.82% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1986 2.68% 99.49% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 153 0.21% 99.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 128 0.17% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 62 0.08% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 21 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 75180 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 71202 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26797.709334 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23346.070270 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 22372.473032 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 68772 96.59% 96.59% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 2000 2.81% 99.40% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 197 0.28% 99.67% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 144 0.20% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 55 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 74234 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 410290287148 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.846605 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.360675 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 62979367364 15.35% 15.35% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 347270506784 84.64% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 38246000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1931000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 236000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 410290287148 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 62851 98.23% 98.23% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1130 1.77% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 63981 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 71202 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 422744199036 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.876427 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.329334 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 52271860780 12.36% 12.36% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 370441299256 87.63% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 29828500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1210500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 422744199036 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 59782 98.27% 98.27% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1054 1.73% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 60836 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 87943 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 87943 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85546 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85546 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 63981 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 63981 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 151924 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 282848559 # ITB inst hits -system.cpu0.itb.inst_misses 87943 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60836 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60836 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 146382 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 220474674 # ITB inst hits +system.cpu0.itb.inst_misses 85546 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 30949 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 31037 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 212727 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 205838 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 282936502 # ITB inst accesses -system.cpu0.itb.hits 282848559 # DTB hits -system.cpu0.itb.misses 87943 # DTB misses -system.cpu0.itb.accesses 282936502 # DTB accesses -system.cpu0.numPwrStateTransitions 28168 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 14084 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3333377849.836978 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 92382687873.308472 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 4020 28.54% 28.54% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 10033 71.24% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 13 0.09% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 6914082605000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 14084 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 437057662896 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46947293637104 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 874125395 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 220560220 # ITB inst accesses +system.cpu0.itb.hits 220474674 # DTB hits +system.cpu0.itb.misses 85546 # DTB misses +system.cpu0.itb.accesses 220560220 # DTB accesses +system.cpu0.numPwrStateTransitions 10840 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 5420 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 8671662092.472324 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 149203914828.202179 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3833 70.72% 70.72% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1557 28.73% 99.45% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.20% 99.65% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.06% 99.70% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.74% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 13 0.24% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 6993554617000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 5420 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 383509168800 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 47000408541200 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 767019929 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 92275983 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 768900237 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 199183431 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 122923240 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 738928784 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 15190816 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2037144 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 294842 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6072240 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 792344 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 839757 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 282635522 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1737700 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 28623 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 848836502 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.034930 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.208968 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 88196996 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 619911097 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 139955722 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 83698400 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 636708825 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14589342 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2007819 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 289070 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6017581 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 759490 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 830550 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 220269194 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1684756 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 27864 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 742105002 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.977120 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.219124 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 416377385 49.05% 49.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 176079063 20.74% 69.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 66732959 7.86% 77.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 189647095 22.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 394679215 53.18% 53.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 135211877 18.22% 71.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 46727804 6.30% 77.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 165486106 22.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 848836502 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.227866 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.879622 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 110330106 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 381856903 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 311429263 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 39757521 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5462709 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 29836532 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2173523 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 791623702 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 24444549 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5462709 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 147675961 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 53914284 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 258297798 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 313275075 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 70210675 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 773227105 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6509157 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 10689754 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 377832 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 811571 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 32991272 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11799 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 742885425 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1169549966 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 880889153 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 700737 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 682115784 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 60769635 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16576266 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14423738 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 79729853 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 141637487 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 90242008 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9692958 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8374311 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 749539213 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16620515 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 754385019 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2849937 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 57154900 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 36998097 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 294454 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 848836502 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.888728 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.088535 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 742105002 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.182467 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.808207 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 106471358 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 362106065 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 229306920 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 38969186 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5251473 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19951761 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2082457 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 641630797 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23347252 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5251473 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 142650653 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 53065481 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 241402745 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 231558396 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 68176254 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 624076980 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6229632 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 10704846 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 385160 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 931811 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 31501280 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11804 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 596222700 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 963956032 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 736577059 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 695179 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 537389975 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 58832686 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16140854 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14103711 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 78118251 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 102816112 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 86124751 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9533509 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8142362 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 600960924 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16329392 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 605893488 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2751703 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 55206879 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 35882934 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 285911 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 742105002 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.816453 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.065729 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 442949824 52.18% 52.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 161566736 19.03% 71.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 148384909 17.48% 88.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 87697049 10.33% 99.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8232602 0.97% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5382 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 411055814 55.39% 55.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 139198751 18.76% 74.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 116841261 15.74% 89.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 67029634 9.03% 98.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 7974397 1.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5145 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 848836502 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 742105002 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 74538342 48.88% 48.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 62447 0.04% 48.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 15099 0.01% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 9 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 37581602 24.64% 73.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 40298347 26.43% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 62807824 45.43% 45.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 65216 0.05% 45.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 15839 0.01% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 32 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 36880846 26.68% 72.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 38467267 27.83% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 519755806 68.90% 68.90% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1543884 0.20% 69.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 77211 0.01% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 64 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 42719 0.01% 69.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.12% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 144854124 19.20% 88.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 88111156 11.68% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 25 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 414236377 68.37% 68.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1540158 0.25% 68.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 80647 0.01% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 9 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 1 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 41778 0.01% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 105913797 17.48% 86.12% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 84080696 13.88% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 754385019 # Type of FU issued -system.cpu0.iq.rate 0.863017 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 152495846 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.202146 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2511823586 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 823027375 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 736101219 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1128735 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 443604 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 415332 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 906176667 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 704147 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2868207 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 605893488 # Type of FU issued +system.cpu0.iq.rate 0.789932 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 138237024 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228154 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2093764115 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 672208466 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 588253598 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1116590 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 439713 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 411739 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 743434871 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 695616 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2774549 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 13104832 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17724 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 157642 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5794849 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12838296 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17783 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 152412 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5562268 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2875718 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4918474 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2788433 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4754457 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5462709 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7926079 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1884320 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 766295642 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5251473 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7932610 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1687524 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 617423509 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 141637487 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 90242008 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 14144816 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 61216 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1749510 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 157642 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2035907 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3235941 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5271848 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 745963336 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 141529970 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7821454 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 102816112 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 86124751 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13854081 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 62183 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1552208 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 152412 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 1974984 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3105212 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5080196 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 597824194 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 102668745 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7465093 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 135914 # number of nop insts executed -system.cpu0.iew.exec_refs 228324326 # number of memory reference insts executed -system.cpu0.iew.exec_branches 170531782 # Number of branches executed -system.cpu0.iew.exec_stores 86794356 # Number of stores executed -system.cpu0.iew.exec_rate 0.853383 # Inst execution rate -system.cpu0.iew.wb_sent 737330155 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 736516551 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 351214969 # num instructions producing a value -system.cpu0.iew.wb_consumers 595098705 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.842575 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.590179 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 49835507 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 16326061 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4903366 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 839368834 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.844688 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.533259 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 133193 # number of nop insts executed +system.cpu0.iew.exec_refs 185500111 # number of memory reference insts executed +system.cpu0.iew.exec_branches 112433305 # Number of branches executed +system.cpu0.iew.exec_stores 82831366 # Number of stores executed +system.cpu0.iew.exec_rate 0.779412 # Inst execution rate +system.cpu0.iew.wb_sent 589443856 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 588665337 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 287005457 # num instructions producing a value +system.cpu0.iew.wb_consumers 470602155 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.767471 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609869 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 48230515 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 16043481 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4724520 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 732949405 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.766879 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.569816 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 512658006 61.08% 61.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 158759517 18.91% 79.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 92536082 11.02% 91.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 27862473 3.32% 94.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13576189 1.62% 95.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9358920 1.11% 97.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6289735 0.75% 97.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3875341 0.46% 98.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14452571 1.72% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 487135616 66.46% 66.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 127506386 17.40% 83.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 54345658 7.41% 91.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18167389 2.48% 93.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13030534 1.78% 95.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9013680 1.23% 96.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6080548 0.83% 97.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3647046 0.50% 98.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14022548 1.91% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 839368834 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 622433451 # Number of instructions committed -system.cpu0.commit.committedOps 709004821 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 732949405 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 479057822 # Number of instructions committed +system.cpu0.commit.committedOps 562083399 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 212979813 # Number of memory references committed -system.cpu0.commit.loads 128532654 # Number of loads committed -system.cpu0.commit.membars 3921678 # Number of memory barriers committed -system.cpu0.commit.branches 164749224 # Number of branches committed -system.cpu0.commit.fp_insts 407380 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 634275437 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14942203 # Number of function calls committed. +system.cpu0.commit.refs 170540284 # Number of memory references committed +system.cpu0.commit.loads 89977801 # Number of loads committed +system.cpu0.commit.membars 3918882 # Number of memory barriers committed +system.cpu0.commit.branches 106864519 # Number of branches committed +system.cpu0.commit.fp_insts 404083 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 515735338 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14196925 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 494636379 69.76% 69.76% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1291078 0.18% 69.95% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 60530 0.01% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 37021 0.01% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 128532654 18.13% 88.09% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 84447159 11.91% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 390151246 69.41% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1292004 0.23% 69.64% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 63609 0.01% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 36256 0.01% 69.66% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.66% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.66% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.66% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 89977801 16.01% 85.67% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 80562483 14.33% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 709004821 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14452571 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1579278211 # The number of ROB reads -system.cpu0.rob.rob_writes 1527109253 # The number of ROB writes -system.cpu0.timesIdled 1033857 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25288893 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93894577230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 622433451 # Number of Instructions Simulated -system.cpu0.committedOps 709004821 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.404368 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.404368 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.712064 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.712064 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 848778973 # number of integer regfile reads -system.cpu0.int_regfile_writes 506977822 # number of integer regfile writes -system.cpu0.fp_regfile_reads 685984 # number of floating regfile reads -system.cpu0.fp_regfile_writes 317032 # number of floating regfile writes -system.cpu0.cc_regfile_reads 188384037 # number of cc regfile reads -system.cpu0.cc_regfile_writes 189031095 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1602344785 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16401028 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6409966 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.619482 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 199938758 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6410478 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.189368 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 562083399 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14022548 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1325013729 # The number of ROB reads +system.cpu0.rob.rob_writes 1229746140 # The number of ROB writes +system.cpu0.timesIdled 998783 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 24914927 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 94000815527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 479057822 # Number of Instructions Simulated +system.cpu0.committedOps 562083399 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.601101 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.601101 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.624570 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.624570 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 705670279 # number of integer regfile reads +system.cpu0.int_regfile_writes 419695299 # number of integer regfile writes +system.cpu0.fp_regfile_reads 680997 # number of floating regfile reads +system.cpu0.fp_regfile_writes 310212 # number of floating regfile writes +system.cpu0.cc_regfile_reads 130338984 # number of cc regfile reads +system.cpu0.cc_regfile_writes 131056521 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1328403158 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16107336 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6279329 # number of replacements +system.cpu0.dcache.tags.tagsinuse 481.718631 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 157880144 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6279840 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.140791 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.619482 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938710 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938710 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 439216738 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 439216738 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 121629785 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 121629785 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73254039 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73254039 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 225954 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 225954 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 195110 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 195110 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1865486 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1865486 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1919454 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1919454 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 195078934 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 195078934 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 195304888 # number of overall hits -system.cpu0.dcache.overall_hits::total 195304888 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7140435 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7140435 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 8024708 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 8024708 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 776369 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 776369 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 838591 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 838591 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 289464 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 289464 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195968 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 195968 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 16003734 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 16003734 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 16780103 # number of overall misses -system.cpu0.dcache.overall_misses::total 16780103 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 108528058000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 108528058000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 153779451872 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 153779451872 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 31763636892 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 31763636892 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4317295000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4317295000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4927286000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4927286000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3123500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3123500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 294071146764 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 294071146764 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 294071146764 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 294071146764 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 128770220 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 128770220 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81278747 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81278747 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1002323 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1002323 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1033701 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1033701 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2154950 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2154950 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2115422 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2115422 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 211082668 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 211082668 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 212084991 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 212084991 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.055451 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.055451 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.098731 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.098731 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.774570 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.774570 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.811251 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.811251 # 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average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19163.245799 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37877.388252 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37877.388252 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14914.790786 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14914.790786 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25143.319317 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25143.319317 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.718631 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940857 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.940857 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 354237308 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 354237308 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 83229187 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 83229187 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69700757 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69700757 # 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number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7047364 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7798246 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7798246 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 750513 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 750513 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796040 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 796040 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 285990 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 285990 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189707 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 189707 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 15641650 # 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number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4536657500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4536657500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2221500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2221500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 285924221171 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 285924221171 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 285924221171 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 285924221171 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 90276551 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 90276551 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77499003 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77499003 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 952272 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 952272 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 944085 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 944085 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2149453 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2149453 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2112219 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2112219 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 168719639 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 168719639 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 169671911 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 169671911 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078064 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.078064 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.100624 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.100624 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.788129 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788129 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843187 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.843187 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.133052 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.133052 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089814 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089814 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092708 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092708 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096611 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096611 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15124.388282 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15124.388282 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19142.332765 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19142.332765 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37762.589517 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37762.589517 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14581.696912 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14581.696912 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23914.022677 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23914.022677 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18375.158370 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18375.158370 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17524.990566 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17524.990566 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9668545 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 23532840 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 779892 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 794197 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.397287 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 29.630986 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6410042 # number of writebacks -system.cpu0.dcache.writebacks::total 6410042 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3690786 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3690786 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6446005 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6446005 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4347 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4347 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 149571 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 149571 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 10141138 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 10141138 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 10141138 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 10141138 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3449649 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3449649 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1578703 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1578703 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 769355 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 769355 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 834244 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 834244 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139893 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139893 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195965 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 195965 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5862596 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5862596 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6631951 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6631951 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31285 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31285 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30958 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 30958 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62243 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62243 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50416416500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50416416500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 33875543231 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33875543231 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17245260500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17245260500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 30759768392 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 30759768392 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1918237000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1918237000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4731380000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4731380000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3064500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3064500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 115051728123 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 115051728123 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 132296988623 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 132296988623 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6062914000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6062914000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6062914000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6062914000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.026789 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026789 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019423 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019423 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.767572 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767572 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.807046 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.807046 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064917 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064917 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092636 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092636 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027774 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027774 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031270 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031270 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14614.940969 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14614.940969 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21457.831670 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21457.831670 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22415.218592 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22415.218592 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36871.428973 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36871.428973 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13712.172875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13712.172875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24144.005307 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24144.005307 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18279.671337 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18279.671337 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17442.739019 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17442.739019 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9136124 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 22955799 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 744485 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 773832 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.271737 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 29.665094 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 6279393 # number of writebacks +system.cpu0.dcache.writebacks::total 6279393 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3627313 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3627313 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6268862 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6268862 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4039 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4039 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 145852 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 145852 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9900214 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9900214 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9900214 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9900214 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3420051 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3420051 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1529384 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1529384 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 743716 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 743716 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792001 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 792001 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140138 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140138 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189707 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 189707 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5741436 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5741436 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6485152 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6485152 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17085 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17085 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18834 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18834 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35919 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 35919 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49260241500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49260241500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32250000948 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 32250000948 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16897998500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16897998500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 29124405259 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 29124405259 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1866604500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1866604500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4347004500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4347004500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2167500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2167500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110634647707 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 110634647707 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 127532646207 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 127532646207 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3215151000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3215151000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3215151000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3215151000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037884 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037884 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019734 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019734 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.780991 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.780991 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.838909 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.838909 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065197 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065197 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089814 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089814 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034029 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034029 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038222 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.038222 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14403.364599 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14403.364599 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21086.921890 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21086.921890 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22721.036659 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22721.036659 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36773.192533 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36773.192533 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13319.759808 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13319.759808 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22914.307327 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22914.307327 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19624.706891 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19624.706891 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19948.426733 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19948.426733 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193796.196260 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193796.196260 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97407.162251 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97407.162251 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 6234341 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.962382 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 276007197 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6234853 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 44.268437 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12884658000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962382 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19269.508135 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19269.508135 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19665.328771 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19665.328771 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188185.601405 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188185.601405 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89511.150088 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89511.150088 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 5960489 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.962298 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 213927686 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5961001 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.887880 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13033031000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962298 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999926 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999926 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 571449747 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 571449747 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 276007197 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 276007197 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 276007197 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 276007197 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 276007197 # number of overall hits -system.cpu0.icache.overall_hits::total 276007197 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6600102 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6600102 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6600102 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6600102 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6600102 # number of overall misses -system.cpu0.icache.overall_misses::total 6600102 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71550800576 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 71550800576 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 71550800576 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 71550800576 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 71550800576 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 71550800576 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 282607299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 282607299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 282607299 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 282607299 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 282607299 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 282607299 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.023354 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023354 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.023354 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023354 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.023354 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023354 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10840.862850 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10840.862850 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10840.862850 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10840.862850 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10840.862850 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10840.862850 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10420482 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1138 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 752268 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.852087 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 103.454545 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 6234341 # number of writebacks -system.cpu0.icache.writebacks::total 6234341 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 364953 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 364953 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 364953 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 364953 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 364953 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 364953 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6235149 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6235149 # 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number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64720811973 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 64720811973 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64720811973 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 64720811973 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62354110053 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 62354110053 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62354110053 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 62354110053 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62354110053 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 62354110053 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1885677498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1885677498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.022063 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.022063 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.022063 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10379.994443 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10379.994443 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10379.994443 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027066 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027066 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027066 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10460.243888 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10460.243888 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10460.243888 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8818791 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8829534 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 9675 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8592940 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8600926 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7220 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1134314 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2939155 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16147.226336 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 18219506 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2955258 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.165115 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2212473000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15244.220202 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.043386 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 62.165258 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000002 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 782.797489 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.930433 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003543 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003794 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.047778 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985548 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1151 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14871 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 189 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 576 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 372 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 48 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1385 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6005 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4408 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2945 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.070251 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004944 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.907654 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 433411639 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 433411639 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 616680 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 198735 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 815415 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4206029 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4206029 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 8435953 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 8435953 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 888 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 888 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1016467 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 1016467 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5621992 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5621992 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3255070 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 3255070 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 189931 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 189931 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 616680 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 198735 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5621992 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4271537 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10708944 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 616680 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 198735 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5621992 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4271537 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10708944 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13303 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10046 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 23349 # number of ReadReq misses -system.cpu0.l2cache.WritebackDirty_misses::writebacks 5 # number of WritebackDirty misses -system.cpu0.l2cache.WritebackDirty_misses::total 5 # number of WritebackDirty misses -system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses -system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 270883 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 270883 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 195959 # 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average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38987.144877 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56590.929630 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20556.048168 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20556.048168 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16627.774157 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16627.774157 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 655374.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 655374.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 44819.023202 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 44819.023202 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28775.786737 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31374.295958 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31374.295958 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36606.229223 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36606.229223 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34126.392569 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32554.736432 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34126.392569 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40136.035953 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228959 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 32290.152869 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59475.138338 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18533.216598 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18533.216598 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15397.474383 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15397.474383 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 587500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 587500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45129.381880 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45129.381880 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29103.997241 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31830.259628 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31830.259628 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36425.359014 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36425.359014 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34545.803791 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32838.272405 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34545.803791 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41184.535280 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185781.620585 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143370.934611 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180158.267486 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125175.439054 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93378.821715 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90238.424152 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 26220064 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13479100 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2657 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2182451 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2181920 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 531 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 979416 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11666319 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 30958 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 30958 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 6060800 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8438347 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2860883 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1184490 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 488552 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348527 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 533031 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1347603 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1325056 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6235149 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5307790 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 891051 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 832317 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18746760 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20650560 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 436622 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1328978 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 41162920 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 798358288 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 780155262 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1670248 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5039864 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1585223662 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7567060 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 126041936 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 21529267 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.118569 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.323357 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85692.920182 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83968.101098 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 25397703 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13066663 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1795 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 671473 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 671468 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 963728 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11315166 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 18834 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 18834 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5872564 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8129050 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1348327 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1122615 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 22 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 466810 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 338240 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 510310 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1307620 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1285212 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5961057 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5219350 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 843100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 790085 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17925156 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20147173 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 419117 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1337980 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 39829426 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 763317520 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 765224037 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1592032 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5061960 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1535195549 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5838031 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 119621704 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 19351504 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.054273 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.226556 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 18977100 88.15% 88.15% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2551636 11.85% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 531 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 18301249 94.57% 94.57% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 1050250 5.43% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 5 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 21529267 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 26091722433 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 19351504 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 25250991712 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 187623310 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 173970437 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9380939070 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 8969219750 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9216328089 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9025116687 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 228203766 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 220608496 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 699632706 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 706093257 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 194671556 # Number of BP lookups -system.cpu1.branchPred.condPredicted 153305610 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6254288 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 157865267 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 88709282 # Number of BTB hits +system.cpu1.branchPred.lookups 128968222 # Number of BP lookups +system.cpu1.branchPred.condPredicted 85282466 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6518355 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 89675287 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 55364340 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 56.193033 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16475486 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 172497 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3896881 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2381021 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1515860 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 389837 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 61.738682 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17439644 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 182879 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 4134289 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2557852 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1576437 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 401535 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1724,93 +1712,96 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 533309 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 533309 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10503 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 81680 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 248509 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 284800 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2470.932233 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 13518.648671 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-32767 279405 98.11% 98.11% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-65535 3083 1.08% 99.19% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-98303 908 0.32% 99.51% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-131071 713 0.25% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-163839 284 0.10% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::163840-196607 163 0.06% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-229375 124 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::229376-262143 32 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-294911 13 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::294912-327679 40 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-360447 32 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 531460 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 531460 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10155 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 82594 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 244261 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 287199 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2189.199823 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 12408.912934 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-32767 282304 98.30% 98.30% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-65535 2996 1.04% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-98303 743 0.26% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-131071 602 0.21% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-163839 197 0.07% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::163840-196607 152 0.05% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-229375 103 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::229376-262143 33 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-294911 16 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::294912-327679 35 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-360447 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 284800 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 268382 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 19517.668845 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17136.373439 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13227.910444 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 250971 93.51% 93.51% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 15361 5.72% 99.24% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 757 0.28% 99.52% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 835 0.31% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 87 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 116 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 116 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 51 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 29 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 31 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 7 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 15 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 287199 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 267684 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20635.114538 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18133.747768 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 11911.787641 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 239914 89.63% 89.63% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 26330 9.84% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 756 0.28% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 476 0.18% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 73 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 24 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 55 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 22 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 9 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 8 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 268382 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 466126532996 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.617043 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.546089 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 464998520496 99.76% 99.76% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 569195000 0.12% 99.88% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 249472000 0.05% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 122508000 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 91886000 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 55274500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 15901500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 23390500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 385000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 466126532996 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 81681 88.61% 88.61% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10503 11.39% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 92184 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 533309 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 267684 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 465694213496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.593113 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.550788 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 464589649996 99.76% 99.76% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 559093500 0.12% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 239052500 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 120378000 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 87009500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 57335500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 14978500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 26310000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 396500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 465694213496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 82595 89.05% 89.05% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10155 10.95% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 92750 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 531460 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 533309 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92184 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 531460 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92750 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92184 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 625493 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92750 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 624210 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 161844710 # DTB read hits -system.cpu1.dtb.read_misses 366883 # DTB read misses -system.cpu1.dtb.write_hits 74184112 # DTB write hits -system.cpu1.dtb.write_misses 166426 # DTB write misses +system.cpu1.dtb.read_hits 93944307 # DTB read hits +system.cpu1.dtb.read_misses 364370 # DTB read misses +system.cpu1.dtb.write_hits 78170381 # DTB write hits +system.cpu1.dtb.write_misses 167090 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 34599 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 386 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6272 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 34720 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 381 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 5735 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 37354 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 162211593 # DTB read accesses -system.cpu1.dtb.write_accesses 74350538 # DTB write accesses +system.cpu1.dtb.perms_faults 39000 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 94308677 # DTB read accesses +system.cpu1.dtb.write_accesses 78337471 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 236028822 # DTB hits -system.cpu1.dtb.misses 533309 # DTB misses -system.cpu1.dtb.accesses 236562131 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 172114688 # DTB hits +system.cpu1.dtb.misses 531460 # DTB misses +system.cpu1.dtb.accesses 172646148 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1840,1178 +1831,1180 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 80718 # Table walker walks requested -system.cpu1.itb.walker.walksLong 80718 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 768 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57037 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 10137 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 70581 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 996.309205 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 6981.449622 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 70036 99.23% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 380 0.54% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 60 0.09% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 83 0.12% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 82381 # Table walker walks requested +system.cpu1.itb.walker.walksLong 82381 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1018 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59631 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9853 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 72528 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 882.590172 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 6870.472006 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 72114 99.43% 99.43% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 279 0.38% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 39 0.05% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 75 0.10% 99.97% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 70581 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 67942 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24162.219246 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22142.693859 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 15015.121608 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 66991 98.60% 98.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 778 1.15% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 100 0.15% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 45 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 67942 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 397380257260 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.877039 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.328570 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 48883602860 12.30% 12.30% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 348476867900 87.69% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 18158500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1572000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 56000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 397380257260 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 57037 98.67% 98.67% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 768 1.33% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 57805 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::163840-196607 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 72528 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 70502 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24022.878784 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22243.496704 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 12757.621468 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 63844 90.56% 90.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 6070 8.61% 99.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 93 0.13% 99.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 382 0.54% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 44 0.06% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 19 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 18 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 70502 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 379792000076 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.874646 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.331269 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 47625596788 12.54% 12.54% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 332150851288 87.46% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 14331500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 990000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 230500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 379792000076 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 59631 98.32% 98.32% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 1018 1.68% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 60649 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 80718 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 80718 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82381 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82381 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57805 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 57805 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 138523 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 264777096 # ITB inst hits -system.cpu1.itb.inst_misses 80718 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 60649 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 60649 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 143030 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 201934152 # ITB inst hits +system.cpu1.itb.inst_misses 82381 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 24684 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 24569 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 195163 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 202631 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 264857814 # ITB inst accesses -system.cpu1.itb.hits 264777096 # DTB hits -system.cpu1.itb.misses 80718 # DTB misses -system.cpu1.itb.accesses 264857814 # DTB accesses -system.cpu1.numPwrStateTransitions 9670 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 4835 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 9724953244.725336 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 147881742434.863098 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3183 65.83% 65.83% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1626 33.63% 99.46% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.04% 99.50% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.10% 99.61% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.04% 99.65% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.67% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.71% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 14 0.29% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7390881470984 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 4835 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 364202361753 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47020148938247 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 728406370 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 202016533 # ITB inst accesses +system.cpu1.itb.hits 201934152 # DTB hits +system.cpu1.itb.misses 82381 # DTB misses +system.cpu1.itb.accesses 202016533 # DTB accesses +system.cpu1.numPwrStateTransitions 26784 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 13392 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3512583180.059961 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 88770415671.353104 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3351 25.02% 25.02% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 10014 74.78% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.82% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 4 0.03% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3.5e+11-4e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 7430623145540 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 13392 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 343403762637 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47040513947363 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 686817572 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 83192103 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 724269312 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 194671556 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 107565789 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 610871186 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13439122 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1719504 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 273339 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 5608482 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 704978 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 774415 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 264561727 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1602178 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 26700 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 709863568 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.153991 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.257090 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 87491536 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 569150585 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 128968222 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 75361836 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 564504137 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 14030828 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1743458 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 273069 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 5670150 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 713565 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 783781 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 201710843 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1678338 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 26867 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 668195110 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.000138 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.225435 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 331851103 46.75% 46.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 119648081 16.86% 63.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 75565351 10.65% 74.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 182799033 25.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 348421230 52.14% 52.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 124504424 18.63% 70.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 42025261 6.29% 77.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 153244195 22.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 709863568 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.267257 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.994320 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 98062054 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 297890044 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 275618841 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 33512378 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4780251 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17247911 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1977266 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 743961992 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21656856 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4780251 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 130238128 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 40363481 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 204147620 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 276602035 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 53732053 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 728176206 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5626727 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9082967 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 240191 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 268836 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 22296515 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 11543 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 630286495 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 1024905330 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 827525539 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 801877 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 577128327 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 53158158 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14384532 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 12638476 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 67737488 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 162372694 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 77181222 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8520193 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7294637 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 707349171 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 14663402 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 711466322 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2509310 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 50084332 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 32217686 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 252969 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 709863568 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.002258 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.141899 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 668195110 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.187777 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.828678 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 102161242 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 311763510 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 215198558 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 34078749 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4993051 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 18208977 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2060516 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 590405276 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22672761 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4993051 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 135354794 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 41008219 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 216515907 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 215714387 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 54608752 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 573925738 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5865325 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9111156 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 235226 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 246551 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 22706071 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 10845 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 544713354 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 881414288 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 677140554 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 799785 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 489645115 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 55068233 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14685141 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 12835902 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 68922736 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 94552173 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 81340147 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8760661 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7542596 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 552653279 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 14818656 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 556478216 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2578197 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 52065959 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 33349277 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 259122 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 668195110 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.832808 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.070079 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 346424684 48.80% 48.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 123916139 17.46% 66.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 138092978 19.45% 85.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 94358537 13.29% 99.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7067534 1.00% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 3696 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 364178661 54.50% 54.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 127786531 19.12% 73.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 107346035 16.07% 89.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 61539810 9.21% 98.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7340180 1.10% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3893 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 709863568 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 668195110 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 53419887 27.72% 27.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 53191 0.03% 27.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 19037 0.01% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 15 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 103986379 53.96% 81.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 35231745 18.28% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 55774345 44.07% 44.07% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 53478 0.04% 44.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 18362 0.01% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 15 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 33579431 26.53% 70.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 37124892 29.34% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 25 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 469996066 66.06% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1210560 0.17% 66.23% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 70927 0.01% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 81598 0.01% 66.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 164776620 23.16% 89.41% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 75330478 10.59% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 35 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 378772554 68.07% 68.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1203453 0.22% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 69506 0.01% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 82169 0.01% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 96967073 17.43% 85.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 79383378 14.27% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 711466322 # Type of FU issued -system.cpu1.iq.rate 0.976744 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 192710254 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.270863 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 2326678945 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 771690256 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 695698465 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1336829 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 536159 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 497637 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 903350253 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 826298 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2394067 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 556478216 # Type of FU issued +system.cpu1.iq.rate 0.810227 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 126550523 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227413 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1908944024 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 619142753 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 540109020 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1336236 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 533681 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 496559 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 682200972 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 827732 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2535076 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11654320 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 15948 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 130447 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5130974 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 12050927 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 15964 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 139670 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5367770 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2399995 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3738162 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2479862 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3811174 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4780251 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5901245 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1355404 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 722138785 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4993051 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6066595 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1484920 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 567600146 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 162372694 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 77181222 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12419825 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 58724 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1239916 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 130447 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1767111 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2862185 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4629296 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 704121990 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 161840669 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6820718 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 94552173 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 81340147 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12593166 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 61012 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1366008 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 139670 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1864288 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2962654 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4826942 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 548760252 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 93936954 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 7198002 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 126212 # number of nop insts executed -system.cpu1.iew.exec_refs 236024480 # number of memory reference insts executed -system.cpu1.iew.exec_branches 169760384 # Number of branches executed -system.cpu1.iew.exec_stores 74183811 # Number of stores executed -system.cpu1.iew.exec_rate 0.966661 # Inst execution rate -system.cpu1.iew.wb_sent 696881354 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 696196102 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 357262878 # num instructions producing a value -system.cpu1.iew.wb_consumers 517340824 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.955780 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.690575 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 43732145 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14410433 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4314978 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 701540457 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.957790 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.589997 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 128211 # number of nop insts executed +system.cpu1.iew.exec_refs 172107181 # number of memory reference insts executed +system.cpu1.iew.exec_branches 103045741 # Number of branches executed +system.cpu1.iew.exec_stores 78170227 # Number of stores executed +system.cpu1.iew.exec_rate 0.798990 # Inst execution rate +system.cpu1.iew.wb_sent 541337937 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 540605579 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 260784878 # num instructions producing a value +system.cpu1.iew.wb_consumers 427489689 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.787117 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610038 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 45375845 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14559534 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4495992 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 659550921 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.781450 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.574730 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 413092247 58.88% 58.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 113176092 16.13% 75.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 83530992 11.91% 86.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 51841229 7.39% 94.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11508500 1.64% 95.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 7726725 1.10% 97.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5343630 0.76% 97.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3131269 0.45% 98.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12189773 1.74% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 433210493 65.68% 65.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 117319741 17.79% 83.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 50366969 7.64% 91.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 16989740 2.58% 93.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 12025543 1.82% 95.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8091474 1.23% 96.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5593324 0.85% 97.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3365512 0.51% 98.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12588125 1.91% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 701540457 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 597176554 # Number of instructions committed -system.cpu1.commit.committedOps 671928235 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 659550921 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 437257329 # Number of instructions committed +system.cpu1.commit.committedOps 515405969 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 222768619 # Number of memory references committed -system.cpu1.commit.loads 150718371 # Number of loads committed -system.cpu1.commit.membars 39196572 # Number of memory barriers committed -system.cpu1.commit.branches 164739467 # Number of branches committed -system.cpu1.commit.fp_insts 488627 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 631392614 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12167965 # Number of function calls committed. +system.cpu1.commit.refs 158473622 # Number of memory references committed +system.cpu1.commit.loads 82501245 # Number of loads committed +system.cpu1.commit.membars 3568741 # Number of memory barriers committed +system.cpu1.commit.branches 97797753 # Number of branches committed +system.cpu1.commit.fp_insts 487077 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 473223690 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12865392 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 448043617 66.68% 66.68% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 985154 0.15% 66.83% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 56630 0.01% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 74173 0.01% 66.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 150718371 22.43% 89.28% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 72050248 10.72% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 355828768 69.04% 69.04% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 973462 0.19% 69.23% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 55201 0.01% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 74874 0.01% 69.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.25% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 82501245 16.01% 85.26% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 75972377 14.74% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 671928235 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12189773 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1401264531 # The number of ROB reads -system.cpu1.rob.rob_writes 1439606443 # The number of ROB writes -system.cpu1.timesIdled 902579 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 18542802 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94040296263 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 597176554 # Number of Instructions Simulated -system.cpu1.committedOps 671928235 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.219750 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.219750 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.819840 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.819840 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 799341399 # number of integer regfile reads -system.cpu1.int_regfile_writes 475575163 # number of integer regfile writes -system.cpu1.fp_regfile_reads 787030 # number of floating regfile reads -system.cpu1.fp_regfile_writes 454812 # number of floating regfile writes -system.cpu1.cc_regfile_reads 112918659 # number of cc regfile reads -system.cpu1.cc_regfile_writes 113685571 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1436513215 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14489141 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5047432 # number of replacements -system.cpu1.dcache.tags.tagsinuse 457.905792 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 212666270 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5047943 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 42.129293 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8477400492000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.905792 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.894347 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.894347 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 457080025 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 457080025 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 145190780 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 145190780 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 62993534 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 62993534 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 167629 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 167629 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 116242 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 116242 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1721505 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1721505 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1728884 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1728884 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 208300556 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 208300556 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 208468185 # number of overall hits -system.cpu1.dcache.overall_hits::total 208468185 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 5993321 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 5993321 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6604202 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6604202 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 607895 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 607895 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 421696 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 421696 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 237246 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 237246 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187668 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 187668 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13019219 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13019219 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 13627114 # number of overall misses -system.cpu1.dcache.overall_misses::total 13627114 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 89379669000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 89379669000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119695443135 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 119695443135 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10488678921 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 10488678921 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3322992000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3322992000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4669078500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4669078500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3521000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3521000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 219563791056 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 219563791056 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 219563791056 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 219563791056 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 151184101 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 151184101 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 69597736 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 69597736 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 775524 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 775524 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 537938 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 537938 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1958751 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1958751 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1916552 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1916552 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 221319775 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 221319775 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 222095299 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 222095299 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039643 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.039643 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094891 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.094891 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.783851 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.783851 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.783912 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.783912 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121121 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121121 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097920 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097920 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.058825 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.058825 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.061357 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.061357 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14913.212391 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14913.212391 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18124.134170 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18124.134170 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24872.607094 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24872.607094 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14006.524873 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14006.524873 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24879.460004 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24879.460004 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 515405969 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12588125 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1203797977 # The number of ROB reads +system.cpu1.rob.rob_writes 1130170940 # The number of ROB writes +system.cpu1.timesIdled 922689 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 18622462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94081017888 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 437257329 # Number of Instructions Simulated +system.cpu1.committedOps 515405969 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.570740 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.570740 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.636643 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.636643 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 647634757 # number of integer regfile reads +system.cpu1.int_regfile_writes 384292228 # number of integer regfile writes +system.cpu1.fp_regfile_reads 785728 # number of floating regfile reads +system.cpu1.fp_regfile_writes 454696 # number of floating regfile writes +system.cpu1.cc_regfile_reads 117471222 # number of cc regfile reads +system.cpu1.cc_regfile_writes 118161265 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1199366647 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14671382 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5153619 # number of replacements +system.cpu1.dcache.tags.tagsinuse 456.044406 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 148207895 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5154131 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.755166 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8517415326000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.044406 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890712 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.890712 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 328622817 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 328622817 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 76967758 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 76967758 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 66682281 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 66682281 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 189501 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 189501 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 166829 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 166829 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1726427 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1726427 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1743769 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1743769 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 143816868 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 143816868 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 144006369 # number of overall hits +system.cpu1.dcache.overall_hits::total 144006369 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 5978399 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 5978399 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6727643 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6727643 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 625948 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 625948 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 458256 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 458256 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 242959 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 242959 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 183921 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 183921 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13164298 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13164298 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13790246 # number of overall misses +system.cpu1.dcache.overall_misses::total 13790246 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 87383841500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 87383841500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119886339095 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 119886339095 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11324190656 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 11324190656 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3328957500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3328957500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4379371000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4379371000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2907500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2907500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 218594371251 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 218594371251 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 218594371251 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 218594371251 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 82946157 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 82946157 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 73409924 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 73409924 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 815449 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 815449 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 625085 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 625085 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1969386 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1969386 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1927690 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1927690 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 156981166 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 156981166 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 157796615 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 157796615 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072076 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.072076 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.091645 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.091645 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.767611 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.767611 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.733110 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.733110 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.123368 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.123368 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095410 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095410 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083859 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.083859 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087393 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.087393 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14616.595764 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14616.595764 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17819.961478 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17819.961478 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24711.494571 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24711.494571 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13701.725394 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13701.725394 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23811.152614 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23811.152614 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16864.590038 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16864.590038 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16112.273740 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16112.273740 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 2706631 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18960106 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 351175 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 660083 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.707357 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 28.723821 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5047462 # number of writebacks -system.cpu1.dcache.writebacks::total 5047462 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3052290 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3052290 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5325465 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5325465 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3276 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3276 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 122610 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 122610 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8381031 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8381031 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8381031 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8381031 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2941031 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2941031 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1278737 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1278737 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 607807 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 607807 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 418420 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 418420 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 114636 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 114636 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187667 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 187667 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4638188 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4638188 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5245995 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5245995 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7218 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7218 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7480 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7480 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14698 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14698 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39704145500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39704145500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24666220214 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24666220214 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14600377000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14600377000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9957787421 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9957787421 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1521960000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1521960000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4481476500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4481476500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3456000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3456000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74328153135 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 74328153135 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 88928530135 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 88928530135 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 880126000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 880126000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 880126000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 880126000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.019453 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.019453 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018373 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018373 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.783737 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.783737 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.777822 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.777822 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058525 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058525 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097919 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097919 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.020957 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.020957 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.023620 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.023620 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13500.077184 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13500.077184 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19289.517871 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19289.517871 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24021.403176 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24021.403176 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23798.545531 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23798.545531 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.457657 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.457657 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23879.938934 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23879.938934 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16605.091381 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16605.091381 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15851.375766 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15851.375766 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 2917967 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18895353 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 374678 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 668758 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.787933 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 28.254395 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 5153631 # number of writebacks +system.cpu1.dcache.writebacks::total 5153631 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3023211 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3023211 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5427179 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5427179 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3743 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3743 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 127495 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 127495 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8454133 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8454133 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8454133 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8454133 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2955188 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2955188 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1300464 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1300464 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 625861 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 625861 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 454513 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 454513 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115464 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115464 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 183920 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 183920 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4710165 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4710165 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5336026 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5336026 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21232 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21232 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19410 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 19410 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40642 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40642 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40128990000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40128990000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24368462066 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24368462066 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13718666000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13718666000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10741056156 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10741056156 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1514532000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1514532000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4195522000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4195522000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2836500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2836500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 75238508222 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 75238508222 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 88957174222 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 88957174222 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3718611500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3718611500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3718611500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3718611500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035628 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035628 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017715 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017715 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.767505 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.767505 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.727122 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.727122 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058629 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058629 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095410 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095410 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030005 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030005 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033816 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033816 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13579.166537 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13579.166537 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18738.282694 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18738.282694 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21919.669064 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21919.669064 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23632.010869 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23632.010869 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13116.919559 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13116.919559 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22811.668117 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22811.668117 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16025.256659 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16025.256659 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16951.699370 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16951.699370 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 121934.885010 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 121934.885010 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59880.664036 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59880.664036 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 5706197 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.707809 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 258521982 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5706709 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 45.301413 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8517122288000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.707809 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979898 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.979898 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15973.645981 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15973.645981 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16671.053369 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16671.053369 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175141.837792 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 175141.837792 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91496.764431 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91496.764431 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 6014648 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.532915 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 195349774 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 6015160 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 32.476239 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8517720712000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.532915 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979556 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.979556 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 307 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 341 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 534817167 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 534817167 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 258521982 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 258521982 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 258521982 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 258521982 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 258521982 # number of overall hits -system.cpu1.icache.overall_hits::total 258521982 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6033199 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6033199 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6033199 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6033199 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6033199 # number of overall misses -system.cpu1.icache.overall_misses::total 6033199 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64071626251 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 64071626251 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 64071626251 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 64071626251 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 64071626251 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 64071626251 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 264555181 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 264555181 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 264555181 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 264555181 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 264555181 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 264555181 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022805 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.022805 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022805 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.022805 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022805 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.022805 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10619.843014 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10619.843014 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10619.843014 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10619.843014 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10619.843014 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10619.843014 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 9429094 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 244 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 708482 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 409423979 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 409423979 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 195349774 # 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number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 66668444908 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 66668444908 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 66668444908 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 66668444908 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 201704396 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 201704396 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 201704396 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 201704396 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 201704396 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 201704396 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031505 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.031505 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031505 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.031505 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031505 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.031505 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10491.331335 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10491.331335 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10491.331335 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10491.331335 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10491.331335 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10491.331335 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 9555681 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 472 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 727552 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.308869 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 5706197 # number of writebacks -system.cpu1.icache.writebacks::total 5706197 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 326394 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 326394 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 326394 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 326394 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 326394 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 326394 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5706805 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5706805 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5706805 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5706805 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5706805 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5706805 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58058775330 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 58058775330 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58058775330 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 58058775330 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58058775330 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 58058775330 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6679498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6679498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6679498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6679498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021571 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.021571 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.021571 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10173.604202 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10173.604202 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10173.604202 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99694 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99694 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99694 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99694 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6901811 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6907587 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 5314 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.134018 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 118 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 6014648 # number of writebacks +system.cpu1.icache.writebacks::total 6014648 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 339435 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 339435 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 339435 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 339435 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 339435 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 339435 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6015187 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 6015187 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 6015187 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 6015187 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 6015187 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 6015187 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 68 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 68 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 68 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 68 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 60428904539 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 60428904539 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 60428904539 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 60428904539 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 60428904539 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 60428904539 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6183499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6183499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6183499 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6183499 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.029822 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.029822 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.029822 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10046.055848 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10046.055848 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10046.055848 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90933.808824 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90933.808824 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6826847 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6833838 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 6347 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 821749 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2026075 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13356.542127 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 16274118 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2041771 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.970589 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9992426830500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12440.422172 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 43.172118 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 33.879322 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000015 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 839.068499 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.759303 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002635 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002068 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051213 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.815219 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1386 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 96 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14214 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 75 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 230 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 627 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 454 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 797 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4633 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4798 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3775 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.084595 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005859 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.867554 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 369100514 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 369100514 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 546957 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 179929 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 726886 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3170558 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3170558 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 7581614 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 7581614 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 544 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 544 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 815108 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 815108 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5173102 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 5173102 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2742764 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2742764 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 184198 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 184198 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 546957 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 179929 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5173102 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3557872 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9457860 # 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mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.146352 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.033331 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044154 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.088092 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.236871 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.216738 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30698.366424 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44779.098624 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21123.913810 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21123.913810 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16366.066612 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16366.066612 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247208.166667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247208.166667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33772.345856 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33772.345856 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28015.333267 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28790.171126 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28790.171126 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26887.644192 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26887.644192 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29817.820889 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29263.608095 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29817.820889 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33864.848983 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 113906.275977 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113706.451613 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55937.916723 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56102.370471 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 22350657 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11505244 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1543 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1883368 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1883027 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 341 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 842183 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10302833 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 7480 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7480 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4215889 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 7583095 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2514473 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 909607 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 430035 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 341692 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 476439 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1090279 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1068076 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5706805 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4656106 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 474602 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 416607 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17119850 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16343111 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 395526 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1186164 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 35044651 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 730427376 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 631688689 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1504072 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4470264 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1368090401 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6163170 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 73999248 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 18018661 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.123449 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.329009 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.206422 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24907.731273 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 47104.456602 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18790.618769 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18790.618769 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15296.842015 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15296.842015 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 574874.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 574874.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33451.032223 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33451.032223 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28270.219367 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28485.685373 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28485.685373 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26859.329809 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26859.329809 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29527.346947 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29059.233508 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29527.346947 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34310.488986 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167132.912585 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166865.680751 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87312.779883 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87306.288381 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 23161545 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11911126 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 559932 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 559928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 4 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 858463 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10650090 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 19410 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 19410 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4372034 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7887876 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1202832 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 877539 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 29 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 412195 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 333118 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 458356 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1116808 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1095312 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6015187 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4685876 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 509592 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 452179 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18045125 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16655613 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 406321 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1179507 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 36286566 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 769908416 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 641765745 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1546392 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4442928 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1417663481 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4824103 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 76247568 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 17122714 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.052642 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.223318 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 15794619 87.66% 87.66% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2223701 12.34% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 341 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 16221347 94.74% 94.74% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 901363 5.26% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 4 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 18018661 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 22188055468 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 17122714 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 23027796506 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 182014003 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 160947650 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8566090793 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 9028759604 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7517136176 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7641863842 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 207825380 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 213393747 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 628033176 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 624968323 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40328 # Transaction distribution -system.iobus.trans_dist::ReadResp 40328 # Transaction distribution -system.iobus.trans_dist::WriteReq 136631 # Transaction distribution -system.iobus.trans_dist::WriteResp 136631 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47646 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40315 # Transaction distribution +system.iobus.trans_dist::ReadResp 40315 # Transaction distribution +system.iobus.trans_dist::WriteReq 136630 # Transaction distribution +system.iobus.trans_dist::WriteResp 136630 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47698 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -3022,15 +3015,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122580 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47666 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353890 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47718 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3041,19 +3034,19 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155687 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339048 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155710 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496821 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36938002 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496732 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36996503 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 332000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -3061,85 +3054,85 @@ system.iobus.reqLayer4.occupancy 10500 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 13500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24205503 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24232502 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36443500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36410001 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569408550 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568919799 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92680000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92681000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147954000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147926000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115626 # number of replacements -system.iocache.tags.tagsinuse 11.305309 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115610 # number of replacements +system.iocache.tags.tagsinuse 11.211324 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115642 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115626 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9115830406000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.413187 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.892123 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463324 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.243258 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706582 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9155814843000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.413268 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.798056 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463329 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.237379 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.700708 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041018 # Number of tag accesses -system.iocache.tags.data_accesses 1041018 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040892 # Number of tag accesses +system.iocache.tags.data_accesses 1040892 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8901 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8938 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115629 # number of demand (read+write) misses -system.iocache.demand_misses::total 115669 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115615 # number of demand (read+write) misses +system.iocache.demand_misses::total 115655 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115629 # number of overall misses -system.iocache.overall_misses::total 115669 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5198500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1667264523 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1672463023 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115615 # number of overall misses +system.iocache.overall_misses::total 115655 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1677259553 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1682459553 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12925157527 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12925157527 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5567500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14592422050 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14597989550 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5567500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14592422050 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14597989550 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12947566246 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12947566246 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14624825799 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14630394799 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14624825799 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14630394799 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8901 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8938 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115629 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115669 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115615 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115655 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115629 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115669 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115615 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115655 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3153,53 +3146,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140500 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 187312.046175 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 187118.261692 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 188731.805221 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 188531.998319 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121103.717178 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 121103.717178 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 126200.365393 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126204.856530 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 126200.365393 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126204.856530 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33241 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121313.678191 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 121313.678191 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 126495.920071 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126500.322502 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 126495.920071 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126500.322502 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33395 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3524 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.432747 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.557813 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106695 # number of writebacks -system.iocache.writebacks::total 106695 # number of writebacks +system.iocache.writebacks::writebacks 106693 # number of writebacks +system.iocache.writebacks::total 106693 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8901 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8938 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8887 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8924 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115629 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115669 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115615 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115655 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115629 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115669 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1222214523 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1225563023 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115615 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115655 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1232909553 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1236259553 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7580015931 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7580015931 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3567500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8802230454 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8805797954 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3567500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8802230454 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8805797954 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7602399187 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7602399187 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3569000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8835308740 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8838877740 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3569000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8835308740 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8838877740 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3213,664 +3206,665 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90500 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137312.046175 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 137118.261692 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138731.805221 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 138531.998319 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71021.811811 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71021.811811 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76124.765016 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76129.282297 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76124.765016 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76129.282297 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1557710 # number of replacements -system.l2c.tags.tagsinuse 63573.891854 # Cycle average of tags in use -system.l2c.tags.total_refs 6243665 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1617388 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.860338 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 3022937500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 21119.731437 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 317.083055 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 501.157048 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4189.705266 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 12756.928607 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 18825.078792 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 29.382680 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 33.853586 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2676.679680 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1884.367858 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1239.923843 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.322262 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004838 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.007647 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063930 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.194655 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.287248 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000448 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000517 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040843 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.028753 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.018920 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.970061 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11464 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 277 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 47937 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1377 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 337 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9749 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 272 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3074 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5518 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 38948 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.174927 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004227 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.731461 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 79574133 # Number of tag accesses -system.l2c.tags.data_accesses 79574133 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2888931 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2888931 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 180891 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 129539 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 310430 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43976 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 36797 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 80773 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55787 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 50048 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105835 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6797 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4576 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 551177 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 671308 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 325157 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6401 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4256 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 484948 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 535287 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 285618 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2875525 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 132882 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 123273 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 256155 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6797 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4576 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 551177 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 727095 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 325157 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6401 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4256 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 484948 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 585335 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 285618 # number of demand (read+write) hits -system.l2c.demand_hits::total 2981360 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6797 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4576 # number of overall hits -system.l2c.overall_hits::cpu0.inst 551177 # number of overall hits -system.l2c.overall_hits::cpu0.data 727095 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 325157 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6401 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4256 # number of overall hits -system.l2c.overall_hits::cpu1.inst 484948 # number of overall hits -system.l2c.overall_hits::cpu1.data 585335 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 285618 # number of overall hits -system.l2c.overall_hits::total 2981360 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 62870 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 65353 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 128223 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 13472 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 11956 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 25428 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 91907 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 48160 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140067 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3207 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3170 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 61507 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 173115 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 339604 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1937 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1306 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 48662 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 111561 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 193805 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 937874 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 497642 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 96113 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 593755 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3207 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3170 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 61507 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 265022 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 339604 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1937 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1306 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 48662 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 159721 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 193805 # number of demand (read+write) misses -system.l2c.demand_misses::total 1077941 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3207 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3170 # number of overall misses -system.l2c.overall_misses::cpu0.inst 61507 # number of overall misses -system.l2c.overall_misses::cpu0.data 265022 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 339604 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1937 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1306 # number of overall misses -system.l2c.overall_misses::cpu1.inst 48662 # number of overall misses -system.l2c.overall_misses::cpu1.data 159721 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 193805 # number of overall misses -system.l2c.overall_misses::total 1077941 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 420802000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 429972500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 850774500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 88078000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 80352500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 168430500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8572942990 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4240159498 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 12813102488 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 292674000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 283861500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5444535999 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 16594648743 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 46635334107 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 183709500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 124471000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4269928000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 11202968996 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 26909035721 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 111941167566 # number of ReadSharedReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu0.data 55164500 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu1.data 62218500 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::total 117383000 # number of InvalidateReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 292674000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 283861500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 5444535999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 25167591733 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 46635334107 # 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number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 183709500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 124471000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4269928000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 15443128494 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 26909035721 # number of overall miss cycles -system.l2c.overall_miss_latency::total 124754270054 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 2888931 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2888931 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 243761 # 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number of demand (read+write) accesses -system.l2c.demand_accesses::total 4059301 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 10004 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7746 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 612684 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 992117 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 664761 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 8338 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5562 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 533610 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 745056 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 479423 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4059301 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.257917 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.335329 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.292311 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.234508 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.245236 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.239433 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.622280 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.490388 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.569605 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.320572 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.409243 # 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average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6579.231252 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6635.116165 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6537.856295 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6720.684175 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 6623.820198 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 93278.455286 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 88043.178945 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 91478.381689 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 91260.991581 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89546.214511 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 88518.965305 # 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average overall miss latency -system.l2c.overall_avg_miss_latency::total 115733.857469 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 7857 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71231.534246 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71231.534246 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.090300 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76424.518957 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.090300 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76424.518957 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1575605 # number of replacements +system.l2c.tags.tagsinuse 65208.311267 # Cycle average of tags in use +system.l2c.tags.total_refs 6750580 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1636875 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.124066 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 3024712500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 9648.504654 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 430.210636 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 509.722466 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4113.935017 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 22579.924066 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 21373.967512 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.667516 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 13.437669 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2580.265558 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2788.873436 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1154.802739 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.147224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006564 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.007778 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062774 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.344542 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.326141 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000205 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.039372 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.042555 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.017621 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995000 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10940 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 249 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50081 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 103 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 404 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10423 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 244 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2182 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3614 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 44004 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.166931 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003799 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.764175 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 76956529 # Number of tag accesses +system.l2c.tags.data_accesses 76956529 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2841841 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2841841 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 3 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 3 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 208782 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 171973 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 380755 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 54097 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 47819 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 101916 # 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number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2798653 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 134880 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 130480 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 265360 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 12794 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5104 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 534660 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 683464 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 294599 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 11629 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5041 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 480238 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 596154 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.401912 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.265748 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.210052 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.392670 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102354 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.272313 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.528211 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.113846 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.160253 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.093499 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.208036 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.401912 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.265748 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20007.215133 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20922.435798 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20480.106273 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24467.990066 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24337.044534 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24399.682682 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85540.175428 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80775.672510 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 83866.595921 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 79397.611466 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 87340.145476 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 78311.895891 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87513.582380 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112772.350532 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24895.958354 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20717.471769 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24117.700412 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 79397.611466 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86722.561889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 78311.895891 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85469.251788 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 109056.054139 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 79397.611466 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86722.561889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 78311.895891 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85469.251788 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 109056.054139 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167775.627329 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 95912.972007 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121759.442826 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162146.824876 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 149138.789590 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 122053.187311 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84328.526919 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 47094.992243 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74147.671970 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 4190264 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2528993 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3019 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 77125.713494 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77908.870645 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74383.639767 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3980803 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2353726 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3243 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 59861 # Transaction distribution -system.membus.trans_dist::ReadResp 1006452 # Transaction distribution -system.membus.trans_dist::WriteReq 38438 # Transaction distribution -system.membus.trans_dist::WriteResp 38438 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1336656 # Transaction distribution -system.membus.trans_dist::CleanEvict 266935 # Transaction distribution -system.membus.trans_dist::UpgradeReq 438975 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 302731 # Transaction distribution -system.membus.trans_dist::UpgradeResp 22 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 150471 # Transaction distribution -system.membus.trans_dist::ReadExResp 135365 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 946591 # Transaction distribution -system.membus.trans_dist::InvalidateReq 696687 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 59676 # Transaction distribution +system.membus.trans_dist::ReadResp 985495 # Transaction distribution +system.membus.trans_dist::WriteReq 38244 # Transaction distribution +system.membus.trans_dist::WriteResp 38244 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1315010 # Transaction distribution +system.membus.trans_dist::CleanEvict 256715 # Transaction distribution +system.membus.trans_dist::UpgradeReq 339680 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 271581 # Transaction distribution +system.membus.trans_dist::UpgradeResp 24 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 147332 # Transaction distribution +system.membus.trans_dist::ReadExResp 134542 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 925819 # Transaction distribution +system.membus.trans_dist::InvalidateReq 674453 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122580 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26078 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5027920 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5176654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238145 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238145 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5414799 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155687 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25318 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4797896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4945870 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237932 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237932 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5183802 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155710 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52156 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147706944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 147915343 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7266880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 155182223 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 597489 # Total snoops (count) -system.membus.snoopTraffic 179456 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2633759 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013061 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.113535 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50636 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144939472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 145146374 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7255040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7255040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 152401414 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 572055 # Total snoops (count) +system.membus.snoopTraffic 191360 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2456788 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015156 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.122173 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2599360 98.69% 98.69% # Request fanout histogram -system.membus.snoop_fanout::1 34399 1.31% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2419553 98.48% 98.48% # Request fanout histogram +system.membus.snoop_fanout::1 37235 1.52% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2633759 # Request fanout histogram -system.membus.reqLayer0.occupancy 98019495 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2456788 # Request fanout histogram +system.membus.reqLayer0.occupancy 98064494 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21931994 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21142497 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9377704107 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9055699898 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5794716587 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5680392120 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45616715 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45554532 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3913,83 +3907,83 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 12205642 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6628070 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1941255 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 157740 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 142803 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 14937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 59863 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4654836 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38438 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38438 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4118892 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2762121 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 740907 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 383504 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1124411 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 124 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298356 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298356 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4595571 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 881263 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 849910 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10458732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7383011 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17841743 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 265418110 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179948433 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 445366543 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3005080 # Total snoops (count) -system.toL2Bus.snoopTraffic 132103248 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 8556754 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.351410 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.481053 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 11893981 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6468498 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1904661 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 211231 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 193743 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 17488 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 59678 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4527289 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38244 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38244 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4050158 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2718586 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 717362 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 373497 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1090859 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 293033 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 293033 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4468431 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 869390 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 835427 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9945746 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7459601 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17405347 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 252717925 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 183230753 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 435948678 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2969827 # Total snoops (count) +system.toL2Bus.snoopTraffic 128627856 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 8396274 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.355668 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.483046 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5564766 65.03% 65.03% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2977051 34.79% 99.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 14937 0.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5427479 64.64% 64.64% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2951307 35.15% 99.79% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 17488 0.21% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8556754 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9506782087 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8396274 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9289434840 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2628899 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2606647 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4728944566 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4518737086 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3692981173 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3678115853 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 14084 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 5420 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 4835 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 13392 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |