diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt | 6345 |
1 files changed, 3175 insertions, 3170 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 6bf45e0f6..9055480cb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.309827 # Number of seconds simulated -sim_ticks 47309826639000 # Number of ticks simulated -final_tick 47309826639000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.309815 # Number of seconds simulated +sim_ticks 47309815475000 # Number of ticks simulated +final_tick 47309815475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115168 # Simulator instruction rate (inst/s) -host_op_rate 135435 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5759542779 # Simulator tick rate (ticks/s) -host_mem_usage 728780 # Number of bytes of host memory used -host_seconds 8214.16 # Real time elapsed on the host -sim_insts 946011818 # Number of instructions simulated -sim_ops 1112485532 # Number of ops (including micro ops) simulated +host_inst_rate 80227 # Simulator instruction rate (inst/s) +host_op_rate 94350 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4125416978 # Simulator tick rate (ticks/s) +host_mem_usage 770696 # Number of bytes of host memory used +host_seconds 11467.89 # Real time elapsed on the host +sim_insts 920033396 # Number of instructions simulated +sim_ops 1081995375 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 184448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 167936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 5084832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 44767048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 19339456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 176320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 161792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2535456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 18891728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 20722048 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 420544 # Number of bytes read from this memory -system.physmem.bytes_read::total 112451608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 5084832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2535456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7620288 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 93755328 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 174848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 152512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4545760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 43325128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 19040640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 136192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 127232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2550688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 17518992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 15564544 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 439744 # Number of bytes read from this memory +system.physmem.bytes_read::total 103576280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4545760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2550688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7096448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 86607680 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 93775912 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2624 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 95403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 699498 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 302179 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2755 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2528 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 39660 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 295196 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 323782 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6571 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1773078 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1464927 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 86628264 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2732 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 86980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 676968 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 297510 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2128 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 273747 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 243196 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6871 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1634401 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1353245 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1467501 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 107479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 946253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 408783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 399319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 438007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2376919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 107479 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 161072 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1981731 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1355819 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 96085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 915775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 402467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2689 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 370304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 328992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2189319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 96085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 149999 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1830649 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1982166 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1981731 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 107479 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 946688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 408783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 399319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 438007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4359084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1773078 # Number of read requests accepted -system.physmem.writeReqs 1467501 # Number of write requests accepted -system.physmem.readBursts 1773078 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1467501 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 113443520 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 33472 # Total number of bytes read from write queue -system.physmem.bytesWritten 93774528 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 112451608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 93775912 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 523 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1831084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1830649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 96085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 916210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 402467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2689 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 370304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 328992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4020403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1634401 # Number of read requests accepted +system.physmem.writeReqs 1355819 # Number of write requests accepted +system.physmem.readBursts 1634401 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1355819 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 104570688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 30976 # Total number of bytes read from write queue +system.physmem.bytesWritten 86627008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 103576280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 86628264 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 484 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 224875 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 113386 # Per bank write bursts -system.physmem.perBankRdBursts::1 120644 # Per bank write bursts -system.physmem.perBankRdBursts::2 108661 # Per bank write bursts -system.physmem.perBankRdBursts::3 115173 # Per bank write bursts -system.physmem.perBankRdBursts::4 103078 # Per bank write bursts -system.physmem.perBankRdBursts::5 114921 # Per bank write bursts -system.physmem.perBankRdBursts::6 108340 # Per bank write bursts -system.physmem.perBankRdBursts::7 105879 # Per bank write bursts -system.physmem.perBankRdBursts::8 98747 # Per bank write bursts -system.physmem.perBankRdBursts::9 127278 # Per bank write bursts -system.physmem.perBankRdBursts::10 99197 # Per bank write bursts -system.physmem.perBankRdBursts::11 111650 # Per bank write bursts -system.physmem.perBankRdBursts::12 107228 # Per bank write bursts -system.physmem.perBankRdBursts::13 113583 # Per bank write bursts -system.physmem.perBankRdBursts::14 112177 # Per bank write bursts -system.physmem.perBankRdBursts::15 112613 # Per bank write bursts -system.physmem.perBankWrBursts::0 94420 # Per bank write bursts -system.physmem.perBankWrBursts::1 97266 # Per bank write bursts -system.physmem.perBankWrBursts::2 90974 # Per bank write bursts -system.physmem.perBankWrBursts::3 94616 # Per bank write bursts -system.physmem.perBankWrBursts::4 87287 # Per bank write bursts -system.physmem.perBankWrBursts::5 94599 # Per bank write bursts -system.physmem.perBankWrBursts::6 89304 # Per bank write bursts -system.physmem.perBankWrBursts::7 90590 # Per bank write bursts -system.physmem.perBankWrBursts::8 84448 # Per bank write bursts -system.physmem.perBankWrBursts::9 90113 # Per bank write bursts -system.physmem.perBankWrBursts::10 85465 # Per bank write bursts -system.physmem.perBankWrBursts::11 93225 # Per bank write bursts -system.physmem.perBankWrBursts::12 88655 # Per bank write bursts -system.physmem.perBankWrBursts::13 95246 # Per bank write bursts -system.physmem.perBankWrBursts::14 93025 # Per bank write bursts -system.physmem.perBankWrBursts::15 95994 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 224542 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 101664 # Per bank write bursts +system.physmem.perBankRdBursts::1 108898 # Per bank write bursts +system.physmem.perBankRdBursts::2 93497 # Per bank write bursts +system.physmem.perBankRdBursts::3 100406 # Per bank write bursts +system.physmem.perBankRdBursts::4 99202 # Per bank write bursts +system.physmem.perBankRdBursts::5 111502 # Per bank write bursts +system.physmem.perBankRdBursts::6 102695 # Per bank write bursts +system.physmem.perBankRdBursts::7 105017 # Per bank write bursts +system.physmem.perBankRdBursts::8 95660 # Per bank write bursts +system.physmem.perBankRdBursts::9 119055 # Per bank write bursts +system.physmem.perBankRdBursts::10 95976 # Per bank write bursts +system.physmem.perBankRdBursts::11 99461 # Per bank write bursts +system.physmem.perBankRdBursts::12 97685 # Per bank write bursts +system.physmem.perBankRdBursts::13 98791 # Per bank write bursts +system.physmem.perBankRdBursts::14 102404 # Per bank write bursts +system.physmem.perBankRdBursts::15 102004 # Per bank write bursts +system.physmem.perBankWrBursts::0 83138 # Per bank write bursts +system.physmem.perBankWrBursts::1 88505 # Per bank write bursts +system.physmem.perBankWrBursts::2 79517 # Per bank write bursts +system.physmem.perBankWrBursts::3 83751 # Per bank write bursts +system.physmem.perBankWrBursts::4 82730 # Per bank write bursts +system.physmem.perBankWrBursts::5 91993 # Per bank write bursts +system.physmem.perBankWrBursts::6 85763 # Per bank write bursts +system.physmem.perBankWrBursts::7 87476 # Per bank write bursts +system.physmem.perBankWrBursts::8 80354 # Per bank write bursts +system.physmem.perBankWrBursts::9 84626 # Per bank write bursts +system.physmem.perBankWrBursts::10 82451 # Per bank write bursts +system.physmem.perBankWrBursts::11 83951 # Per bank write bursts +system.physmem.perBankWrBursts::12 82076 # Per bank write bursts +system.physmem.perBankWrBursts::13 85332 # Per bank write bursts +system.physmem.perBankWrBursts::14 85178 # Per bank write bursts +system.physmem.perBankWrBursts::15 86706 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 83 # Number of times write queue was full causing retry -system.physmem.totGap 47309825190500 # Total gap between requests +system.physmem.numWrRetry 54 # Number of times write queue was full causing retry +system.physmem.totGap 47309813973500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1751720 # Read request sizes (log2) +system.physmem.readPktSize::6 1613043 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1464927 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 608524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 449703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 194607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 195607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 116312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 71048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 40112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 36551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 32712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 10303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 5634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 3467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1353245 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 578892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 412924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 179105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 178845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 107013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 63608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 8546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -188,170 +188,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 20153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 23447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 36691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 53186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 72210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 82749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 88726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 95528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 97547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 101638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 103246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 108748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 123417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 115282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 109625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 98032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 19221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 22339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 41881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 50025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 77253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 82334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 88348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 89969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 94025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 94875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 99373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 112446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 104983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 99994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 89665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 136 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 281 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1119709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 185.063798 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 114.156365 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.940793 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 674939 60.28% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 219039 19.56% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 70659 6.31% 86.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 37987 3.39% 89.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 28223 2.52% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 14545 1.30% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 15798 1.41% 94.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9595 0.86% 95.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 48924 4.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1119709 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 84177 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.057367 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 250.150754 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 84175 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::61 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 146 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1028414 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 185.914855 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 114.442896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 243.413322 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 618503 60.14% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 202037 19.65% 79.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 65034 6.32% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35244 3.43% 89.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24806 2.41% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13355 1.30% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14362 1.40% 94.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8867 0.86% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 46206 4.49% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1028414 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 77347 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.124284 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 260.957500 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 77345 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::69632-73727 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 84177 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 84177 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.406501 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.998569 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.063432 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 78913 93.75% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2654 3.15% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 594 0.71% 97.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 256 0.30% 97.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 356 0.42% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 499 0.59% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 111 0.13% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 36 0.04% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 47 0.06% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 28 0.03% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 36 0.04% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 26 0.03% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 418 0.50% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 37 0.04% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 46 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 46 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 12 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 77347 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 77347 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.499670 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.056595 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.288618 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 72278 93.45% 93.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2489 3.22% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 567 0.73% 97.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 275 0.36% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 300 0.39% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 491 0.63% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 126 0.16% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 49 0.06% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 40 0.05% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 44 0.06% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 35 0.05% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 27 0.03% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 405 0.52% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 43 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 50 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 52 0.07% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 16 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 25 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 23 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 84177 # Writes before turning the bus around for reads -system.physmem.totQLat 95142418476 # Total ticks spent queuing -system.physmem.totMemAccLat 128377824726 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8862775000 # Total ticks spent in databus transfers -system.physmem.avgQLat 53675.30 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::148-151 8 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 77347 # Writes before turning the bus around for reads +system.physmem.totQLat 84737173288 # Total ticks spent queuing +system.physmem.totMemAccLat 115373117038 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8169585000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51861.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 72425.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.98 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 70611.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.21 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing -system.physmem.readRowHits 1427545 # Number of row buffer hits during reads -system.physmem.writeRowHits 690525 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.13 # Row buffer hit rate for writes -system.physmem.avgGap 14599188.97 # Average gap between requests -system.physmem.pageHitRate 65.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4299372000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2345887500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6942631800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4789082880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3090047684880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1174100419575 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27355981545000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31638506623635 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.751312 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45508743621503 # Time in different power states -system.physmem_0.memoryStateTime::REF 1579778980000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.70 # Average write queue length when enqueuing +system.physmem.readRowHits 1319893 # Number of row buffer hits during reads +system.physmem.writeRowHits 639153 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.22 # Row buffer hit rate for writes +system.physmem.avgGap 15821516.13 # Average gap between requests +system.physmem.pageHitRate 65.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3982161960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2172806625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6418448400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4425017040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3090046667760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1165891095180 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27363173363250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31636109560215 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.700864 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45520771842112 # Time in different power states +system.physmem_0.memoryStateTime::REF 1579778460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 221302763997 # Time in different power states +system.physmem_0.memoryStateTime::ACT 209258446888 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4165628040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2272912125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6883242600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4705588080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3090047684880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1168667714520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27360747075750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31637489845995 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.729820 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45516677078545 # Time in different power states -system.physmem_1.memoryStateTime::REF 1579778980000 # Time in different power states +system.physmem_1.actEnergy 3792625200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2069388750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6326026200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4345967520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3090046667760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1161508413915 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27367017820500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31635106909845 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.679671 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45527169156111 # Time in different power states +system.physmem_1.memoryStateTime::REF 1579778460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 213370138955 # Time in different power states +system.physmem_1.memoryStateTime::ACT 202865647889 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -385,15 +378,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 147637418 # Number of BP lookups -system.cpu0.branchPred.condPredicted 98315773 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7247820 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 103619610 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 67413734 # Number of BTB hits +system.cpu0.branchPred.lookups 147707110 # Number of BP lookups +system.cpu0.branchPred.condPredicted 98263896 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7114286 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 103765470 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 67713845 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.058857 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 20080737 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 195189 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.256626 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20037326 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 200169 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -424,84 +417,90 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 596316 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 596316 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13005 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90766 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 267964 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 328352 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 1967.306427 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 12140.663837 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 326191 99.34% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1511 0.46% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 485 0.15% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 70 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 71 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 17 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 575296 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 575296 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12884 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88904 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 257665 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 317631 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2022.074357 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 12176.572384 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 315561 99.35% 99.35% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1443 0.45% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 466 0.15% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 74 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 64 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 16 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 328352 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 293288 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 18414.921511 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 15494.626324 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16461.439983 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 290000 98.88% 98.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2364 0.81% 99.68% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 368 0.13% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 346 0.12% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 119 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 72 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 12 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 293288 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 554812439744 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.594659 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.537153 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 553701545244 99.80% 99.80% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 589103000 0.11% 99.91% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 238633000 0.04% 99.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 116174000 0.02% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 85227000 0.02% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 46829500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 15433000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 19112000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 363500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 19500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 554812439744 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 90767 87.47% 87.47% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 13005 12.53% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 103772 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 596316 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 317631 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 284896 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 18154.968831 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15325.984047 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16062.585690 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 269179 94.48% 94.48% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 12793 4.49% 98.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1124 0.39% 99.37% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 999 0.35% 99.72% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 121 0.04% 99.76% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 154 0.05% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 275 0.10% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 60 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 49 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 59 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 25 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 23 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 18 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::491520-524287 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 284896 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 550505269948 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.606717 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.533946 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 549425097448 99.80% 99.80% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 576911000 0.10% 99.91% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 232215500 0.04% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 109337500 0.02% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 81684000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 43624500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 15920500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 20013500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 440500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 25500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 550505269948 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 88905 87.34% 87.34% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 12884 12.66% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 101789 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 575296 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 596316 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 103772 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 575296 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101789 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 103772 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 700088 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101789 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 677085 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 107674804 # DTB read hits -system.cpu0.dtb.read_misses 416109 # DTB read misses -system.cpu0.dtb.write_hits 89240851 # DTB write hits -system.cpu0.dtb.write_misses 180207 # DTB write misses -system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 107498760 # DTB read hits +system.cpu0.dtb.read_misses 398450 # DTB read misses +system.cpu0.dtb.write_hits 89911233 # DTB write hits +system.cpu0.dtb.write_misses 176846 # DTB write misses +system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37572 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 168 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7516 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36343 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 6513 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 38101 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 108090913 # DTB read accesses -system.cpu0.dtb.write_accesses 89421058 # DTB write accesses +system.cpu0.dtb.perms_faults 39209 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 107897210 # DTB read accesses +system.cpu0.dtb.write_accesses 90088079 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 196915655 # DTB hits -system.cpu0.dtb.misses 596316 # DTB misses -system.cpu0.dtb.accesses 197511971 # DTB accesses +system.cpu0.dtb.hits 197409993 # DTB hits +system.cpu0.dtb.misses 575296 # DTB misses +system.cpu0.dtb.accesses 197985289 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -531,326 +530,332 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 85428 # Table walker walks requested -system.cpu0.itb.walker.walksLong 85428 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 771 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61190 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10178 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 75250 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1283.993355 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 9203.446829 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 74460 98.95% 98.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 428 0.57% 99.52% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 166 0.22% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 158 0.21% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 10 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 75250 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 72139 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 23671.051720 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 20466.529400 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 20605.197168 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 70248 97.38% 97.38% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1514 2.10% 99.48% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 196 0.27% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 111 0.15% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 47 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 72139 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 421639244068 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.834946 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.371382 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 69614918048 16.51% 16.51% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 352004823020 83.48% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 17379000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 2056500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 67500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 421639244068 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 61190 98.76% 98.76% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 771 1.24% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 61961 # Table walker page sizes translated +system.cpu0.itb.walker.walks 88373 # Table walker walks requested +system.cpu0.itb.walker.walksLong 88373 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1010 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63733 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10354 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 78019 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1154.635409 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 8302.318133 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 77325 99.11% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 373 0.48% 99.59% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 149 0.19% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 144 0.18% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 7 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 78019 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 75097 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 22974.939079 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 20231.234781 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18518.097642 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 68416 91.10% 91.10% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 5120 6.82% 97.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 490 0.65% 98.57% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 809 1.08% 99.65% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 63 0.08% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 55 0.07% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 56 0.07% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 27 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 16 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 17 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 75097 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 413042823976 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.838558 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.368059 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 66699023100 16.15% 16.15% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 346328877376 83.85% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 13315500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1543000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 65000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 413042823976 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 63733 98.44% 98.44% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1010 1.56% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64743 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85428 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85428 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88373 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88373 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61961 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61961 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 147389 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 231535487 # ITB inst hits -system.cpu0.itb.inst_misses 85428 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64743 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64743 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 153116 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 231997623 # ITB inst hits +system.cpu0.itb.inst_misses 88373 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26943 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26272 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 216195 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 223051 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 231620915 # ITB inst accesses -system.cpu0.itb.hits 231535487 # DTB hits -system.cpu0.itb.misses 85428 # DTB misses -system.cpu0.itb.accesses 231620915 # DTB accesses -system.cpu0.numCycles 805724204 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 232085996 # ITB inst accesses +system.cpu0.itb.hits 231997623 # DTB hits +system.cpu0.itb.misses 88373 # DTB misses +system.cpu0.itb.accesses 232085996 # DTB accesses +system.cpu0.numCycles 807086065 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 95731684 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 652075833 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 147637418 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 87494471 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 667504198 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 15546378 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1866411 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 305738 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6228904 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 744813 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 860245 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 231319013 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1833472 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 28917 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 781015182 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.979576 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.220669 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 93861008 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 652896475 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 147707110 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 87751171 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 672171434 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15342460 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1905506 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 292447 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6425780 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 696882 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 817665 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 231773404 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1782410 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 29765 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 783841952 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.977378 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.220143 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 414945915 53.13% 53.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 142136658 18.20% 71.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 48870776 6.26% 77.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 175061833 22.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 417241550 53.23% 53.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 142387565 18.17% 71.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 48916006 6.24% 77.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 175296831 22.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 781015182 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.183236 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.809304 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 113248081 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 377378437 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 245811555 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 39067395 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5509714 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 21219272 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2308032 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 677494422 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 25172258 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5509714 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 150635102 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 57564950 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 243777898 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 246916319 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 76611199 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 659282826 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6463914 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 10193503 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 302591 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 345572 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 40114273 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11761 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 627680154 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1013922393 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 779757811 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 794183 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 565536193 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 62143943 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16063927 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14023847 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 79290060 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 107984972 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 92881396 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9789553 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8248701 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 636103677 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16216212 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 639991449 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2906968 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 58559234 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 38038909 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 288402 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 781015182 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.819435 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.071222 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 783841952 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.183013 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.808955 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 111750908 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 381172853 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 246402586 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 39053255 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5462350 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 21288781 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2252861 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 678905918 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 24756446 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5462350 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 148938841 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 55630896 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 250198036 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 247704695 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 75907134 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 660737654 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6369939 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 10029778 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 264844 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 301380 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 39545548 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11804 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 629064095 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1015658028 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 780465434 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 875541 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 567964584 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 61099508 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16110257 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14023115 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 79266160 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 107669777 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 93504359 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9663954 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8219387 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 637670623 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16186083 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 641968825 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2865871 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 57572234 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 37073972 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 286236 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 783841952 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.819003 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.071442 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 434056489 55.58% 55.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 142602713 18.26% 73.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 124298977 15.92% 89.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 71442121 9.15% 98.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8609991 1.10% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 4891 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 436124999 55.64% 55.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 142425457 18.17% 73.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 124936152 15.94% 89.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 71756087 9.15% 98.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8593482 1.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5775 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 781015182 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 783841952 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 67040735 45.54% 45.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 53703 0.04% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 26002 0.02% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 14 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 38206404 25.96% 71.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 41875543 28.45% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 67185359 45.52% 45.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 54880 0.04% 45.56% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 27644 0.02% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 23 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 37910313 25.69% 71.26% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 42413379 28.74% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 436779538 68.25% 68.25% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1517289 0.24% 68.48% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 81855 0.01% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 5 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 23 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 47604 0.01% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 110932479 17.33% 85.84% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 90632632 14.16% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 438393066 68.29% 68.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1458143 0.23% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 76119 0.01% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 8 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 85008 0.01% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.54% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 110671978 17.24% 85.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 91284446 14.22% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 639991449 # Type of FU issued -system.cpu0.iq.rate 0.794306 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 147202401 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.230007 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2209837146 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 710527601 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 621905864 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1270303 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 504170 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 467307 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 786402566 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 791283 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2962367 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 641968825 # Type of FU issued +system.cpu0.iq.rate 0.795416 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 147591598 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.229905 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2216794106 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 710999195 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 623995458 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1442965 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 583548 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 537913 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 788669354 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 891059 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2946784 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 13371443 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 16751 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 153989 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 6295959 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13030035 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 16500 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 154978 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6224286 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2934112 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4671160 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2912970 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4614756 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5509714 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7058035 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 5778589 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 652441938 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5462350 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6648440 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 5673367 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 653983600 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 107984972 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 92881396 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13772451 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 68630 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5639093 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 153989 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2201982 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3098287 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5300269 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 631633854 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 107665614 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7773689 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 107669777 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 93504359 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13738155 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 65760 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5541873 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 154978 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2183890 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3035421 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5219311 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 633716914 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 107489609 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7688831 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 122049 # number of nop insts executed -system.cpu0.iew.exec_refs 196907522 # number of memory reference insts executed -system.cpu0.iew.exec_branches 119104624 # Number of branches executed -system.cpu0.iew.exec_stores 89241908 # Number of stores executed -system.cpu0.iew.exec_rate 0.783933 # Inst execution rate -system.cpu0.iew.wb_sent 623170550 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 622373171 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 301982038 # num instructions producing a value -system.cpu0.iew.wb_consumers 495557723 # num instructions consuming a value +system.cpu0.iew.exec_nop 126894 # number of nop insts executed +system.cpu0.iew.exec_refs 197402015 # number of memory reference insts executed +system.cpu0.iew.exec_branches 119462239 # Number of branches executed +system.cpu0.iew.exec_stores 89912406 # Number of stores executed +system.cpu0.iew.exec_rate 0.785191 # Inst execution rate +system.cpu0.iew.wb_sent 625355277 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 624533371 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 303033924 # num instructions producing a value +system.cpu0.iew.wb_consumers 497197749 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.772439 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609378 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.773813 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609484 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 51133197 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15927810 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4984345 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 771348242 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.769770 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.572751 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 50242588 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15899847 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4905406 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 774311548 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.770083 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.572660 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 513096769 66.52% 66.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 132148168 17.13% 83.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 58179832 7.54% 91.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 19360594 2.51% 93.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 14004722 1.82% 95.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9477117 1.23% 96.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6473381 0.84% 97.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3935015 0.51% 98.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14672644 1.90% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 515220918 66.54% 66.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 132191074 17.07% 83.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 58451829 7.55% 91.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 19702970 2.54% 93.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 14118724 1.82% 95.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9514083 1.23% 96.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6460440 0.83% 97.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3939203 0.51% 98.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14712307 1.90% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 771348242 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 504955538 # Number of instructions committed -system.cpu0.commit.committedOps 593760630 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 774311548 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 507069048 # Number of instructions committed +system.cpu0.commit.committedOps 596284470 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 181198957 # Number of memory references committed -system.cpu0.commit.loads 94613526 # Number of loads committed -system.cpu0.commit.membars 4060839 # Number of memory barriers committed -system.cpu0.commit.branches 113014510 # Number of branches committed -system.cpu0.commit.fp_insts 458000 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 545152087 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14971844 # Number of function calls committed. +system.cpu0.commit.refs 181919815 # Number of memory references committed +system.cpu0.commit.loads 94639742 # Number of loads committed +system.cpu0.commit.membars 4012038 # Number of memory barriers committed +system.cpu0.commit.branches 113466884 # Number of branches committed +system.cpu0.commit.fp_insts 524978 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 547272509 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14945710 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 411193864 69.25% 69.25% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1260833 0.21% 69.46% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 65173 0.01% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 413008446 69.26% 69.26% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1219700 0.20% 69.47% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 60724 0.01% 69.48% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.48% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.48% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.48% # Class of committed instruction @@ -873,818 +878,821 @@ system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.48% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.48% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 41761 0.01% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 94613526 15.93% 85.42% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 86585431 14.58% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 75743 0.01% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 94639742 15.87% 85.36% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 87280073 14.64% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 593760630 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14672644 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1397369391 # The number of ROB reads -system.cpu0.rob.rob_writes 1299419087 # The number of ROB writes -system.cpu0.timesIdled 1071653 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24709022 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93813929115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 504955538 # Number of Instructions Simulated -system.cpu0.committedOps 593760630 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.595634 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.595634 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.626710 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.626710 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 746722296 # number of integer regfile reads -system.cpu0.int_regfile_writes 443322911 # number of integer regfile writes -system.cpu0.fp_regfile_reads 778801 # number of floating regfile reads -system.cpu0.fp_regfile_writes 335108 # number of floating regfile writes -system.cpu0.cc_regfile_reads 136612374 # number of cc regfile reads -system.cpu0.cc_regfile_writes 137527114 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1389482326 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16167899 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6374252 # number of replacements -system.cpu0.dcache.tags.tagsinuse 504.525126 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 168612051 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6374762 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.449937 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 596284470 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14712307 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1401646047 # The number of ROB reads +system.cpu0.rob.rob_writes 1302545204 # The number of ROB writes +system.cpu0.timesIdled 1046717 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 23244113 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93812546108 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 507069048 # Number of Instructions Simulated +system.cpu0.committedOps 596284470 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.591669 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.591669 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.628271 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.628271 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 748239233 # number of integer regfile reads +system.cpu0.int_regfile_writes 444460602 # number of integer regfile writes +system.cpu0.fp_regfile_reads 860614 # number of floating regfile reads +system.cpu0.fp_regfile_writes 470540 # number of floating regfile writes +system.cpu0.cc_regfile_reads 137535879 # number of cc regfile reads +system.cpu0.cc_regfile_writes 138377705 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1393834331 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16112974 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6187008 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.050028 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 169602823 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6187519 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.410473 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1887138000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 504.525126 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.985401 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.985401 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.050028 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986426 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986426 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 375986188 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 375986188 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 87724319 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 87724319 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 75477797 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 75477797 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 231729 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 231729 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 266468 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 266468 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2022541 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2022541 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2052696 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2052696 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 163202116 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 163202116 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 163433845 # number of overall hits -system.cpu0.dcache.overall_hits::total 163433845 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7197565 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7197565 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7724152 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7724152 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 724383 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 724383 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 844788 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 844788 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 278463 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 278463 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 208196 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 208196 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 14921717 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 14921717 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15646100 # number of overall misses -system.cpu0.dcache.overall_misses::total 15646100 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 108620779500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 108620779500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 138974834179 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 138974834179 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 74732911806 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 74732911806 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4099802000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4099802000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4408839000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4408839000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3050500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3050500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 247595613679 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 247595613679 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 247595613679 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 247595613679 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 94921884 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 94921884 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 83201949 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 83201949 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 956112 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 956112 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1111256 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1111256 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2301004 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2301004 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2260892 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2260892 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 178123833 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 178123833 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 179079945 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 179079945 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075826 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.075826 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.092836 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.092836 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.757634 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.757634 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760210 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760210 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.121018 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.121018 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092086 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092086 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.083772 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.083772 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087369 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.087369 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15091.323177 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15091.323177 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17992.244868 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17992.244868 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 88463.510142 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 88463.510142 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14722.968581 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14722.968581 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21176.386674 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21176.386674 # average StoreCondReq miss latency +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 376921548 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 376921548 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 87937173 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 87937173 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 76339825 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 76339825 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228046 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 228046 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 267132 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 267132 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1986809 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1986809 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2024617 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2024617 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 164276998 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 164276998 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 164505044 # number of overall hits +system.cpu0.dcache.overall_hits::total 164505044 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6895567 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6895567 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7624089 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7624089 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 725854 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 725854 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 804065 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 804065 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 277240 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 277240 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200055 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 200055 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 14519656 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 14519656 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 15245510 # number of overall misses +system.cpu0.dcache.overall_misses::total 15245510 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 102037717000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 102037717000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 136358862160 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 136358862160 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 72398693034 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 72398693034 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4092900000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4092900000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4230014500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4230014500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5283500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5283500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 238396579160 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 238396579160 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 238396579160 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 238396579160 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 94832740 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 94832740 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 83963914 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 83963914 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 953900 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 953900 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1071197 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1071197 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2264049 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2264049 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2224672 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2224672 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 178796654 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 178796654 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 179750554 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 179750554 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.072713 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.072713 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.090802 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.090802 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760933 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760933 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.750623 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.750623 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.122453 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.122453 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089926 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089926 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081208 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.081208 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.084815 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.084815 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14797.581838 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14797.581838 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17885.266313 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17885.266313 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 90040.846243 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 90040.846243 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14763.021209 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14763.021209 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21144.257829 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21144.257829 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16592.970747 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16592.970747 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15824.749534 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15824.749534 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 23148520 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 20510394 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 766944 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 746852 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 30.182803 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 27.462461 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16418.886175 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16418.886175 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15637.166560 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15637.166560 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 22487796 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 20190626 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 731543 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 741822 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 30.740224 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 27.217616 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4317679 # number of writebacks -system.cpu0.dcache.writebacks::total 4317679 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3700903 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3700903 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6185217 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6185217 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 5102 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 5102 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 141775 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 141775 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9886120 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9886120 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9886120 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9886120 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3496662 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3496662 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1538935 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1538935 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 717217 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 717217 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 839686 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 839686 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 136688 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136688 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 208181 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 208181 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5035597 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5035597 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5752814 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5752814 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21352 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21352 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 23308 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 23308 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 44660 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 44660 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50025996500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50025996500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29968345030 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29968345030 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17752964500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17752964500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 73677446306 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 73677446306 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1889285500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1889285500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4200723000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4200723000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2985500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2985500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 79994341530 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 79994341530 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 97747306030 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 97747306030 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3896297500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3896297500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4053651000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4053651000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7949948500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7949948500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036837 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036837 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018496 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018496 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750139 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.750139 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.755619 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.755619 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059404 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059404 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092079 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092079 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028270 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028270 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032124 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032124 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14306.786444 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14306.786444 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19473.431321 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19473.431321 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24752.570700 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24752.570700 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87744.045162 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87744.045162 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13821.882682 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13821.882682 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20178.224718 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20178.224718 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 4210788 # number of writebacks +system.cpu0.dcache.writebacks::total 4210788 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3513002 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3513002 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6114706 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6114706 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4602 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4602 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 143782 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 143782 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9627708 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9627708 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9627708 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9627708 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3382565 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3382565 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1509383 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1509383 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 718663 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 718663 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 799463 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 799463 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 133458 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 133458 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200041 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 200041 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4891948 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4891948 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5610611 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5610611 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32342 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32342 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31823 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31823 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64165 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64165 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48415097500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48415097500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29340240291 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29340240291 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16426692500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16426692500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 71393732534 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 71393732534 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1844525500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1844525500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4030091500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4030091500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5165500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5165500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 77755337791 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 77755337791 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94182030291 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 94182030291 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5817539000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5817539000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5518707000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5518707000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11336246000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11336246000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035669 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035669 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017977 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017977 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753394 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.753394 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746327 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746327 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058947 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058947 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089919 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089919 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027360 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027360 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031213 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031213 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14313.131455 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14313.131455 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19438.565487 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19438.565487 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22857.295422 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22857.295422 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 89302.109709 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 89302.109709 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13821.018598 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13821.018598 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20146.327503 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20146.327503 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15885.771147 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15885.771147 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16991.216130 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16991.216130 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182479.275946 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182479.275946 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173916.723872 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173916.723872 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 178010.490372 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178010.490372 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15894.555255 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15894.555255 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16786.412441 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16786.412441 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179875.672500 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179875.672500 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173418.816579 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173418.816579 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 176673.357750 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176673.357750 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6538162 # number of replacements +system.cpu0.icache.tags.replacements 6407339 # number of replacements system.cpu0.icache.tags.tagsinuse 511.955601 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 224372588 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6538674 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.314693 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 224970066 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6407851 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.108505 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 17322639000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.955601 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999913 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999913 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 309 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 330 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 469120906 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 469120906 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 224372588 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 224372588 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 224372588 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 224372588 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 224372588 # number of overall hits -system.cpu0.icache.overall_hits::total 224372588 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6918516 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6918516 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6918516 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6918516 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6918516 # number of overall misses -system.cpu0.icache.overall_misses::total 6918516 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 73530599413 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 73530599413 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 73530599413 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 73530599413 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 73530599413 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 73530599413 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 231291104 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 231291104 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 231291104 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 231291104 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 231291104 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 231291104 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029913 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029913 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029913 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029913 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029913 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029913 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10628.088366 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10628.088366 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10628.088366 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10628.088366 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10628.088366 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10628.088366 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10842770 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 750 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 802318 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.514305 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 75 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 469899085 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 469899085 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 224970066 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 224970066 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 224970066 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 224970066 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 224970066 # number of overall hits +system.cpu0.icache.overall_hits::total 224970066 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6775541 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6775541 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6775541 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6775541 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6775541 # number of overall misses +system.cpu0.icache.overall_misses::total 6775541 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71079582898 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 71079582898 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 71079582898 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 71079582898 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 71079582898 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 71079582898 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 231745607 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 231745607 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 231745607 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 231745607 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 231745607 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 231745607 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029237 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029237 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029237 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029237 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029237 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029237 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10490.613650 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10490.613650 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10490.613650 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10490.613650 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10490.613650 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10490.613650 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 10215206 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 732 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 767906 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.302678 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 81.333333 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 379817 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 379817 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 379817 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 379817 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 379817 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 379817 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6538699 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6538699 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6538699 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6538699 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6538699 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6538699 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 367670 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 367670 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 367670 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 367670 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 367670 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 367670 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6407871 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6407871 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6407871 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6407871 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6407871 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6407871 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 66562536735 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 66562536735 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 66562536735 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 66562536735 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 66562536735 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 66562536735 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64388034562 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 64388034562 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64388034562 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 64388034562 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64388034562 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 64388034562 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1863746498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1863746498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028270 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028270 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028270 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028270 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028270 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028270 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10179.782971 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10179.782971 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10179.782971 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10179.782971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10179.782971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10179.782971 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027650 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027650 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027650 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10048.272595 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10048.272595 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10048.272595 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87524.490373 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87524.490373 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8420678 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8427841 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 6477 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8228747 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8235731 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 6331 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1085415 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2879166 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16210.435264 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 21867253 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2894850 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.553847 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1065389 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2775717 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16223.891094 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 21402394 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2791423 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 7.667198 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 16000650500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7399.715112 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 85.098490 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 94.687899 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4348.179928 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3389.288950 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 893.464886 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.451643 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005194 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005779 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.265392 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.206866 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054533 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989406 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1404 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14188 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 100 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 251 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 619 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 434 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 68 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 213 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 757 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4744 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4803 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3671 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.085693 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.865967 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 440722520 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 440722520 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 580486 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 180915 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 761401 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 4317669 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 4317669 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 115526 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 115526 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36643 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 36643 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 998559 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 998559 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5850201 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5850201 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3218899 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 3218899 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 227084 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 227084 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 580486 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 180915 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5850201 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4217458 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10829060 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 580486 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 180915 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5850201 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4217458 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10829060 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13187 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9856 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 23043 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 5 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 5 # number of Writeback misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 140809 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 140809 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 171530 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 171530 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 296756 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 296756 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 688482 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 688482 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1127441 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1127441 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 611195 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 611195 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13187 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9856 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 688482 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1424197 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2135722 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13187 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9856 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 688482 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1424197 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2135722 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 534558500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 449764500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 984323000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3072018500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 3072018500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3550746499 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3550746499 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2885498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2885498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16106273500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 16106273500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 21873259998 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 21873259998 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 41772472980 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 41772472980 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 70023878999 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 70023878999 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 534558500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 449764500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 21873259998 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 57878746480 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 80736329478 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 534558500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 449764500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 21873259998 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 57878746480 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 80736329478 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 593673 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 190771 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 784444 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 4317674 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 4317674 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 256335 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 256335 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 208173 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 208173 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1295315 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1295315 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6538683 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 6538683 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4346340 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 4346340 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 838279 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 838279 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 593673 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 190771 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 6538683 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5641655 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 12964782 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 593673 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 190771 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 6538683 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5641655 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 12964782 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022213 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051664 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.029375 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.549316 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.549316 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.823978 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.823978 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 7115.603862 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 78.900810 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 84.351377 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4177.499611 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3867.898858 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 899.636576 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.434302 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004816 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005148 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.254974 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.236078 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054909 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.990228 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1370 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14231 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 95 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 230 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 633 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 79 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 777 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4691 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4874 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3670 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.083618 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.868591 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 429969971 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 429969971 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 556706 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 187543 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 744249 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 4210780 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 4210780 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 112692 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 112692 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36481 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 36481 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 982818 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 982818 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5746953 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 5746953 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3150457 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 3150457 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 210597 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 210597 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 556706 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 187543 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 5746953 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 4133275 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 10624477 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 556706 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 187543 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 5746953 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 4133275 # number of overall hits +system.cpu0.l2cache.overall_hits::total 10624477 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12834 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9490 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 22324 # number of ReadReq misses +system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses +system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 137568 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 137568 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 163550 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 163550 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 10 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 289201 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 289201 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 660894 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 660894 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1080002 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1080002 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 587441 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 587441 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12834 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9490 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 660894 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1369203 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2052421 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12834 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9490 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 660894 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1369203 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2052421 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 512484500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 411800500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 924285000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2995269498 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2995269498 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3391228500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3391228500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4985998 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4985998 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15723716499 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 15723716499 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 20507752998 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 20507752998 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 39428872479 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 39428872479 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 67940497999 # number of InvalidateReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::total 67940497999 # number of InvalidateReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 512484500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 411800500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20507752998 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 55152588978 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 76584626976 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 512484500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 411800500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20507752998 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 55152588978 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 76584626976 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 569540 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 197033 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 766573 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 4210782 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 4210782 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 250260 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 250260 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200031 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 200031 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1272019 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1272019 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6407847 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 6407847 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4230459 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4230459 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 798038 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 798038 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 569540 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 197033 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 6407847 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5502478 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 12676898 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 569540 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 197033 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 6407847 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5502478 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 12676898 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022534 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048165 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.029122 # miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.549700 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.549700 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.817623 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.817623 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.229099 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.229099 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.105294 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.105294 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.259400 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.259400 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.729107 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.729107 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022213 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051664 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.105294 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.252443 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.164733 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022213 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051664 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.105294 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.252443 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.164733 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40536.778646 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 45633.573458 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 42716.790348 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21816.918663 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21816.918663 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20700.440150 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20700.440150 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 360687.250000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 360687.250000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54274.466228 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54274.466228 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 31770.271406 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 31770.271406 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37050.695318 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37050.695318 # average ReadSharedReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 114568.802099 # average InvalidateReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 114568.802099 # average InvalidateReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40536.778646 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 45633.573458 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31770.271406 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 40639.564948 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 37802.827090 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40536.778646 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 45633.573458 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31770.271406 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 40639.564948 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 37802.827090 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 1651 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.227356 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.227356 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.103138 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.103138 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.255292 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.255292 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.736107 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.736107 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022534 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048165 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.103138 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.248834 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.161902 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022534 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048165 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.103138 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.248834 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.161902 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 39931.782765 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 43393.097998 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 41403.198352 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21773.010424 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21773.010424 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20735.117701 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20735.117701 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 498599.800000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 498599.800000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54369.509438 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54369.509438 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 31030.321047 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 31030.321047 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 36508.147651 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 36508.147651 # average ReadSharedReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 115655.015566 # average InvalidateReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 115655.015566 # average InvalidateReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 39931.782765 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 43393.097998 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31030.321047 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 40280.797645 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 37314.287359 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 39931.782765 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 43393.097998 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31030.321047 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 40280.797645 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 37314.287359 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 1981 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 275.166667 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 152.384615 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1533538 # number of writebacks -system.cpu0.l2cache.writebacks::total 1533538 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 3 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 198 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 201 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 18639 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 18639 # number of ReadExReq MSHR hits +system.cpu0.l2cache.writebacks::writebacks 1508833 # number of writebacks +system.cpu0.l2cache.writebacks::total 1508833 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 7 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 199 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 206 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 18287 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 18287 # number of ReadExReq MSHR hits system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 9 # number of ReadCleanReq MSHR hits system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 6125 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 6125 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 3 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 198 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5427 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5427 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 6 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 7 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 199 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 24764 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 24974 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 3 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 198 # number of overall MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 23714 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 23929 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 7 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 199 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 24764 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 24974 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13184 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9658 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 22842 # number of ReadReq MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::writebacks 5 # number of Writeback MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::total 5 # number of Writeback MSHR misses -system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 117912 # number of CleanEvict MSHR misses -system.cpu0.l2cache.CleanEvict_mshr_misses::total 117912 # number of CleanEvict MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 787872 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 787872 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 140809 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 140809 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 171530 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 171530 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 278117 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 278117 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 688473 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 688473 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1121316 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1121316 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 611195 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::total 611195 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13184 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9658 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 688473 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1399433 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 2110748 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13184 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9658 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 688473 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1399433 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 787872 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2898620 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 23714 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 23929 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12827 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9291 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 22118 # number of ReadReq MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 112445 # number of CleanEvict MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::total 112445 # number of CleanEvict MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 792314 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 792314 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 137568 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 137568 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 163550 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 163550 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 10 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 270914 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 270914 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 660885 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 660885 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1074575 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1074575 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 587435 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 587435 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12827 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9291 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 660885 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1345489 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 2028492 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12827 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9291 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 660885 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1345489 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 792314 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2820806 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 21352 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 42646 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 23308 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 23308 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32342 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53636 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31823 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31823 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 44660 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 65954 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 455402500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 383158000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 838560500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 47401942947 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 47401942947 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2887874997 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2887874997 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2620767495 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2620767495 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2495498 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2495498 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11968940000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11968940000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 17742237498 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 17742237498 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34600470980 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34600470980 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 66356708999 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 66356708999 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 455402500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 383158000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17742237498 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 46569410980 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 65150208978 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 455402500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 383158000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17742237498 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 46569410980 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47401942947 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 112552151925 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 64165 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 85459 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 435391500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 348114500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 783506000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 46187185788 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 46187185788 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2827746492 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2827746492 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2511676494 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2511676494 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4277998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4277998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11675388499 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11675388499 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 16542258498 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 16542258498 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 32603545979 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 32603545979 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 64414833499 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 64414833499 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 435391500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 348114500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16542258498 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 44278934478 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 61604698976 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 435391500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 348114500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16542258498 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 44278934478 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 46187185788 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 107791884764 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1704040500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3725362000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5429402500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3873404967 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3873404967 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5558674000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7262714500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5274604967 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5274604967 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1704040500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7598766967 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9302807467 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022208 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.050626 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029119 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10833278967 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12537319467 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022522 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047155 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028853 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.549316 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.549316 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.823978 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.823978 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.549700 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.549700 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.817623 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.817623 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.214710 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.214710 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.105292 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.105292 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257991 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257991 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.729107 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.729107 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022208 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.050626 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.105292 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248054 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.162806 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022208 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.050626 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.105292 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248054 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212980 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212980 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.103137 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.103137 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254009 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254009 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.736099 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.736099 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022522 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047155 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.103137 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.244524 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.160015 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022522 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047155 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.103137 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.244524 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.223576 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 36711.343140 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60164.522850 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60164.522850 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20509.164876 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20509.164876 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15278.770448 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15278.770448 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311937.250000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311937.250000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43035.628890 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43035.628890 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 25770.418735 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 25770.418735 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30857.020661 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30857.020661 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108568.802099 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108568.802099 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25770.418735 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33277.342309 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30865.934246 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25770.418735 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33277.342309 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60164.522850 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38829.564388 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.222515 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35423.908129 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58294.042246 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58294.042246 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20555.263521 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20555.263521 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15357.239340 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15357.239340 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 427799.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 427799.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43096.290701 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43096.290701 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 25030.464450 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30340.875210 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30340.875210 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 109654.401762 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 109654.401762 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32909.176127 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30369.702703 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32909.176127 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58294.042246 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38213.150697 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174473.679281 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127313.288468 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166183.497812 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166183.497812 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171871.683879 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 135407.459542 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165748.199950 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165748.199950 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170147.043596 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 141049.935819 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168834.706881 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 146705.665489 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 984567 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11961948 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 972246 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11719640 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38204 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 23308 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 8463420 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 11561533 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1016095 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 502894 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 380729 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 540434 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 136 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1691199 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1306018 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6538699 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6804200 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 945007 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 838279 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19656927 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20547872 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414026 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1295337 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 41914162 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 418816352 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 645201790 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1526168 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4749384 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1070293694 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 11878703 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 38928585 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.320254 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.466574 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31823 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 8100286 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 11177309 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1018919 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 495790 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 366670 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 532232 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 139 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1670081 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1283370 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6407871 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6502663 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 904766 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 798038 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19264194 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20025393 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 428101 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1250579 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 40968267 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 410442912 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 629983858 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1576264 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4556320 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1046559354 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 11261603 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 37657626 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.313855 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.464058 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 26461563 67.97% 67.97% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 12467022 32.03% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 25838573 68.61% 68.61% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 11819053 31.39% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 38928585 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 18022605428 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 37657626 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 17602075916 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 218178978 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 231593980 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9834328997 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9637654372 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9151913574 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8931019988 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 223594319 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 231432265 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 702320680 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 681669728 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 127974219 # Number of BP lookups -system.cpu1.branchPred.condPredicted 85721226 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6122377 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 91131353 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 60172902 # Number of BTB hits +system.cpu1.branchPred.lookups 121094303 # Number of BP lookups +system.cpu1.branchPred.condPredicted 80706133 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6142160 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 84960891 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 56341743 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 66.028760 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17085083 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 181731 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 66.314915 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16429988 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 173246 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1714,89 +1722,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 610901 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 610901 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 15580 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 103695 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 293448 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 317453 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2113.928676 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 12461.929670 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-32767 312797 98.53% 98.53% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-65535 2424 0.76% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-98303 700 0.22% 99.52% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-131071 857 0.27% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-163839 351 0.11% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::163840-196607 153 0.05% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-229375 53 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::229376-262143 19 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-294911 21 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::294912-327679 57 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-360447 14 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 582230 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 582230 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 14388 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94420 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 278308 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 303922 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 1994.445943 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 12173.491739 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-32767 299685 98.61% 98.61% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-65535 2211 0.73% 99.33% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-98303 696 0.23% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-131071 740 0.24% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-163839 294 0.10% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::163840-196607 141 0.05% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-229375 47 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::229376-262143 22 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-294911 14 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::294912-327679 44 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-360447 15 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::360448-393215 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 317453 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 338102 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 18568.539967 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 16066.889111 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14911.003076 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 335377 99.19% 99.19% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1909 0.56% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 302 0.09% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 312 0.09% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 121 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 38 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 24 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::491520-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 303922 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 314895 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 18136.229537 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 15585.359240 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14753.917468 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 312363 99.20% 99.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1838 0.58% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 299 0.09% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 215 0.07% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 97 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 46 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 18 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 338102 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 438848021252 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.580073 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.553130 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 437543459752 99.70% 99.70% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 782991500 0.18% 99.88% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 243923500 0.06% 99.94% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 110155500 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 88476500 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 41634500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 16681500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 20049000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 649500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 438848021252 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 103695 86.94% 86.94% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 15580 13.06% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 119275 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 610901 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 314895 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 417361955272 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.556480 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.556703 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 416192825272 99.72% 99.72% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 674141500 0.16% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 223425500 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 105228000 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 86739500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 43806500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 16133000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 19234500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 421500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 417361955272 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 94420 86.78% 86.78% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 14388 13.22% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 108808 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 582230 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 610901 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 119275 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 582230 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108808 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 119275 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 730176 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108808 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 691038 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 94901630 # DTB read hits -system.cpu1.dtb.read_misses 438242 # DTB read misses -system.cpu1.dtb.write_hits 77470080 # DTB write hits -system.cpu1.dtb.write_misses 172659 # DTB write misses -system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 89807249 # DTB read hits +system.cpu1.dtb.read_misses 419450 # DTB read misses +system.cpu1.dtb.write_hits 72180592 # DTB write hits +system.cpu1.dtb.write_misses 162780 # DTB write misses +system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 42323 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 163 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7630 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 41875 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 370 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6410 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 42941 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 95339872 # DTB read accesses -system.cpu1.dtb.write_accesses 77642739 # DTB write accesses +system.cpu1.dtb.perms_faults 41502 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 90226699 # DTB read accesses +system.cpu1.dtb.write_accesses 72343372 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 172371710 # DTB hits -system.cpu1.dtb.misses 610901 # DTB misses -system.cpu1.dtb.accesses 172982611 # DTB accesses +system.cpu1.dtb.hits 161987841 # DTB hits +system.cpu1.dtb.misses 582230 # DTB misses +system.cpu1.dtb.accesses 162570071 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1826,1161 +1835,1148 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 86285 # Table walker walks requested -system.cpu1.itb.walker.walksLong 86285 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1166 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 62692 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9855 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 76430 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1337.426403 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 10105.936208 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 75617 98.94% 98.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 383 0.50% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 204 0.27% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 174 0.23% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 76430 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 73713 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 23336.867310 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 20402.005732 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19525.264050 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 72001 97.68% 97.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1393 1.89% 99.57% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 144 0.20% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 112 0.15% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 36 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 81350 # Table walker walks requested +system.cpu1.itb.walker.walksLong 81350 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 844 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59039 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9413 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 71937 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1124.310160 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8422.739912 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 71675 99.64% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 232 0.32% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 13 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-327679 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 71937 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 69296 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 22634.596514 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19851.891028 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18070.710028 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 67837 97.89% 97.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1226 1.77% 99.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 116 0.17% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 73713 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 417370190772 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.853526 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.353735 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 61155433348 14.65% 14.65% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 356194673424 85.34% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 18786000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1262500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 417370190772 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 62692 98.17% 98.17% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 1166 1.83% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 63858 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 69296 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 391589144496 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.846934 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.360225 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 59961618480 15.31% 15.31% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 331606536516 84.68% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 19274500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1690500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 24500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 391589144496 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 59039 98.59% 98.59% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 844 1.41% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 59883 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 86285 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 86285 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 81350 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 81350 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63858 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63858 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 150143 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 203133106 # ITB inst hits -system.cpu1.itb.inst_misses 86285 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59883 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59883 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 141233 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 191639831 # ITB inst hits +system.cpu1.itb.inst_misses 81350 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 30560 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 29949 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 224551 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 209776 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 203219391 # ITB inst accesses -system.cpu1.itb.hits 203133106 # DTB hits -system.cpu1.itb.misses 86285 # DTB misses -system.cpu1.itb.accesses 203219391 # DTB accesses -system.cpu1.numCycles 708901373 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 191721181 # ITB inst accesses +system.cpu1.itb.hits 191639831 # DTB hits +system.cpu1.itb.misses 81350 # DTB misses +system.cpu1.itb.accesses 191721181 # DTB accesses +system.cpu1.numCycles 657106376 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 79210227 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 569056404 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 127974219 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 77257985 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 596249525 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13297978 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1936888 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 233747 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6483042 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 760521 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 721953 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 202886748 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1527721 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 28660 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 692244892 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.964370 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.215604 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 80139865 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 537547218 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 121094303 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 72771731 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 544595085 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13230640 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1750818 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 245014 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 5964311 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 783127 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 735374 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 191409476 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1578665 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 27162 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 640828914 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.984123 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.220773 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 371999522 53.74% 53.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 125145403 18.08% 71.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 42864856 6.19% 78.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 152235111 21.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 338710091 52.85% 52.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 117550572 18.34% 71.20% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 40600676 6.34% 77.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 143967575 22.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 692244892 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.180525 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.802730 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 98103528 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 343550458 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 207545620 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 38285921 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4759365 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 18045337 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1925812 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 590182189 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 20993149 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4759365 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 132299037 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 44198902 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 235238981 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 211136719 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 64611888 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 574391592 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5359861 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9789729 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 401271 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 868513 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 28581746 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 10968 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 549201958 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 896745625 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 678703153 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 702078 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 496570478 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 52631474 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 16637084 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 14688391 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 76542594 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 94434816 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 80595349 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8923483 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7689116 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 551758554 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 16802636 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 558923093 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2479703 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 49836281 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 32327580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 272404 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 692244892 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.807407 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.056587 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 640828914 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.184284 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.818052 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 96524622 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 306596217 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 198367702 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 34666699 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4673674 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17189225 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1979171 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 555902892 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21032284 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4673674 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 128741707 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 40944507 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 207984500 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 200380023 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 58104503 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 540647070 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5273833 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8920508 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 357666 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 869250 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 25304278 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 12220 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 515542885 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 838360476 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 639083471 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 635892 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 463444914 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 52097965 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14931648 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13102843 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 69578208 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 89907304 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 75221964 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8553187 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7364919 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 519731744 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15160501 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 524719232 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2440222 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 49181333 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 32199370 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 264903 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 640828914 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.818813 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.060738 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 382813800 55.30% 55.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 135617529 19.59% 74.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 105540069 15.25% 90.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 60873310 8.79% 98.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7395424 1.07% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4760 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 351184657 54.80% 54.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 125580577 19.60% 74.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 99945390 15.60% 89.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 57229371 8.93% 98.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6884833 1.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 4086 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 692244892 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 640828914 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 54751854 43.35% 43.35% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 59874 0.05% 43.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 7206 0.01% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 22 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 34635726 27.43% 70.83% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 36835867 29.17% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 51884545 43.66% 43.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 60325 0.05% 43.71% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 6398 0.01% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 22 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 32949736 27.73% 71.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 33928397 28.55% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 22 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 381080184 68.18% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1279374 0.23% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 67457 0.01% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.42% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 77518 0.01% 68.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.44% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 97747450 17.49% 85.92% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 78671088 14.08% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 357316080 68.10% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1302107 0.25% 68.34% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 73183 0.01% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 41368 0.01% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 92637950 17.65% 86.02% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 73348522 13.98% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 558923093 # Type of FU issued -system.cpu1.iq.rate 0.788436 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 126290549 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.225953 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1937670345 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 618057050 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 542680096 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1190983 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 486822 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 443064 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 684478646 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 734974 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2497447 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 524719232 # Type of FU issued +system.cpu1.iq.rate 0.798530 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 118829423 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.226463 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1810487568 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 583794764 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 509259381 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1049453 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 417103 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 385439 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 642894662 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 653971 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2364683 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11391566 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16442 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 147287 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5480411 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11367007 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 15961 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 139264 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5290675 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2518337 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4561530 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2384785 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 4103064 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4759365 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7377288 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1779487 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 568686865 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4673674 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6987028 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1738087 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 535009487 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 94434816 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 80595349 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 14436432 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 67561 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1633321 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 147287 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1861843 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2641662 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4503505 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 551808656 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 94901612 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6513481 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 89907304 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 75221964 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12892176 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 53410 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1616074 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 139264 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1829419 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2640296 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4469715 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 517720791 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 89804186 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6423141 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 125675 # number of nop insts executed -system.cpu1.iew.exec_refs 172371354 # number of memory reference insts executed -system.cpu1.iew.exec_branches 103407043 # Number of branches executed -system.cpu1.iew.exec_stores 77469742 # Number of stores executed -system.cpu1.iew.exec_rate 0.778400 # Inst execution rate -system.cpu1.iew.wb_sent 543849746 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 543123160 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 263131919 # num instructions producing a value -system.cpu1.iew.wb_consumers 431737287 # num instructions consuming a value +system.cpu1.iew.exec_nop 117242 # number of nop insts executed +system.cpu1.iew.exec_refs 161982461 # number of memory reference insts executed +system.cpu1.iew.exec_branches 97046647 # Number of branches executed +system.cpu1.iew.exec_stores 72178275 # Number of stores executed +system.cpu1.iew.exec_rate 0.787880 # Inst execution rate +system.cpu1.iew.wb_sent 510319956 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 509644820 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 247330259 # num instructions producing a value +system.cpu1.iew.wb_consumers 405058762 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.766148 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.609472 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.775590 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610603 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 43653536 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 16530232 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4232753 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 683948716 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.758427 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.554925 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 43050408 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14895598 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4200514 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 632658676 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.767730 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.562752 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 453202569 66.26% 66.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 123078137 18.00% 84.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 49564580 7.25% 91.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 16593049 2.43% 93.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11718092 1.71% 95.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8048900 1.18% 96.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5489767 0.80% 97.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3345988 0.49% 98.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12907634 1.89% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 417403815 65.98% 65.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 113799591 17.99% 83.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 46934435 7.42% 91.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15547292 2.46% 93.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10981139 1.74% 95.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7643765 1.21% 96.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5190686 0.82% 97.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3150553 0.50% 98.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12007400 1.90% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 683948716 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 441056280 # Number of instructions committed -system.cpu1.commit.committedOps 518724902 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 632658676 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 412964348 # Number of instructions committed +system.cpu1.commit.committedOps 485710905 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 158158187 # Number of memory references committed -system.cpu1.commit.loads 83043249 # Number of loads committed -system.cpu1.commit.membars 3695786 # Number of memory barriers committed -system.cpu1.commit.branches 98284315 # Number of branches committed -system.cpu1.commit.fp_insts 431344 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 475340146 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12767541 # Number of function calls committed. +system.cpu1.commit.refs 148471585 # Number of memory references committed +system.cpu1.commit.loads 78540296 # Number of loads committed +system.cpu1.commit.membars 3510647 # Number of memory barriers committed +system.cpu1.commit.branches 92021861 # Number of branches committed +system.cpu1.commit.fp_insts 377145 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 445805015 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12220081 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 359393863 69.28% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1051243 0.20% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 53001 0.01% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 68608 0.01% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 83043249 16.01% 85.52% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 75114938 14.48% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 336089825 69.20% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1056611 0.22% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 57564 0.01% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 35320 0.01% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 78540296 16.17% 85.60% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 69931289 14.40% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 518724902 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12907634 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1229236643 # The number of ROB reads -system.cpu1.rob.rob_writes 1133012460 # The number of ROB writes -system.cpu1.timesIdled 937113 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 16656481 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 93910751930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 441056280 # Number of Instructions Simulated -system.cpu1.committedOps 518724902 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.607281 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.607281 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.622169 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.622169 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 651831389 # number of integer regfile reads -system.cpu1.int_regfile_writes 384949596 # number of integer regfile writes -system.cpu1.fp_regfile_reads 687947 # number of floating regfile reads -system.cpu1.fp_regfile_writes 437000 # number of floating regfile writes -system.cpu1.cc_regfile_reads 121245693 # number of cc regfile reads -system.cpu1.cc_regfile_writes 121813302 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1231894475 # number of misc regfile reads -system.cpu1.misc_regfile_writes 16565900 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5500590 # number of replacements -system.cpu1.dcache.tags.tagsinuse 430.004525 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 146156295 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5501102 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 26.568548 # Average number of references to valid blocks. +system.cpu1.commit.op_class_0::total 485710905 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12007400 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1145678392 # The number of ROB reads +system.cpu1.rob.rob_writes 1065656273 # The number of ROB writes +system.cpu1.timesIdled 931363 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 16277462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 93962526294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 412964348 # Number of Instructions Simulated +system.cpu1.committedOps 485710905 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.591194 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.591194 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.628459 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.628459 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 611833579 # number of integer regfile reads +system.cpu1.int_regfile_writes 362533704 # number of integer regfile writes +system.cpu1.fp_regfile_reads 622107 # number of floating regfile reads +system.cpu1.fp_regfile_writes 321740 # number of floating regfile writes +system.cpu1.cc_regfile_reads 111613116 # number of cc regfile reads +system.cpu1.cc_regfile_writes 112230966 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1145938750 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14868837 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5274603 # number of replacements +system.cpu1.dcache.tags.tagsinuse 426.947513 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 137535053 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5275114 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 26.072432 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8485200468500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.004525 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.839853 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.839853 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 388 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 327866519 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 327866519 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 76697860 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 76697860 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 64975008 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 64975008 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170492 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 170492 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 54492 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 54492 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1753772 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1753772 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1761808 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1761808 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 141672868 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 141672868 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 141843360 # number of overall hits -system.cpu1.dcache.overall_hits::total 141843360 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6400758 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6400758 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7699637 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7699637 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 744836 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 744836 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 409878 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 409878 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 258549 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 258549 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 208576 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 208576 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 14100395 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 14100395 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14845231 # number of overall misses -system.cpu1.dcache.overall_misses::total 14845231 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92687894000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 92687894000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138325220262 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 138325220262 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20294196326 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 20294196326 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4013433500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 4013433500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4392601500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4392601500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3408500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3408500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 231013114262 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 231013114262 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 231013114262 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 231013114262 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 83098618 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 83098618 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 72674645 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 72674645 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 915328 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 915328 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 464370 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 464370 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2012321 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2012321 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1970384 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1970384 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 155773263 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 155773263 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 156688591 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 156688591 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.077026 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.077026 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.105947 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.105947 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.813737 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.813737 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.882654 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.882654 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.128483 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.128483 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105856 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105856 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.090519 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.090519 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.094744 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.094744 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14480.768371 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14480.768371 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17965.161249 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17965.161249 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 49512.772889 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 49512.772889 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15522.912485 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15522.912485 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21059.956563 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21059.956563 # average StoreCondReq miss latency +system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.947513 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.833882 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.833882 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 308540922 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 308540922 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 72744707 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 72744707 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 60628902 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 60628902 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 161948 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 161948 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50338 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 50338 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1624470 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1624470 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1636906 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1636906 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 133373609 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 133373609 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 133535557 # number of overall hits +system.cpu1.dcache.overall_hits::total 133535557 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6201374 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6201374 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6969409 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6969409 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 662990 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 662990 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 447840 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 447840 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 255439 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 255439 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 200646 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 200646 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13170783 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13170783 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13833773 # number of overall misses +system.cpu1.dcache.overall_misses::total 13833773 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 88228717500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 88228717500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 123237994379 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 123237994379 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20350455489 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 20350455489 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3706894000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3706894000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4288443500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4288443500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6003000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6003000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 211466711879 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 211466711879 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 211466711879 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 211466711879 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 78946081 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 78946081 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 67598311 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 67598311 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 824938 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 824938 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 498178 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 498178 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1879909 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1879909 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837552 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1837552 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 146544392 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 146544392 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 147369330 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 147369330 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078552 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.078552 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.103100 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.103100 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.803685 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.803685 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.898956 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.898956 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135878 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135878 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.089876 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.089876 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.093871 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.093871 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14227.285356 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14227.285356 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17682.703710 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17682.703710 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45441.352914 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45441.352914 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14511.856060 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14511.856060 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21373.182122 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21373.182122 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16383.449844 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16383.449844 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15561.436145 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15561.436145 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 5682783 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 23004045 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 345925 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 792691 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 16.427789 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 29.020192 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16055.743374 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16055.743374 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15286.264411 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15286.264411 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 5662057 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 20000375 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 377912 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 710012 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 14.982475 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 28.169066 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3566261 # number of writebacks -system.cpu1.dcache.writebacks::total 3566261 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3293272 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3293272 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6267237 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 6267237 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 2938 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 2938 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 130878 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 130878 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 9560509 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 9560509 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 9560509 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 9560509 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3107486 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3107486 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1432400 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1432400 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 744751 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 744751 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 406940 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 406940 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127671 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127671 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 208566 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 208566 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4539886 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4539886 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5284637 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5284637 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 16935 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 16935 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14896 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14896 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31831 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31831 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43040497000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43040497000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26400232128 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26400232128 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15655161500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15655161500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19798456326 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19798456326 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1838541000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1838541000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4184106500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4184106500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3337500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3337500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69440729128 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 69440729128 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 85095890628 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 85095890628 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2604403500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2604403500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2300537000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2300537000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4904940500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4904940500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037395 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037395 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019710 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019710 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.813644 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.813644 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.876327 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.876327 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063445 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063445 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105850 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105850 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029144 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029144 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033727 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033727 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13850.584363 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13850.584363 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18430.768031 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18430.768031 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21020.665296 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21020.665296 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 48652.028127 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 48652.028127 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14400.615645 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14400.615645 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20061.306733 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20061.306733 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3411546 # number of writebacks +system.cpu1.dcache.writebacks::total 3411546 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3176462 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3176462 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5650771 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5650771 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3283 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3283 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 129585 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 129585 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8827233 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8827233 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8827233 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8827233 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3024912 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3024912 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1318638 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1318638 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 662904 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 662904 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 444557 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 444557 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125854 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125854 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 200639 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 200639 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4343550 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4343550 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5006454 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5006454 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6436 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6436 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6853 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6853 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 13289 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 13289 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40779010000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40779010000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24146673124 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24146673124 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13797097500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13797097500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19809664989 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19809664989 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1736527500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1736527500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4087933500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4087933500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5874000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5874000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 64925683124 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 64925683124 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 78722780624 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 78722780624 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 710484000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 710484000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 859770500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 859770500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1570254500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1570254500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.038316 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.038316 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019507 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019507 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.803580 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.803580 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.892366 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.892366 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066947 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066947 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109188 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109188 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029640 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029640 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033972 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033972 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13481.056639 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13481.056639 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18311.828663 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18311.828663 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20813.115474 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20813.115474 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44560.461288 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44560.461288 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13797.952389 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13797.952389 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20374.570746 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20374.570746 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15295.698863 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15295.698863 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16102.504416 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16102.504416 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 153788.219663 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 153788.219663 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154439.916756 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154439.916756 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 154093.195313 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 154093.195313 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14947.608091 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14947.608091 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15724.259251 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15724.259251 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110392.169049 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110392.169049 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125458.996060 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125458.996060 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 118161.976070 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 118161.976070 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5403947 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.811782 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 197154720 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5404459 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 36.480010 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 5512111 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.811781 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 185560716 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5512623 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 33.661057 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8495886874000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.811782 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.811781 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980101 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.980101 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 411165528 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 411165528 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 197154720 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 197154720 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 197154720 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 197154720 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 197154720 # number of overall hits -system.cpu1.icache.overall_hits::total 197154720 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5725810 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5725810 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5725810 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5725810 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5725810 # number of overall misses -system.cpu1.icache.overall_misses::total 5725810 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 59819230732 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 59819230732 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 59819230732 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 59819230732 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 59819230732 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 59819230732 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 202880530 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 202880530 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 202880530 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 202880530 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 202880530 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 202880530 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028223 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.028223 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028223 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.028223 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028223 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.028223 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10447.295794 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10447.295794 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10447.295794 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10447.295794 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10447.295794 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10447.295794 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 8523796 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 288 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 664103 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.835051 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 96 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 388319278 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 388319278 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 185560716 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 185560716 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 185560716 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 185560716 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 185560716 # number of overall hits +system.cpu1.icache.overall_hits::total 185560716 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5842603 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5842603 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5842603 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5842603 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5842603 # number of overall misses +system.cpu1.icache.overall_misses::total 5842603 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 60453928731 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 60453928731 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 60453928731 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 60453928731 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 60453928731 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 60453928731 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 191403319 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 191403319 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 191403319 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 191403319 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 191403319 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 191403319 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030525 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030525 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030525 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030525 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030525 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030525 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10347.088230 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10347.088230 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10347.088230 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10347.088230 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10347.088230 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10347.088230 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 8745745 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 74 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 694595 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.591143 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 74 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 321342 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 321342 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 321342 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 321342 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 321342 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 321342 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5404468 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5404468 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5404468 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5404468 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5404468 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5404468 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 329963 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 329963 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 329963 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 329963 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 329963 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 329963 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5512640 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5512640 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5512640 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5512640 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5512640 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5512640 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 54260492010 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 54260492010 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 54260492010 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 54260492010 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 54260492010 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 54260492010 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 54827935019 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 54827935019 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 54827935019 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 54827935019 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 54827935019 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 54827935019 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5791998 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5791998 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5791998 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5791998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026639 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026639 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026639 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.026639 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026639 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.026639 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10039.932147 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10039.932147 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10039.932147 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10039.932147 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10039.932147 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10039.932147 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028801 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.028801 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.028801 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9945.858068 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9945.858068 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9945.858068 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86447.731343 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86447.731343 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7840068 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7844426 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 3981 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7331800 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7336274 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 4099 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 944222 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2377748 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13486.772220 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 18876475 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2393818 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.885510 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10140216096000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5055.984886 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.053821 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 84.713714 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3027.541847 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 4406.199695 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 842.278257 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.308593 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004276 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005171 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.184786 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.268933 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051409 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.823167 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1281 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 69 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14720 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 30 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 223 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 628 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 392 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 34 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1431 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5385 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4653 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3120 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078186 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.898438 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 375099508 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 375099508 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 592978 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 185889 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 778867 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3566243 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3566243 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 83253 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 83253 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35939 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 35939 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 957303 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 957303 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4781175 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4781175 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2910784 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2910784 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 147109 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 147109 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 592978 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 185889 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4781175 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3868087 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9428129 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 592978 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 185889 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4781175 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3868087 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9428129 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12789 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9475 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 22264 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 18 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 18 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 144289 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 144289 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 172622 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 172622 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 255780 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 255780 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 623287 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 623287 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1065341 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 1065341 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 258817 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 258817 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12789 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9475 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 623287 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1321121 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1966672 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12789 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9475 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 623287 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1321121 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1966672 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 512874500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 430496500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 943371000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3103492000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 3103492000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3553775999 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3553775999 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3230499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3230499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13173602496 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 13173602496 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17677681000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 17677681000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 35240864484 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 35240864484 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 17868215998 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 17868215998 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 512874500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 430496500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17677681000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 48414466980 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 67035518980 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 512874500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 430496500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17677681000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 48414466980 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 67035518980 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 605767 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 195364 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 801131 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3566261 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3566261 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 227542 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 227542 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 208561 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 208561 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1213083 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1213083 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5404462 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 5404462 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3976125 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3976125 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 405926 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 405926 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 605767 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 195364 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5404462 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5189208 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 11394801 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 605767 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 195364 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5404462 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5189208 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 11394801 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021112 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048499 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.027791 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000005 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000005 # miss rate for Writeback accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.634120 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.634120 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.827681 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.827681 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 897950 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2207622 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13131.101294 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 18758807 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2223617 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 8.436168 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9687561014000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5032.423158 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 78.618743 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.333738 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3261.641393 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3759.864250 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 912.220012 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.307155 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004799 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005269 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199075 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229484 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055677 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.801459 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1285 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 80 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14630 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 33 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 250 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 623 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 379 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1375 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5281 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4801 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3028 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078430 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.892944 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 369655582 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 369655582 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 548671 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168948 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 717619 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3411534 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3411534 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 70189 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 70189 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33871 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 33871 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 868044 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 868044 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4905635 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4905635 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2835466 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 2835466 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 174715 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 174715 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 548671 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 168948 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4905635 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3703510 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 9326764 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 548671 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168948 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4905635 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3703510 # number of overall hits +system.cpu1.l2cache.overall_hits::total 9326764 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11848 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8514 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 20362 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 12 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 12 # number of Writeback misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139128 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 139128 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 166752 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 166752 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 16 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 16 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 247689 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 247689 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 607002 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 607002 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 976114 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 976114 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 268832 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 268832 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11848 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8514 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 607002 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1223803 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1851167 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11848 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8514 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 607002 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1223803 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1851167 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 446786000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 357242500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 804028500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2996930500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 2996930500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3475655499 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3475655499 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5675991 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5675991 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11909522998 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 11909522998 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17320734000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 17320734000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31800458472 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31800458472 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 17606608999 # number of InvalidateReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::total 17606608999 # number of InvalidateReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 446786000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 357242500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17320734000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 43709981470 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 61834743970 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 446786000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 357242500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17320734000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 43709981470 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 61834743970 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 560519 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 177462 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 737981 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3411546 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3411546 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 209317 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 209317 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 200623 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 200623 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 16 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 16 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1115733 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1115733 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5512637 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 5512637 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3811580 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 3811580 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 443547 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 443547 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 560519 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 177462 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5512637 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4927313 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 11177931 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 560519 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 177462 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 5512637 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4927313 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 11177931 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021138 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.047976 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.027591 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.664676 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.664676 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.831171 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.831171 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210851 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210851 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.115328 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.115328 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.267934 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.267934 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.637597 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.637597 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021112 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048499 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.115328 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.254590 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.172594 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021112 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048499 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.115328 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.254590 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.172594 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 40102.783642 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45434.986807 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 42372.035573 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21508.860689 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21508.860689 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20587.039885 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20587.039885 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 646099.800000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 646099.800000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51503.645696 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51503.645696 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28362.024236 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28362.024236 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 33079.421973 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 33079.421973 # average ReadSharedReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 69038.030724 # average InvalidateReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 69038.030724 # average InvalidateReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 40102.783642 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45434.986807 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28362.024236 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36646.504733 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 34085.764673 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 40102.783642 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45434.986807 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28362.024236 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36646.504733 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 34085.764673 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 3889 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.221997 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.221997 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110111 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110111 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.256092 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.256092 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.606096 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.606096 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021138 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.047976 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110111 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.248371 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.165609 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021138 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.047976 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110111 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.248371 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.165609 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37709.824443 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41959.419779 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 39486.715450 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21540.814933 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21540.814933 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20843.261244 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20843.261244 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 354749.437500 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 354749.437500 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 48082.567244 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 48082.567244 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28534.887859 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28534.887859 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32578.631668 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32578.631668 # average ReadSharedReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 65492.980743 # average InvalidateReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 65492.980743 # average InvalidateReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37709.824443 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41959.419779 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28534.887859 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35716.517667 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 33403.114884 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37709.824443 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41959.419779 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28534.887859 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35716.517667 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 33403.114884 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 2210 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 299.153846 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 170 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1147174 # number of writebacks -system.cpu1.l2cache.writebacks::total 1147174 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 177 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 180 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 16460 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 16460 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 3382 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 3382 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.writebacks::writebacks 1027358 # number of writebacks +system.cpu1.l2cache.writebacks::total 1027358 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 2 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 142 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 12070 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 12070 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 3614 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 3614 # number of ReadSharedReq MSHR hits system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 177 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 19842 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 20023 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 177 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 19842 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 20023 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12786 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9298 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 22084 # number of ReadReq MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::writebacks 18 # number of Writeback MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::total 18 # number of Writeback MSHR misses -system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 111700 # number of CleanEvict MSHR misses -system.cpu1.l2cache.CleanEvict_mshr_misses::total 111700 # number of CleanEvict MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 804888 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 804888 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 144289 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 144289 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 172622 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 172622 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 239320 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 239320 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 623286 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 623286 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 1061959 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 1061959 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 258814 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::total 258814 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12786 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9298 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 623286 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1301279 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1946649 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12786 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9298 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 623286 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1301279 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 804888 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2751537 # number of overall MSHR misses +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 2 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 142 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 15684 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 15828 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 2 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 142 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 15684 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 15828 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11846 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8372 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 20218 # number of ReadReq MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::writebacks 12 # number of Writeback MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::total 12 # number of Writeback MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 104589 # number of CleanEvict MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::total 104589 # number of CleanEvict MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 722741 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 722741 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 139128 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 139128 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 166752 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 166752 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 16 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 16 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 235619 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 235619 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 607002 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 607002 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 972500 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 972500 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 268829 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::total 268829 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11846 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8372 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 607002 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1208119 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1835339 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11846 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8372 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 607002 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1208119 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 722741 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2558080 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 16935 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17002 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14896 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14896 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6436 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6503 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 6853 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 6853 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31831 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31898 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 436116500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 365754500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 801871000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 50468745441 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 50468745441 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2875133996 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2875133996 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2601766497 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2601766497 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2804499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2804499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9250303496 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9250303496 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 13937951500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 13937951500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 28711604984 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 28711604984 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 16314942498 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 16314942498 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 436116500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 365754500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13937951500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 37961908480 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 52701730980 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 436116500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 365754500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13937951500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 37961908480 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 50468745441 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 103170476421 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 13289 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 13356 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 375677000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 300105000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 675782000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 38256632769 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 38256632769 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2790814493 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2790814493 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2566482493 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2566482493 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4901991 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4901991 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8739513998 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8739513998 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 13678722000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 13678722000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 25793385972 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 25793385972 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 15993437499 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 15993437499 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 375677000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 300105000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13678722000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34532899970 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 48887403970 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 375677000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 300105000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13678722000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34532899970 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 38256632769 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 87144036739 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5288500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2468909500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2474198000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2188801500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2188801500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 658981000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 664269500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 808356000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 808356000 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5288500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 4657711000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 4662999500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021107 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.047593 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027566 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000005 # mshr miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000005 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1467337000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1472625500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021134 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.047176 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027396 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.634120 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.634120 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827681 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.827681 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.664676 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.664676 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.831171 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.831171 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.197282 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.197282 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.115328 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.115328 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.267084 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.267084 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.637589 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.637589 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021107 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047593 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.115328 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250766 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170837 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021107 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047593 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.115328 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250766 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.211179 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.211179 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.110111 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110111 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255144 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255144 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.606089 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.606089 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021134 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047176 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.110111 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245188 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.164193 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021134 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047176 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.110111 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245188 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.241473 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 36310.043470 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62702.817586 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19926.217494 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19926.217494 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15072.044681 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15072.044681 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 560899.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 560899.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 38652.446498 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 38652.446498 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22362.048081 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22362.048081 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27036.453370 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27036.453370 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63037.326026 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63037.326026 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22362.048081 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29172.766547 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27073.052707 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22362.048081 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29172.766547 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37495.580260 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228851 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33424.770007 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52932.700330 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 52932.700330 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20059.330207 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20059.330207 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15391.014758 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15391.014758 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 306374.437500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 306374.437500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37091.720099 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37091.720099 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22534.887859 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22534.887859 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26522.761925 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26522.761925 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 59492.976944 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 59492.976944 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22534.887859 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28584.021913 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26636.716143 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22534.887859 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28584.021913 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52932.700330 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34066.188993 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145787.392973 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 145523.938360 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146938.876208 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146938.876208 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102389.838409 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102148.162387 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117956.515395 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117956.515395 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 146326.254280 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 146184.698100 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 110417.412898 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 110259.471399 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 997626 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10426628 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38204 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 14896 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 7712009 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 10305258 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1022601 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 482744 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 380034 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 500528 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 136 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1988029 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1220428 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5404468 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6543941 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 512654 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 405926 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16212466 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17789160 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 422162 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1316947 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 35740735 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 345886640 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 566771243 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1562912 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4846136 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 919066931 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 12378423 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 35388761 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.367817 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.482211 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 950963 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10318053 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6853 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 7301053 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 10168977 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 922205 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 460948 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 364065 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 477238 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 134 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1860044 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1122762 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5512640 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6310959 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 550275 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 443547 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16537003 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17033306 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 391276 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1237529 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 35199114 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 352809840 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 540363378 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1419696 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4484152 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 899077066 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 11781593 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 34442064 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.358530 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.479569 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 22372180 63.22% 63.22% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 13016581 36.78% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 22093559 64.15% 64.15% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 12348505 35.85% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 35388761 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 15228808958 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 34442064 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 14907193441 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 179948989 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 189176968 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8110869278 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8273171683 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8234240098 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7832975507 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 227095399 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 214052518 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 711723893 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 677527956 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40342 # Transaction distribution -system.iobus.trans_dist::ReadResp 40342 # Transaction distribution -system.iobus.trans_dist::WriteReq 136642 # Transaction distribution -system.iobus.trans_dist::WriteResp 136642 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47708 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40376 # Transaction distribution +system.iobus.trans_dist::ReadResp 40376 # Transaction distribution +system.iobus.trans_dist::WriteReq 136648 # Transaction distribution +system.iobus.trans_dist::WriteResp 136648 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47800 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2990,18 +2986,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122642 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231246 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231246 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122682 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231286 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353968 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47728 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47820 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3011,18 +3007,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155749 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339000 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339000 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155812 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496835 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36238000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7497058 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36303000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -3042,7 +3038,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -3050,71 +3046,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 569545477 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 569813871 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92731000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92765000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147942000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147982000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115612 # number of replacements -system.iocache.tags.tagsinuse 11.307418 # Cycle average of tags in use +system.iocache.tags.replacements 115623 # number of replacements +system.iocache.tags.tagsinuse 11.307008 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115639 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9081354759000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.848836 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.458583 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 9081350424000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.848834 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.458174 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.240552 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466161 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706714 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466136 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706688 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040964 # Number of tag accesses -system.iocache.tags.data_accesses 1040964 # Number of data accesses +system.iocache.tags.tag_accesses 1041144 # Number of tag accesses +system.iocache.tags.data_accesses 1041144 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8895 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8932 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8915 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8952 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8895 # number of demand (read+write) misses -system.iocache.demand_misses::total 8935 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8915 # number of demand (read+write) misses +system.iocache.demand_misses::total 8955 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8895 # number of overall misses -system.iocache.overall_misses::total 8935 # number of overall misses +system.iocache.overall_misses::realview.ide 8915 # number of overall misses +system.iocache.overall_misses::total 8955 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1662593136 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1667788136 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1625113033 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1630308033 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12635360341 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12635360341 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12635282838 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12635282838 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1662593136 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1668157136 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1625113033 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1630677033 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1662593136 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1668157136 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1625113033 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1630677033 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8895 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8932 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8915 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8952 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8895 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8935 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8915 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8955 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8895 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8935 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8915 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8955 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3129,54 +3125,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186913.224958 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 186720.570533 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182289.740101 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182116.625670 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118388.429850 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118388.429850 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118387.703677 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118387.703677 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 186913.224958 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 186699.175825 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182289.740101 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 182096.821106 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 186913.224958 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 186699.175825 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32654 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 182289.740101 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 182096.821106 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 30957 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3383 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3475 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.652380 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.908489 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106702 # number of writebacks -system.iocache.writebacks::total 106702 # number of writebacks +system.iocache.writebacks::writebacks 106693 # number of writebacks +system.iocache.writebacks::total 106693 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8895 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8932 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8915 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8952 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8895 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8935 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8915 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8955 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8895 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8935 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8915 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8955 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1217843136 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1221188136 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1179363033 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1182708033 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7298960341 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7298960341 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7298882838 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7298882838 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1217843136 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1221407136 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1179363033 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1182927033 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1217843136 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1221407136 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1179363033 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1182927033 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3191,614 +3187,623 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136913.224958 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136720.570533 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132289.740101 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 132116.625670 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68388.429850 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68388.429850 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68387.703677 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68387.703677 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 136913.224958 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 136699.175825 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 132289.740101 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 132096.821106 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 136913.224958 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 136699.175825 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 132289.740101 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 132096.821106 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1760747 # number of replacements -system.l2c.tags.tagsinuse 63871.601453 # Cycle average of tags in use -system.l2c.tags.total_refs 6095006 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1821172 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.346749 # Average number of references to valid blocks. +system.l2c.tags.replacements 1604376 # number of replacements +system.l2c.tags.tagsinuse 63973.571253 # Cycle average of tags in use +system.l2c.tags.total_refs 5805157 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1664778 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.487046 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 18326.572985 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 182.034797 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 268.280441 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4619.393037 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9002.087865 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11374.868707 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 179.474155 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 242.215899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2745.232497 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8268.941513 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8662.499555 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.279641 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002778 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004094 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.137361 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.173567 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002739 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003696 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.041889 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.126174 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.132179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.974603 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11384 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 237 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48804 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1357 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 826 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9193 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 233 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2623 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5288 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 40501 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.173706 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003616 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.744690 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 76795315 # Number of tag accesses -system.l2c.tags.data_accesses 76795315 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2680735 # number of Writeback hits -system.l2c.Writeback_hits::total 2680735 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 32943 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 31048 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 63991 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6336 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5767 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12103 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 174506 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 154775 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 329281 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6806 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4586 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 614111 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 638498 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 286433 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6534 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4346 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 583459 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 618336 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 287570 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3050679 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6806 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4586 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 614111 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 813004 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 286433 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6534 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 583459 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 773111 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 287570 # number of demand (read+write) hits -system.l2c.demand_hits::total 3379960 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6806 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4586 # number of overall hits -system.l2c.overall_hits::cpu0.inst 614111 # number of overall hits -system.l2c.overall_hits::cpu0.data 813004 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 286433 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6534 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4346 # number of overall hits -system.l2c.overall_hits::cpu1.inst 583459 # number of overall hits -system.l2c.overall_hits::cpu1.data 773111 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 287570 # number of overall hits -system.l2c.overall_hits::total 3379960 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 48112 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 44467 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 92579 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 10023 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 8706 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 18729 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 523780 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 170521 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 694301 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2882 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2624 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 74362 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 179746 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 302363 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2755 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2528 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 39827 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 128012 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 323843 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 1058942 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2882 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2624 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 74362 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 703526 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 302363 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2755 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2528 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 39827 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 298533 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 323843 # number of demand (read+write) misses -system.l2c.demand_misses::total 1753243 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2882 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2624 # number of overall misses -system.l2c.overall_misses::cpu0.inst 74362 # number of overall misses -system.l2c.overall_misses::cpu0.data 703526 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 302363 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2755 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2528 # number of overall misses -system.l2c.overall_misses::cpu1.inst 39827 # number of overall misses -system.l2c.overall_misses::cpu1.data 298533 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 323843 # number of overall misses -system.l2c.overall_misses::total 1753243 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 280230500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 263754000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 543984500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 55711000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 50228500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 105939500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 68581440500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 18910817992 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 87492258492 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 268423000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 251208500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6463422502 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 17884384500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 42388472929 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 254889500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 239052000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3438315000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 12527996000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 45486797416 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 129202961347 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 268423000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 251208500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 6463422502 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 86465825000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 42388472929 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 254889500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 239052000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3438315000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 31438813992 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 45486797416 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 216695219839 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 268423000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 251208500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 6463422502 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 86465825000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 42388472929 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 254889500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 239052000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3438315000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 31438813992 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 45486797416 # number of overall miss cycles -system.l2c.overall_miss_latency::total 216695219839 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 2680735 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2680735 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 81055 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 75515 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 156570 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 16359 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 14473 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 30832 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 698286 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 325296 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1023582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9688 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7210 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 688473 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 818244 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 588796 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9289 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6874 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 623286 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 746348 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 611413 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 4109621 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9688 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7210 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 688473 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1516530 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 588796 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9289 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6874 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 623286 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1071644 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 611413 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 5133203 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9688 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7210 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 688473 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1516530 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 588796 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9289 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6874 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 623286 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1071644 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 611413 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 5133203 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.593572 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.588850 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.591295 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.612690 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.601534 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.607453 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.750094 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.524203 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.678305 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.297481 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.363939 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.108010 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.219673 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.513528 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.296587 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.367763 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.063898 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.171518 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.529663 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.257674 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.297481 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.363939 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.108010 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.463905 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.513528 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.296587 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.367763 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.063898 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.278575 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.529663 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.341550 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.297481 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.363939 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.108010 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.463905 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.513528 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.296587 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.367763 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.063898 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.278575 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.529663 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.341550 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5824.544812 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5931.454787 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5875.895181 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5558.315873 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5769.411900 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5656.441882 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 130935.584597 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 110900.229250 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 126014.881862 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 93137.751561 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 95734.946646 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 86918.352142 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 99498.094533 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92518.874773 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 94561.708861 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86331.257690 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97865.793832 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 122011.367334 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93137.751561 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 95734.946646 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 86918.352142 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 122903.524532 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92518.874773 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 94561.708861 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 86331.257690 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 105311.017516 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 123596.797386 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93137.751561 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 95734.946646 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 86918.352142 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 122903.524532 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92518.874773 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 94561.708861 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 86331.257690 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 105311.017516 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 123596.797386 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 12094 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 16659.203027 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 347.238411 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 480.079854 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4726.149973 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 13722.940289 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 19518.694683 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 39.930664 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 37.878689 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2515.843694 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3528.824222 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2396.787747 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.254199 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.005298 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.007325 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.072115 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.209395 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.297832 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000609 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000578 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.038389 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.053846 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036572 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.976159 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10879 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49303 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1360 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 633 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 8884 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 213 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2421 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4883 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 41670 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.166000 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.752304 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 72712060 # Number of tag accesses +system.l2c.tags.data_accesses 72712060 # Number of data accesses +system.l2c.Writeback_hits::writebacks 2536205 # number of Writeback hits +system.l2c.Writeback_hits::total 2536205 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 30090 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 27013 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 57103 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 6458 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 6165 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 12623 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 162036 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 153866 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 315902 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6626 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4489 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 594958 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 614676 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 296621 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6612 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4192 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 566970 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 555261 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 284702 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2935107 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6626 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4489 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 594958 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 776712 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 296621 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6612 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4192 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 566970 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 709127 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 284702 # number of demand (read+write) hits +system.l2c.demand_hits::total 3251009 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6626 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4489 # number of overall hits +system.l2c.overall_hits::cpu0.inst 594958 # number of overall hits +system.l2c.overall_hits::cpu0.data 776712 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 296621 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6612 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4192 # number of overall hits +system.l2c.overall_hits::cpu1.inst 566970 # number of overall hits +system.l2c.overall_hits::cpu1.data 709127 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 284702 # number of overall hits +system.l2c.overall_hits::total 3251009 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 47588 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 43593 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 91181 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 9906 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 10331 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 20237 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 509249 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 164886 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 674135 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2732 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2383 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 65927 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 171520 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 297602 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2128 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1988 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 40032 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 112082 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 243379 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 939773 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2732 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2383 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 65927 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 680769 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 297602 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2128 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1988 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 40032 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 276968 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 243379 # number of demand (read+write) misses +system.l2c.demand_misses::total 1613908 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2732 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2383 # number of overall misses +system.l2c.overall_misses::cpu0.inst 65927 # number of overall misses +system.l2c.overall_misses::cpu0.data 680769 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 297602 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2128 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1988 # number of overall misses +system.l2c.overall_misses::cpu1.inst 40032 # number of overall misses +system.l2c.overall_misses::cpu1.data 276968 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 243379 # number of overall misses +system.l2c.overall_misses::total 1613908 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 285345500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 229148000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 514493500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 53588000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 57099500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 110687500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 66726621996 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 17979484499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 84706106495 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 253095500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 219982000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5658543002 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 16552075998 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 41040485814 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 202746500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 183043000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3466352000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 10969692499 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 33324994201 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 111871010514 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 253095500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 219982000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 5658543002 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 83278697994 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 41040485814 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 202746500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 183043000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3466352000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 28949176998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 33324994201 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 196577117009 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 253095500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 219982000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 5658543002 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 83278697994 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 41040485814 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 202746500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 183043000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3466352000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 28949176998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 33324994201 # number of overall miss cycles +system.l2c.overall_miss_latency::total 196577117009 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 2536205 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2536205 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 77678 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 70606 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 148284 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 16364 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 16496 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 32860 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 671285 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 318752 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 990037 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9358 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6872 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 660885 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 786196 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 594223 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8740 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6180 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 607002 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 667343 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 528081 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 3874880 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6872 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 660885 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1457481 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 594223 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 8740 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6180 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 607002 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 986095 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 528081 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4864917 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6872 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 660885 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1457481 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 594223 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 8740 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6180 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 607002 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 986095 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 528081 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4864917 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.612632 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.617412 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.614908 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.605353 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.626273 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.615855 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.758618 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.517286 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.680919 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.291943 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.346769 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.099756 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.218164 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.500825 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.243478 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.321683 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.065950 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.167953 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.460874 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.242530 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.291943 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.346769 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.099756 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.467086 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.500825 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.243478 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.321683 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.065950 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.280874 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.460874 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.331744 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.291943 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.346769 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.099756 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.467086 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.500825 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.243478 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.321683 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.065950 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.280874 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.460874 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.331744 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5996.165000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5256.532012 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5642.551628 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5409.650717 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5527.006098 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5469.560706 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 131029.461022 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109041.910769 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 125651.548273 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 92641.105417 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92313.050776 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85830.433692 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 96502.308757 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 137903.931472 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 95275.610902 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92073.943662 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86589.528377 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97872.026722 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136926.333829 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 119040.460318 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92641.105417 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92313.050776 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 85830.433692 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 122330.332307 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 137903.931472 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 95275.610902 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92073.943662 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 86589.528377 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 104521.738966 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136926.333829 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 121801.934812 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92641.105417 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92313.050776 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 85830.433692 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 122330.332307 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 137903.931472 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 95275.610902 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92073.943662 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 86589.528377 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 104521.738966 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136926.333829 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 121801.934812 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 7662 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 115 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 92 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 105.165217 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 83.282609 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1358225 # number of writebacks -system.l2c.writebacks::total 1358225 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 229 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.data 34 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 211 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.data 37 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 511 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 229 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 34 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 211 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 37 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 511 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 229 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 34 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 211 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 37 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 511 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 57055 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 57055 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 48112 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 44467 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 92579 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10023 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8706 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 18729 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 523780 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 170521 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 694301 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2882 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2624 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 74133 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 179712 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 302363 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2755 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2528 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 39616 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 127975 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 323843 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 1058431 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 2882 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2624 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 74133 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 703492 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 302363 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2755 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2528 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 39616 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 298496 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 323843 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 1752732 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 2882 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2624 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 74133 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 703492 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 302363 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2755 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2528 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 39616 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 298496 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 323843 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 1752732 # number of overall MSHR misses +system.l2c.writebacks::writebacks 1246552 # number of writebacks +system.l2c.writebacks::total 1246552 # number of writebacks +system.l2c.ReadExReq_mshr_hits::cpu0.data 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 3 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 217 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 87 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 35 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 178 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 73 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 598 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 217 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 90 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 35 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 178 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 73 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 601 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 217 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 90 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 35 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 178 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 73 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 601 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 52518 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 52518 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 47588 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 43593 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 91181 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9906 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10331 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 20237 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 509246 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 164886 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 674132 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2732 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2383 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 65710 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 171433 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 297567 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2128 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1988 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 39854 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 112009 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 243371 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 939175 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 2732 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2383 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 65710 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 680679 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 297567 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2128 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1988 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 39854 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 276895 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 243371 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1613307 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 2732 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2383 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 65710 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 680679 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 297567 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2128 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1988 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 39854 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 276895 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 243371 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1613307 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 21352 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32342 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16933 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 59646 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 23308 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14896 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 38204 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6434 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 60137 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31823 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 6853 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38676 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 44660 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 64165 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31829 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 97850 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1000759503 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 924536001 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1925295504 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 208161502 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 180991502 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 389153004 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 63343640500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 17205607992 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 80549248492 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 239603000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 224968500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5703318002 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 16083965000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 39364842929 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 227339500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 213772000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3027081000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 11244495000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 42248367416 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 118577752347 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 239603000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 224968500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 5703318002 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 79427605500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 39364842929 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 227339500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 213772000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3027081000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 28450102992 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 42248367416 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 199127000839 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 239603000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 224968500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 5703318002 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 79427605500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39364842929 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 227339500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 213772000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3027081000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 28450102992 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 42248367416 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 199127000839 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 13287 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 98813 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 990436504 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 906238506 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1896675010 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 205762002 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 214626501 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 420388503 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 61634019996 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 16330624499 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 77964644495 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 225775500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 196152000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4984045002 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14830916998 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38062777880 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 181466500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 163163000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3054573000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 9843412999 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 30890783215 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 102433066094 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 225775500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 196152000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 4984045002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 76464936994 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 38062777880 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 181466500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 163163000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3054573000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 26174037498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 30890783215 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 180397710589 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 225775500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 196152000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 4984045002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 76464936994 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38062777880 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 181466500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 163163000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3054573000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 26174037498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30890783215 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 180397710589 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1320748000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3340995000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4976486500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4081500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2164071000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6829895500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3477095533 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1935550000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5412645533 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 543120500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6844436500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4733537033 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 691840500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5425377533 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1320748000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6818090533 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9710023533 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4081500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4099621000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 12242541033 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1234961000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 12269814033 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.593572 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.588850 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.591295 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.612690 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.601534 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.607453 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.750094 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.524203 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.678305 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.297481 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.363939 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.107677 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.219631 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.513528 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.296587 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.367763 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.063560 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.171468 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529663 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.257550 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.297481 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.363939 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.107677 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.463883 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.513528 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.296587 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.367763 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.063560 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.278540 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529663 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.341450 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.297481 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.363939 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.107677 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.463883 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.513528 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.296587 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.367763 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.063560 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.278540 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529663 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.341450 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20800.621529 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.508332 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20796.244332 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20768.382919 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20789.283483 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20778.098350 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120935.584597 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 100900.229250 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 116014.881862 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76933.592354 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 89498.558805 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76410.566438 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87864.778277 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112031.632054 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76933.592354 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 112904.774326 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76410.566438 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95311.504985 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 113609.496968 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76933.592354 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 112904.774326 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76410.566438 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95311.504985 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 113609.496968 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.612632 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.617412 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.614908 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.605353 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.626273 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.615855 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.758614 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.517286 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.680916 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.291943 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.346769 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.099427 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.218054 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.500767 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.243478 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.321683 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.065657 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.167843 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.460859 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.242375 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.291943 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.346769 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.099427 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.467024 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.500767 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.243478 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.321683 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.065657 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.280800 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.460859 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.331621 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.291943 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.346769 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.099427 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.467024 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.500767 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.243478 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.321683 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.065657 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.280800 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.460859 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.331621 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20812.736488 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20788.624458 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20801.208695 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20771.451847 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20774.997677 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20773.261995 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 121029.954081 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99041.910769 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 115651.896802 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75849.109755 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 86511.447609 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76644.075877 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87880.554232 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109067.070667 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75849.109755 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 112336.265691 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76644.075877 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94526.941613 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 111818.587900 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75849.109755 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 112336.265691 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76644.075877 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94526.941613 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 111818.587900 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156472.227426 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153870.709913 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127801.984291 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 114507.184053 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149180.347220 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 129937.567132 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141677.456104 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84414.128070 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 113814.066215 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148745.782390 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100954.399533 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 140277.627805 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152666.603963 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151328.972695 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 128801.438939 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 125115.391242 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 92945.059080 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 124172.062714 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 59646 # Transaction distribution -system.membus.trans_dist::ReadResp 1127009 # Transaction distribution -system.membus.trans_dist::WriteReq 38204 # Transaction distribution -system.membus.trans_dist::WriteResp 38204 # Transaction distribution -system.membus.trans_dist::Writeback 1464927 # Transaction distribution -system.membus.trans_dist::CleanEvict 280718 # Transaction distribution -system.membus.trans_dist::UpgradeReq 444619 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 331926 # Transaction distribution -system.membus.trans_dist::UpgradeResp 118163 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 708914 # Transaction distribution -system.membus.trans_dist::ReadExResp 687449 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1067363 # Transaction distribution +system.membus.trans_dist::ReadReq 60137 # Transaction distribution +system.membus.trans_dist::ReadResp 1008264 # Transaction distribution +system.membus.trans_dist::WriteReq 38676 # Transaction distribution +system.membus.trans_dist::WriteResp 38676 # Transaction distribution +system.membus.trans_dist::Writeback 1353245 # Transaction distribution +system.membus.trans_dist::CleanEvict 256072 # Transaction distribution +system.membus.trans_dist::UpgradeReq 446472 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 317458 # Transaction distribution +system.membus.trans_dist::UpgradeResp 117838 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.membus.trans_dist::ReadExReq 689582 # Transaction distribution +system.membus.trans_dist::ReadExResp 667715 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 948127 # Transaction distribution system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122682 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6087631 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6235467 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342027 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342027 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6577494 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155749 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27002 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5660502 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5810264 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342643 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342643 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6152907 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155812 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 198978048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 199184601 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7249472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7249472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 206434073 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 682959 # Total snoops (count) -system.membus.snoop_fanout::samples 4505681 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54004 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 182936448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 183146836 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7268096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190414932 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 670794 # Total snoops (count) +system.membus.snoop_fanout::samples 4218827 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4505681 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4218827 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4505681 # Request fanout histogram -system.membus.reqLayer0.occupancy 98301494 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4218827 # Request fanout histogram +system.membus.reqLayer0.occupancy 97993999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21116985 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22746984 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 10136025529 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9381331556 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9507659574 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8783305125 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 229108938 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229295864 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3842,60 +3847,60 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 59648 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5069827 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38204 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38204 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 4145743 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1638680 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 501758 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 344029 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 845787 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 136 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 136 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1170821 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1170821 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 5017419 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 60139 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4816420 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38676 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3889503 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1527175 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 497158 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 330081 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 827239 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 247 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1142368 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1142368 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4763508 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9001938 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7449274 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16451212 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 278573838 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 222195147 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 500768985 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3698425 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 14333755 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.138980 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.345926 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8767118 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6899331 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15666449 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 271825986 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202528722 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 474354708 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3515812 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 13605383 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.134927 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.341646 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 12341651 86.10% 86.10% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1992104 13.90% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 11769647 86.51% 86.51% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1835736 13.49% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 14333755 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9346036195 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 13605383 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8891301093 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2541000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2589000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5271518855 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5132723331 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4504542320 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4211299918 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4738 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 14670 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14252 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 7288 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |